JP3001574B1 - First in first out memory device - Google Patents

Abstract

Abstract: PROBLEM TO BE SOLVED: To prevent transfer of error data and reduce the buffer amount even when the data length of one packet changes for each packet and the speeds on the input side and output side are slightly different. A first-in first-out memory device is provided. SOLUTION: In a first-in first-out memory device, a frequency detection / comparison circuit 6 for comparing a write speed and a read speed of a data holding buffer 2 before data writing is performed, and a write address at which writing of the data holding buffer 2 is performed. Address difference detecting means for detecting an address difference between the read address and a read address at which reading is performed. Further, when the write speed is higher than the read speed, the address difference reaches a first value.When the read speed is higher than the write speed, the address difference reaches a second value. A read enable selection circuit 1 for starting data reading is provided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a first-in first-out memory device used for transferring data between clusters of computers connected in parallel, and more particularly to a first-in-first-out memory device for preventing transfer of error data.

[0002]

2. Description of the Related Art A first-in first-out memory device (hereinafter, FIFO device) is used as a relay device between data transfer devices specified by a communication protocol. This F
The IFO device is used for data transfer (packet transfer) particularly when the speed difference between the transmission side and the reception side slightly changes. The data holding buffer amount (depth of memory) of the FIFO device is determined by the maximum data length (maximum packet length) specified by the protocol. Has a margin defined, and the speed may change within the range of the maximum speed and the minimum speed. As described above, in the case where the speeds of the input side and the output side are different in the packet transfer device, a method of absorbing the difference in data transfer speed using a FIFO device is generally adopted.

[0003] In a FIFO device, there is a FIFO device which informs an external input side and / or an output side of a data holding amount stored in a memory by a flag and stops writing and / or reading to absorb a speed difference. Since the clock of the packet transfer device does not stop, when such a FIFO device is used in the packet transfer device, a margin is set in the storage capacity (depth of the memory) of the data holding buffer provided in the FIFO device. That is, it is necessary to absorb the speed difference by providing an extra storage capacity.

FIG. 9 is a block diagram showing a configuration of a conventional FIFO device. The conventional FIFO device is provided with a data holding buffer 22 for holding data input from a data input line 31. This data holding buffer 2
2 is output to the data output line 32. Further, a write address generation circuit 23 for specifying a write address of the data holding buffer 22 and a read address generation circuit 24 for specifying a read address of the data holding buffer 22 are provided. Further, various flag generation circuits 21 for calculating the data holding amount of the data holding buffer 22 from the output values of both address generation circuits 23 and 24
Is provided. The write address generation circuit 23 and the read address generation circuit 24 are composed of a counter and the like.

A write request (enable) signal and a write clock signal are externally input to a data holding buffer 22 and a write address generation circuit 23,
A read request (enable) signal and a read clock signal are externally input to the data holding buffer 22 and the read address generation circuit 24. Further, a reset signal for initializing both address generation circuits 23 and 24 is input to both address generation circuits 23 and 24, and various flag signals indicating the data holding amount to the outside are output from various flag generation circuits 21 to the outside. .

In the conventional FIFO device configured as described above, first, both address generation circuits 23 and 24 are initialized by a reset signal, and address 0 of the data holding buffer 22 is designated.

At the time of data writing, the write address generation circuit 23 specifies write addresses WA in order from address 0 based on a write request signal and a write clock, and writes the addresses to a data holding buffer specified by the write address WA. Write input data from the data input line.

When data is read after the data is written, the read address generation circuit 24 specifies the read addresses RA in order from address 0 based on the read request signal and the read clock, and specifies the read addresses RA by the read address RA. Data is output from the address of the data holding buffer to the data output line.

Further, the various flag generation circuits 21 calculate the remaining amount of the data holding buffer 22 from the values of the write address WA and the read address RA, and output a state such as full, empty or half to the outside, and output an error. Block data output.

In such a conventional FIFO device,
For example, the frequency of the write clock signal and the read clock signal is 50 ± 1 MHz, and the maximum packet length is 102
In the case of 4 bytes, a memory depth of 84 stages is required according to the following estimation. That is, a storage capacity of 84 bytes is required.

When the write speed is higher than the read speed, for example, the frequency of the write clock signal is 49 MHz.
When z (period: 20.4 nsec) and the frequency of the read clock signal is 51 MHz (period: 19.6 nsec), the time required to write 1024 bytes of data is 20.4 nsec × 1024 The time required for reading out 1024 bytes of data is 20.07 μsec from 19.6 nsec × 1024. Therefore, in this case, the depth of the memory required to absorb the speed difference is 42 steps from ((write time)-(read time)) / (read cycle).

When the writing speed is lower than the reading speed, for example, when the frequency of the writing clock signal is 51
When the frequency of the read clock signal is 49 MHz (period: 20.4 ns), the time required to write 1024 bytes of data is 19.6 ns × 1024. The time required to read 1024 bytes of data is 20.88 μsec from 20.4 nsec × 1024. Therefore, in this case, the depth of the memory required to absorb the speed difference is -42 steps from ((write time)-(read time)) / (read cycle).

From these results, in order to prevent the write from overtaking the read and the read from overtaking the write, since the read start threshold value is one, the time when 42 bytes of data are written is It is necessary to set the depth of the memory of the time difference in the above two cases. For this reason, a memory depth of 84 stages is required, and the threshold value for starting reading is 42.

Further, recently, the data scale of one packet has become large, and the storage capacity of the data holding buffer has increased, and the amount of hardware of the FIFO device has been increasing. Is beginning to be hindered. Therefore, it is required to reduce the amount of hardware in the device.

In order to meet this demand, for example, as disclosed in Japanese Patent Application Laid-Open No. 9-190334, the frequency difference is absorbed by increasing or decreasing the frame interval at the time of data output, and the data difference is absorbed by a small data holding buffer amount. It has been proposed to implement the transfer. FIG.
FIG. 1 is a schematic diagram illustrating a configuration of a conventional FIFO device described in Japanese Patent No. 90334.

The conventional FIFO device described in Japanese Patent Application Laid-Open No. 9-190334 is provided with a data holding buffer 42 for holding data input from a data input line 51. The data held from the data holding buffer 42 is output to the data output line 52. A write address generation circuit 43 for designating a write address of the data holding buffer 42 and a data holding buffer 42
Read address generation circuit 4 for specifying the read address of
4 are provided. Further, there is provided an address comparison circuit 45 which compares an output value from the write address generation circuit 43 with an output value from the read address generation circuit 44 and outputs a signal according to the comparison result. Furthermore, a write counter 47 for counting up the write clock, a read counter 48 for counting up the read clock, and a counter value comparison circuit 49 for comparing the counter values of both counters 47 and 48 are provided. The write address generation circuit 43, the read address generation circuit 44, the address comparison circuit 45, the write counter 47, the read counter 48, and the counter value comparison circuit 49 constitute a frequency comparison circuit 46 for comparing the write clock signal with the output clock signal. Have been.

Then, the write address generation circuit 43,
Read address generation circuit 44, address comparison circuit 45
And a read enable control circuit 41 for outputting a read enable signal based on an output signal from the counter value comparison circuit 49, and a logical product of the read enable signal output from the read enable control circuit 41 and the output side clock signal. AND circuit AND which takes the following is provided.

FIG. 11 is a block diagram showing a configuration of a read enable control circuit 41 in a conventional FIFO device described in Japanese Patent Application Laid-Open No. 9-190334. The read enable control circuit 41 receives a write address and a read address, and detects whether data has been written to the data holding buffer 42.
A read enable generation circuit 41b for generating a read enable signal for a frame length is provided. Also, 1 or 2 from the read enable generation circuit 41b
A first frame interval selection circuit 41c for selecting one or two bits of a frame interval based on the bit output signal and the output signal from the address comparison circuit 45;
Further, based on the output signal from the first frame interval selection circuit 41c and the output signal from the counter value comparison circuit 49, a second, which selects 0, 1, or 2 bits of the frame interval.
A frame interval selection circuit 41d is provided.

FIG. 12A is a schematic diagram showing input data, FIG. 12B is a schematic diagram showing data output when the write speed is the same as the read speed, and FIG. 12C is a schematic diagram showing the write speed. FIG. 4D is a schematic diagram illustrating data output when the read speed is higher than the write speed, and FIG. 4D is a schematic diagram illustrating data output when the read speed is higher than the write speed.

In the conventional FIFO device described in Japanese Patent Application Laid-Open No. 9-190334, when the writing speed is the same as the reading speed, as shown in FIGS. And the output data match.

On the other hand, when the writing speed is higher than the reading speed, when the output value of the writing counter 47 and the output value of the reading counter 48 are shifted by 2 bits, the data shown in FIG.
As shown in (c), the frame interval (idle period) i
Is 0 bits. This prevents data overflow. When the read speed is higher than the write speed, when the difference between the write address value and the read address value becomes 1, the frame interval i is set to 2 bits as shown in FIG. . This allows
Data underflow is prevented. Therefore, the capacity of the data holding buffer can be reduced.

[0022]

However, according to the above-mentioned Japanese Patent Application Laid-Open No. 9-190334, although the intended purpose has been achieved, FIGS. 12 (a), (c) and (d) As shown in (1), when the read speed and the write speed are different, there is a problem that data different from the format of the input data is output. In the packet transfer, since the packet is recognized based on the packet and the frame interval of the packet, FIG.
As shown in (2), when the frame interval i is lost, there is also a problem that the packet is not recognized.

Further, the conventional FIFO device described in Japanese Patent Application Laid-Open No. 9-190334 is applied to data transfer of a fixed frame length. Since the read enable signal is output, if the data length of the frame is not constant, extra error data other than the frame is transferred.

The present invention has been made in view of such a problem. Even when the data length of one packet changes for each packet and the speeds on the input side and the output side are slightly different, error data can be obtained. It is an object of the present invention to provide a first-in first-out memory device that can prevent transfer of data and reduce the amount of buffer.

[0025]

According to a first-in first-out memory device according to the present invention, a data holding buffer for storing data and a writing speed and a reading speed of the data holding buffer are controlled by writing data to the data holding buffer. Speed comparison means for comparing before the read operation, address difference detection means for detecting an address difference between a write address at which data is written to the data holding buffer and a read address at which data is read, and wherein the write speed is higher than the read speed. When fast, the address difference is the first
The reading of the data stored in the data holding buffer is started when the value reaches the value, and when the reading speed is higher than the writing speed, the address difference becomes the second.
Read control means for starting reading of data stored in the data holding buffer when the value of
It is characterized by having.

In the present invention, when the write speed is higher than the read speed by the read control means, the reading of the data stored in the data holding buffer is started when the address difference reaches the first value, and the read speed is reduced. When the writing speed is higher than the writing speed, the reading is started when the address difference reaches the second value. Therefore, even if the writing speed or the reading speed is higher,
The speed difference is absorbed, and the transfer of error data is prevented.
For this reason, no extra capacity is required for the data holding buffer, and the conventional FIFO in which the read threshold is fixed is used.
The amount of memory is reduced as compared with the device.

In this embodiment, the read control means can terminate the reading of the data stored in the data holding buffer when the address difference becomes zero.

Further, the speed comparing means includes a write frequency detecting circuit for detecting a frequency of a write clock signal for setting a data write timing to the data holding buffer, and a read for setting a data read timing from the data holding buffer. A read frequency detection circuit that detects a frequency of a clock signal, and a frequency comparison circuit that compares an output signal from the write frequency detection circuit with an output signal from the read frequency detection circuit can be provided.

Further, the address difference detecting means includes a write address generating circuit for incrementing the write address for each pulse of the write clock signal, and a read address generating circuit for incrementing the read address for each pulse of the read clock signal. And an address comparison circuit that compares an output signal from the write address generation circuit with an output signal from the read address generation circuit.

Further, the read control means determines a time to start reading data stored in the data holding buffer in association with an output signal from the speed comparison means, and generates a read enable signal requesting the reading. And a read end time determining means for determining whether to generate the read enable signal in association with an output signal from the address comparison circuit.

Further, the reading start time determining means includes:
The first signal in association with the output signal from the speed comparing means;
Or the second value can be selected as the threshold value for starting reading.

[0032]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first-in first-out memory device according to an embodiment of the present invention will be specifically described with reference to the accompanying drawings. FIG. 1 is a block diagram showing a configuration of a first-in first-out memory device (FIFO device) according to the first embodiment of the present invention.

In the first embodiment of the present invention, there is provided a data holding buffer 2 for holding data for each byte input from the data input line 11. The data holding buffer 2 is, for example, a two-port RAM. The data held from the data holding buffer 2 is output to the data output line 12. The data input line 11 and the data output line 12 transmit, for example, data in units of 1 byte. Further, a write address generation circuit 3 for specifying a write address of the data holding buffer 2 and a 42-ary read address generation circuit 4 for specifying a read address of the data holding buffer 2 are provided. Further, the output value W_ad from the write address generation circuit 3 is compared with the output value R_ad from the read address generation circuit 4, and an address difference High, an address difference Low, or an address difference match signal is output according to the comparison result. An address comparison circuit 5 is provided.

A write enable signal and a write clock signal for requesting data writing from the outside are supplied to the data holding buffer 2 and the write address generation circuit 3.
, And a read clock signal is input to the data holding buffer 2 and the read address generation circuit 4 from the outside. Further, a reset signal is externally input to the write address generation circuit 3 and the read address generation circuit 4.

This embodiment further includes a frequency detection / comparison circuit 6 for comparing the speeds of the write clock signal and the read clock signal and detecting the faster clock signal. The frequency detection / comparison circuit 6 counts a write clock and outputs a carry signal W_cry at a maximum value, and a read frequency detection circuit 8 counts a read clock and outputs a carry signal R_cry at a maximum value. A frequency comparing circuit 9 is provided which detects a faster clock signal based on the carry signals of the frequency detecting circuits 7 and 8 and outputs a signal Frq_HL indicating the result.

Further, in this embodiment, the signal Frq_H
A read enable selection circuit 1 is provided which selects the output from the address comparison circuit 5 using L as a selection signal and controls the start of reading. A read enable signal requesting the reading of data from the data holding buffer 2 is output from the read enable selection circuit 1 to the data holding buffer 2 and the read address generation circuit 4.

The data holding buffer 2 is composed of a RAM or the like, holds data input from the data input line 11 at a predetermined address, and stores it at a data output line 12.
Output function.

The write address generation circuit 3 and the read address generation circuit 4 are composed of a counter and the like.
A function is provided for designating addresses of the data holding buffer in order from address 0. Further, the write frequency detection circuit 7 and the read frequency detection circuit 8 are also composed of a counter and the like.

The address comparison circuit 5 compares the output values of the write address generation circuit 3 and the output value of the read address generation circuit 4 to determine the difference between them. When the data amount held in the data holding buffer 2 is smaller than a predetermined amount, It has a function of outputting a signal for judging whether the address difference is low (address difference high) or not (address difference high) or not (address difference match).

FIG. 2 is a block diagram showing a configuration of the read enable selection circuit 1 according to the first embodiment of the present invention. The read enable selection circuit 1 is provided with a read start threshold value selection circuit 1a that generates a signal (read enable signal) for performing a read request of the data holding buffer 2 according to the writing and reading speeds.
At the start of the read enable signal, the speed differs depending on the speed difference between writing and reading, and the signal Frq_HL from the frequency detection / comparison circuit 9 is used as a selection signal. The read enable signal is activated when the address difference row signal becomes active. On the other hand, when the read speed is high, the read enable signal is activated when the address difference high signal indicating that the address difference is large becomes active.
As a result, the frequency difference between writing and reading is absorbed.

Further, when the address difference match, which is one of the comparison result signals from the address comparison circuit 5, becomes active, that is, after the read enable signal becomes active, the read enable selection circuit 1 When the address matches the read address, the read enable signal is made inactive, and the operation of stopping reading data from the data holding buffer 2 is executed.

In the FIFO device according to the first embodiment, for example, when the frequency of the write clock signal and the read clock signal is 50 ± 1 MHz and the maximum packet length is 1024 bytes, the following estimation is performed for 42 stages. Memory depth is required. That is, 84
Byte storage capacity is required.

When the write speed is faster than the read speed, for example, the frequency of the write clock signal is 49 MHz.
When z (period: 20.4 nsec) and the frequency of the read clock signal is 51 MHz (period: 19.6 nsec), the time required to write 1024 bytes of data is 20.4 nsec × 1024 The time required for reading out 1024 bytes of data is 20.07 μsec from 19.6 nsec × 1024. Therefore, in this case, the depth of the memory required to absorb the speed difference is 42 steps from ((write time)-(read time)) / (read cycle).

Therefore, assuming that reading is started at the time of writing 1-byte data, if the depth of the memory of the time difference is provided, the writing operation will not overtake the reading operation. When calculated under these conditions, the depth of the memory is 42 steps, and the threshold value for starting reading is 1.

When the write speed is lower than the read speed, for example, when the frequency of the write clock signal is 51
When the frequency of the read clock signal is 49 MHz (period: 20.4 ns), the time required to write 1024 bytes of data is 19.6 ns × 1024. The time required to read 1024 bytes of data is 20.88 μsec from 20.4 nsec × 1024. Therefore, in this case, the depth of the memory required to absorb the speed difference is -42 steps from ((write time)-(read time)) / (read cycle).

Therefore, assuming that reading is started when 42 bytes of data are written, if the depth of the memory of the above time difference is provided, the writing operation will not be overtaken by the reading operation. Calculating under these conditions,
The depth of the memory is 42 steps, and the threshold value for starting reading is 4
It becomes 1.

As described above, the memory depth is set to 42 steps,
By setting two thresholds for reading start, such as 1 and 41, it is possible to cope with either of the above cases, and error data transfer does not occur. That is, it is possible to prevent the write operation from overtaking the read operation with half the memory amount of the conventional FIFO device, and also prevent the read operation from overtaking the write operation. Therefore, the hardware amount of the data holding buffer 2 can be reduced to half.

Next, an FIF adapted to the specification in which the frequency of the write clock signal and the read clock signal is 50 ± 1 MHz and the maximum packet length is 1024 bytes.
The configuration and operation of the O device will be described. FIG. 3 is a block diagram showing a FIFO device adapted to a predetermined specification.

The FIFO according to the first embodiment conforms to the above specifications.
When adapting the device, the memory capacity of the data holding buffer 2 is 42 stages. The write address generation circuit 3
And the read address generation circuit 4 is a 42-ary one. Further, the write frequency detection circuit 7 and the read frequency detection circuit 8 are hexadecimal.

Then, the data from the input data line is supplied to the data input of the data holding buffer 2, and when the write enable signal is active, the data is stored in the address of the data holding buffer 2 based on the output value W_ad of the write address generating circuit 3. Will be retained. When the read enable signal is active, the held data is read from the address of the data holding buffer 2 based on the output value R_ad of the read address generation circuit 4 and output to the data output line.

The write address generation circuit 3 is initialized by a reset signal, and in the initial state, “W_ad =
After that, when the write enable signal becomes active, it is sequentially incremented by the write clock signal, and after outputting "W_ad = 41", outputs "W_ad = 0" again. The read address generation circuit 4 also outputs “R_ad = 0” in the initial state based on the reset signal, the read enable signal, and the read clock signal, and then sequentially increments to indicate “R_ad = 0”.
The operation of outputting “R_ad = 0” again is performed.

Further, the write frequency detection circuit 7 and the read frequency detection circuit 8 provided in the frequency detection comparison circuit 6 are initialized by a reset signal. Then, during a period before the start of packet transfer, that is, during an idle period in which the write enable signal is inactive, the frequencies of the write clock signal and the read clock signal are changed to the write frequency detection circuit 7 and the read frequency detection circuit, respectively. 8 counts. The frequency comparison circuit 9
A selection signal F that determines which one of the write frequency detection circuits 7 and the read frequency detection circuit 8 rises earlier is detected by the carry signal W_cry and the carry signal R_cry output at the maximum value, and determines a read start threshold value according to the comparison result.
rq_HL is output.

The address comparing circuit 5 compares the difference between the write address and the read address to obtain "W_ad =
An address difference low signal is output when R_ad + 1 is set, and an address difference high signal is output when W_ad = R_ad + 41 is set.
When it becomes "ad + 1", an address difference match signal is output.

Thereafter, the signal Frq_HL is supplied to the read enable selection circuit 1, which selects one of the address difference high signal and the address difference low signal output from the address comparison circuit 5. And the read enable signal is activated. Further, the read enable selection circuit 1 makes the read enable signal inactive when the coincidence signal from the address comparison circuit 5 becomes active.

FIG. 4 shows an FIF according to the first embodiment of the present invention.
6 is a timing chart showing an operation when a write clock of the O device is faster than a read clock.

The write clock signal and the read clock signal are always input. When the reset signal becomes active, the write address generation circuit 3, read address generation circuit 4, write frequency detection circuit 7, and read frequency detection 8 are initialized.

If the write clock is faster than the read clock, the carry signal W_cry rises earlier than the carry signal R_cry while the write enable signal is low (inactive), so the signal Frq_HL indicates that, and the read enable selection circuit The read start threshold value selection circuit 1a in 1 selects the address difference row signal.

When the write enable signal is high (active), the write address generation circuit 3 increments the output value W_ad at the rise of the write clock signal, and the data holding buffer 2 sequentially converts the input data into the output value W_ad. Write to the specified address.

Further, since the address difference row signal is selected, when the output value W_ad becomes 1, "W_ad
= R_ad + 1 "holds, the read enable signal goes high (active), and the reading of the data held in the data holding buffer 2 is started.
The data holding buffer 2 outputs data from the address designated by the output value R_ad to the output data line. The read address generation circuit 4 increments the output value R_ad at the rise of the read clock signal.

Thereafter, when 1024 bytes of data are input, the write enable signal becomes inactive, and the write address generation circuit 3 stops incrementing the output value W_ad. Thereafter, when the write address matches the read address, that is, “W_ad = R
When “_ad” is satisfied, the read enable signal becomes inactive, and the data reading ends.

FIG. 5 shows an FIF according to the first embodiment of the present invention.
6 is a timing chart illustrating an operation when a read clock of the O device is faster than a write clock.

Also in this case, the write clock signal and the read clock signal are always input. When the reset signal becomes active, the write address generation circuit 3,
The read address generation circuit 4, the write frequency detection circuit 7, and the read frequency detection 8 are initialized.

When the read clock is faster than the write clock, the carry signal R_cry rises earlier than the carry signal W_cry when the write enable signal is low, so that the signal Frq_HL indicates that. The start threshold value selection circuit 1a selects an address difference high signal.

When the write enable signal is high (active), the write address generation circuit 3 increments the output value W_ad at the rise of the write clock signal, and the data holding buffer 2 sequentially converts the input data into the output value W_ad. Write to the specified address.

Further, since the address difference high signal is selected, when the output value W_ad becomes 41, “W_a
d = R_ad + 41 "holds, the read enable signal goes high (active). Then, reading of the data held in the data holding buffer 2 is started, and the data holding buffer 2 outputs the data from the address specified by the output value R_ad. The data is output to the data line, and the read address generation circuit 4 increments the output value R_ad at the rise of the read clock signal.

Thereafter, when 1024 bytes of data are input, the write enable signal becomes inactive, and the write address generation circuit 3 stops incrementing the output value W_ad. Thereafter, when the write address matches the read address, that is, “W_ad = R
When “_ad” is satisfied, the read enable signal becomes inactive, and the data reading ends.

Next, a description will be given of data packets input / output. FIG. 6A is a schematic diagram illustrating a packet of input data, FIG. 6B is a schematic diagram illustrating a packet of data output when the writing speed is higher than or equal to the reading speed, and FIG. FIG. 9 is a schematic diagram showing data packets output when the speed is higher than the writing speed.

Packets are continuously transmitted with an idle period, which is a frame interval. For example, as shown in FIG.
800-byte packet 2, 880-byte packet 3
Even if the data amount is variable as described above, as described above, when the write clock signal is faster or the same, the read operation is started when one byte of data is written, and If it is faster,
Since the read operation starts when 41-byte data is written, unnecessary error data other than the frame is not transferred. Even if there is no frame interval, the packet is recognized.

As described above, according to the present embodiment, the faster one of the writing and the reading is detected, and the reading threshold is automatically selected based on the result to start the reading. Whichever is faster, it is possible to absorb the speed difference and prevent the transfer of error data. That is, by setting two read thresholds, an extra memory depth for absorbing the speed difference between the write clock signal and the read clock signal becomes unnecessary, and the read threshold is fixed. Compared with the conventional FIFO device, the amount of memory can be reduced to half. In addition, if the depth of the memory is reduced, it is possible to reduce the amount of registers for specifying the address of the memory.

Also, since the one with the higher speed is detected and the reading threshold is automatically set in association with the result,
Even when the speed difference between the input side and the output side is changed from the value at the time of design due to a factor at the time of manufacturing, there is no need to redesign, and there is an effect that productivity is improved.

Next, a second embodiment of the present invention will be described. In this embodiment, the configuration is such that the write frequency detection circuit 7 and the read frequency detection circuit 8 in the first embodiment are incorporated in the write address generation circuit 3 and the read address generation circuit 4, respectively. FIG. 7 is a block diagram showing the configuration of the FIFO device according to the second embodiment of the present invention. In the second embodiment shown in FIG. 7, the same components as those in the first embodiment shown in FIG. 3 are denoted by the same reference numerals, and detailed description thereof will be omitted.

In the second embodiment, the write address generation circuit 13 is composed of a 42-ary counter, counts the write clock signal and carries the carry signal W_
Cry output function and data holding buffer (RA
M) a function of outputting an output value W_ad designating a write address of 2); The read address generation circuit 14 is composed of a 42-ary counter, counts the read clock signal and outputs the carry signal R_cry, and outputs the output value R_ad specifying the read address of the data holding buffer 2. It has.

Next, the FIF according to the second embodiment of the present invention will be described.
The operation of the O circuit will be described. FIG. 8 is a timing chart showing the operation of the FIFO device according to the second embodiment of the present invention when the write clock is faster than the read clock.

In the calibration period after the reset, the write address generation circuit 13 counts the write clock signal and outputs the carry signal W_cry when the output value W_ad becomes 15. When the carry signal W_cry rises once, the write address generation circuit 1
3 sets the output value W_ad to 0 and does not count up until the write enable signal becomes active.

Similarly, the read address generation circuit 14 counts the read clock signal and outputs an output value R_ad of 15
, A carry signal R_cry is output.
When the carry signal R_cry rises once, the read address generation circuit 14 sets the output value R_ad to 0 and does not count up until the read enable signal becomes active.

Here, since the write clock is faster than the read clock, as shown in FIG. 8, carry signal W_cry rises earlier than carry signal R_cry, signal Frq_HL indicates that, and read enable select circuit 1 Read start threshold selection circuit 1
“a” selects the address difference row signal. Therefore, "W
When _ad = R_ad + 1 ", the read enable signal becomes active, and the reading of the data held in the data holding buffer 2 is started.
The data holding buffer 2 outputs data from the address designated by the output value R_ad to the output data line. Thereafter, the same operation as in the first embodiment is performed.

When the read clock is faster than the write clock, the read enable selection circuit 1
The read start threshold value selection circuit 1a selects the address difference high signal, and the read enable signal becomes active when “W_ad = R_ad + 41”, except that the write clock is faster than the read clock. Perform the operation.

[0078]

As described in detail above, according to the present invention,
Read control means is provided to control the data read start timing according to the address difference between the write address and the read address, so even if the write speed or the read speed is faster, the speed difference is absorbed. Thus, transfer of error data can be prevented. In addition, since an extra capacity is not required for the data holding buffer, the conventional FIFO in which the read threshold is fixed is used.
The amount of memory can be significantly reduced as compared with the device. Thus, the number of registers for specifying the address of the data holding buffer can be reduced.

Further, even if the speed difference between the input side and the output side has been changed from the value at the time of design due to factors at the time of manufacture, etc., redesign is not required, so that productivity can be improved. Can be.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a FIFO device according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a read enable selection circuit 1 according to the first embodiment of the present invention.

FIG. 3 is a block diagram showing a FIFO device adapted to a predetermined specification.

FIG. 4 is a timing chart showing an operation of the FIFO device according to the first embodiment of the present invention when a write clock is faster than a read clock.

FIG. 5 is a timing chart showing an operation of the FIFO device according to the first embodiment of the present invention when a read clock is faster than a write clock.

FIG. 6A is a schematic diagram illustrating a packet of input data, FIG. 6B is a schematic diagram illustrating a packet of data output when a writing speed is higher than or equal to a reading speed, and FIG. FIG. 4 is a schematic diagram showing data packets output when the read speed is higher than the write speed.

FIG. 7 is a block diagram illustrating a configuration of a FIFO device according to a second embodiment of the present invention.

FIG. 8 is a timing chart showing an operation of the FIFO device according to the second embodiment of the present invention when the write clock is faster than the read clock.

FIG. 9 is a block diagram showing a configuration of a conventional FIFO device.

FIG. 10 is a schematic diagram showing a configuration of a conventional FIFO device described in Japanese Patent Application Laid-Open No. 9-190334.

FIG. 11 is a block diagram showing a configuration of a read enable control circuit 41 in a conventional FIFO device described in JP-A-9-190334.

FIG. 12A is a schematic diagram showing input data,
(B) is a schematic diagram showing data output when the write speed is equal to the read speed, (c) is a schematic diagram showing data output when the write speed is faster than the read speed, and (d) is a schematic diagram showing data output when the write speed is higher than the read speed. FIG. 9 is a schematic diagram illustrating data output when a read speed is faster than a write speed.

[Explanation of symbols]

 1; read enable selection circuit 1a; read start threshold value selection circuit 1b; read enable end detection circuit 2, 22, 42; data holding buffer 3, 13, 23, 43; write address generation circuit 4, 14, 24, 44; Address generation circuits 5, 45; address comparison circuits 6, frequency detection comparison circuits 7, write frequency detection circuits 8, read frequency detection circuits 9, 46; frequency comparison circuits 11, 31, 51; data input lines 12, 32, 52; Data output line 21; various flag generation circuits 41a; write start detection circuit 41b; read enable generation circuits 41c and 41d; frame interval selection circuit 47; write counter 48; read counter 49; counter value comparison circuit AND;

Continuation of the front page (56) References JP-A-5-61640 (JP, A) JP-A-7-23015 (JP, A) JP-A-3-238685 (JP, A) JP-A-62-256033 (JP) , A) (58) Field surveyed (Int. Cl. ⁷ , DB name) G06F 5/06 311 G11C 7/00 318 G06F 13/38 310 H04L 13/08

Claims (6)

(57) [Claims] A data holding buffer for storing data; a speed comparing means for comparing a writing speed and a reading speed of the data holding buffer before data is written to the data holding buffer; Address difference detection means for detecting an address difference between a write address at which writing to the buffer is performed and a read address at which reading is performed;
The reading of the data stored in the data holding buffer is started when the value reaches the value, and when the reading speed is higher than the writing speed, the address difference becomes the second.
Read control means for starting reading of data stored in the data holding buffer when the value of
A first-in, first-out memory device. 2. The first-in, first-out memory device according to claim 1, wherein said read control means terminates reading of data stored in said data holding buffer when said address difference becomes zero. 3. A write frequency detection circuit for detecting a frequency of a write clock signal for setting a timing for writing data to the data holding buffer, and a reading for setting a timing for reading data from the data holding buffer. A read frequency detection circuit that detects a frequency of a clock signal, and a frequency comparison circuit that compares an output signal from the write frequency detection circuit with an output signal from the read frequency detection circuit. 3. A first-in first-out memory device according to claim 1 or 2. 4. A write address generation circuit for incrementing the write address for each pulse of the write clock signal, and a read address generation circuit for incrementing the read address for each pulse of the read clock signal. 4. The first-in-first-out memory device according to claim 3, further comprising: an address comparison circuit that compares an output signal from the write address generation circuit with an output signal from the read address generation circuit. 5. The read control means determines a time to start reading data stored in the data holding buffer in association with an output signal from the speed comparison means, and generates a read enable signal requesting the reading. 5. A read start timing determining means, and read end timing determining means for determining whether to generate the read enable signal in association with an output signal from the address comparison circuit. A first-in first-out memory device according to any one of the preceding claims. 6. The read start time determining means selects the first value or the second value as a read start threshold value in association with an output signal from the speed comparing means. 6. A first-in first-out memory device according to claim 5.