JP2995060B2 - Active load circuit for ECL type output - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to an active load circuit used for an emitter-coupled logic circuit (hereinafter referred to as an ECL circuit).

<Conventional technology and its problems> In recent years, a load circuit used at an output terminal of an ECL circuit includes a normal resistor toward a negative supply voltage line (VEE) or a positive phase and a complementary phase. A transistor arranged in series with a resistor connected between the two emitters of the emitter follower output transistor is used. By the way, such loads reduce the power consumption of most ECL circuits by 20.
~ 30% increase. With respect to the load in such a load circuit, a differential transistor pair with one transistor connected to VEE, having each output transistor in the collector circuit of each transistor in the pair, is used. This can be halved.
However, it is strongly desired to further reduce the power consumption of such a load circuit.

A more complex pull-in or load circuit in an ECL circuit is disclosed in U.S. Pat. No. 4,559,458 to Bing-Fing Ma, issued Dec. 17, 1985. In this patent, a load circuit for one output
Thirteen elements are used. From the viewpoint of power consumption, in the above patent, five elements are grounded for one output. Each time one element is grounded, the DC power consumption increases. The minimum voltage required to operate the circuit of the above patent is 3.7 volts. It is desired that ECL circuits operate at voltages below 2 volts.

Therefore, it is rather an object of the present invention to provide an active load circuit for an ECL circuit which hardly causes an increase in power consumption.

<Means for Solving the Problems> According to the gist of the present invention, as shown in FIG. 2, an active load circuit for an ECL circuit having a pair of transistors of a complementary emitter follower is provided. And the active load circuit includes the pair of transistors,
That is, the positive phase output transistor 28 and the complementary phase output transistor
The positive and negative dual load transistors 72 and 73 connected from the respective emitters of 26 to the negative voltage supply line 58, and between each base of the positive and complementary dual load transistors 72 and 73 and the negative voltage supply line 58 The inserted bias element 84 and the AC coupling elements 74 and 76 connected separately from the output terminals of the positive and complementary dual output transistors 28 and 26 to the respective bases of the positive and complementary dual load transistors 72 and 73. And are included.

The AC coupling elements 74 and 76 can be effectively realized by capacitors.

<Operation> When the transistor 26 of the positive and complementary dual output transistors 28 and 26 is turned on and its output is driven to “H”, the electric charge on the output line 64 where the “H” output appears appears. The load transistor is supplied to the base of the transistor 72 of the positive and complementary phase dual load transistors 72 and 73 via the AC coupling element 76 connected to the output line 64.
72 is strongly driven as a pull-in transistor, thereby acting to lower the emitter potential of the other output transistor 28.

<Example> First, in order to make the present invention easy to understand, FIG.
An active load circuit for an ECL circuit will be described.

In the modified ECL circuit positive / complementary buffer shown in FIG. 1, the input on line 50 drives the base of a PNP transistor 10 whose emitter draws current from bias resistor 42. The current through resistor 42 is determined by transistors 14, 20 and diodes 40, 34, 36,
Bias current for 38. Transistor 12 having a base 70 driven externally by a control signal,
When its base 70 is driven low, the diode 3
Supply current to 4, 36 and 38. The base of the transistor 16 of the pair of transistors 14 and 16 forming the differential pair is connected to the first reference voltage REF1 via the line 60. The resistors 44 and 46 are respectively connected to the transistor 14,
As well as becoming the collector load of 16, they are also connected to the emitter of the clamp transistor 18, the collector of which is connected to the high voltage line 52, the base of which is externally connected via line 48. Connected to the supplied clamp voltage.

The emitters of the transistors 14 and 16 are commonly connected to the collector of the transistor 22, and the emitter of the transistor 22 is connected to the ground line 58. The base of the constant current source transistor 22 is connected to another constant current source transistor 32.
Is driven via a line 56 from an external terminal together with the base. The collector output of transistor 16 drives the base of the positive follower output transistor 28 of the emitter follower. On the other hand, the collector output of the transistor 14 drives the base of the complementary output transistor 26 of the emitter follower. line
The in-phase output of 66 is taken from the emitter of the in-phase output transistor 28, and the complement output on line 64 is taken from the emitter of the in-phase output transistor 26.

The output transistor load circuit 15 includes transistors 20 and 2
It consists of 4, 30, and 32. Regarding the transistors 24 and 30, the emitters are commonly connected to the collector of the constant current source transistor 32, and the emitter of the transistor 32 is connected to the ground line 58. The base of transistor 30 is connected via line 62 to a second reference voltage REF2. The emitter of transistor 20 in the emitter follower drives the base of transistor 24. A resistor 54 inserted between the ground line 58 and the emitter of the transistor 20 forms the load resistance of the transistor 20.

 Next, the operation will be described.

Assuming that line 70 is "L" and line 48 is "H", transistor 12 supplies a bias current to the emitter diode rows 34, 36, 38, thereby allowing the voltage allowed at the base of transistor 14 This results in fixing the upper limit of the amplitude to the forward voltage drop of the four diodes. For example, if the voltage on line 50 drops enough to draw current from the base of transistor 10, the transistor
14 turns off and transistor 20 similarly turns off.
When the emitter voltage of transistor 10 drops, diode 40 turns off. On the other hand, in response to the transistor 14 being turned off, the transistor 16 is turned on, so that the base of the transistor 26 becomes “H” and conversely, the base of the transistor 28 becomes “L”. . Thus,
The complement output of line 64 goes to "H", and conversely the positive output of line 66 goes to "L". At the same time, transistors 20 and 24 are turned off, while transistor 30 is turned on, forcing the positive phase output voltage on line 66 to decrease. Due to the amount of current drawn in the output transistor load circuit 15 necessary to reduce the voltage remaining as a voltage drop on the positive or complementary phase output lines 66, 64, the output lines themselves pass the drawn current. The lower limit of the bias current required for the base of the transistor 32 is limited. On the other hand, the pull-down transistors 24 and 30 are differentially connected, and the current drawn from these transistors is halved, but such a current still has a relatively large value as the power consumption in the entire circuit. is occupying.

An active load circuit 17 improved according to the present invention is shown in FIG. In the figure, the same components as those of the circuit configuration of FIG. 1 are denoted by the same reference numerals. The circuit shown in FIG. 2 includes components other than the load circuit 17 in which the transistors 72 and 73 are connected to the positive-phase and complementary-phase output lines 66 and 64, respectively.
The circuit configuration is the same as that of FIG. Each transistor 72, 73
The base bias of the diode-connected transistor 84
Transistor 84 is determined by resistors 78, 80
Are connected to the respective bases of the transistors 72 and 73.
The bias current for the diode 84 and the base of the transistors 72, 73 is due to the current through the resistor 82 from the line 56. Coupling capacitors 74 and 76 respectively transfer charges from the positive-phase and complementary-phase output lines 66 and 64 to the transistors 73 and 72, respectively.
Carry towards the base.

As before, the complement output on line 64 goes high,
Assuming that the positive output of line 66 has gone "L", the charge from line 64 whose complementary output is "H" is carried by capacitor 76 towards the base of pull-in transistor 72 and Driving transistor 72 more robustly to enhance the pulling of line 66 whose output is "L". In the circuit of FIG. 2, the recovery time is selected to be 3 to 5 times the RC value (time constant) which is a combination of the resistors 80 and 78 and the capacitors 74 and 76.

The output transistor load circuit shown in FIG.
It can be used inside other types of logic circuits, and this can greatly reduce the power consumption of the entire chip.

As described above, the present invention has been disclosed with reference to the above embodiments, but the present disclosure is not construed as being limited. Various modifications of the above embodiments, as well as other embodiments of the invention, will be readily apparent to those skilled in the art from reference to the present disclosure. Accordingly, the appended claims are intended to cover any variations or embodiments within the true scope of the invention.

Next, disclosure items related to the technical matters of the present invention will be described.

(1) An active pull-down circuit for a logic circuit having a true and a complement output, the pull-down transistor connected to one of the true and complement outputs, a bias element for biasing the pull-down transistor, The pull-down transistor is connected between the other of the true and complement outputs and the base of the pull-down transistor, and pulls down the charge from the other output to turn on the pull-down transistor when the other output goes low. And a charge-coupled device coupled to the transistor.

(2) In the circuit according to item 1, the charge-coupled device is a capacitor.

(3) In the circuit according to the first aspect, the bias element is a diode connected to a transistor connected to the base of the pull-down transistor via a current source and a base series resistor.

(4) an active pull-down circuit for an emitter-coupled logic circuit having true and complement outputs, connected to a true and complement pull-down transistor connected to the true and complement outputs, and a base of each of the pull-down transistors; Bias means for biasing each of the pull-down transistors; and a connection from each of the true and complement outputs to the base of the complement and true pull-down transistors, respectively. And a charge-coupled device that turns on strongly.

(5) In the circuit according to item 4, the charge-coupled device is a capacitor.

(6) In the circuit according to item 4, the bias means is a diode connected to the base of the pull-down transistor via a current source and an insulating resistor.

(7) In the circuit according to item 5, the product of the resistance value of the insulation resistance and the capacitance value of the charge-coupled device is in a range of 0.5 to 2.0 ns (nanosecond).

(8) In the circuit according to item 6, each current flowing through the pull-down transistor and the diode is in a range of 1/10 to 1/100 of a current flowing in the logic circuit.

(9) An active pull-down circuit (17) having true and complement outputs (66, 64),
A pull-down transistor (72, 73) connected to one of the true and complement outputs (66, 64); a bias element (84) for biasing the pull-down transistor;
4, 66) and the pull-down transistor (72, 7
3) connected between the other output (64, 6)
When 6) goes low, the pull-down transistor (7
2, 73) for coupling the charge from the other output (64, 66) to the pull-down transistor (72, 73) to turn on the second pull-down transistor (72, 73).

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a conventional active load circuit used in an ECL circuit, and FIG. 2 is a block diagram showing a configuration of an active load circuit according to a preferred embodiment of the present invention. 17 Active load circuit 26 Complementary output transistor 28 Positive output transistor 64 Complementary output line 66 Positive output line 72, 73 Pull-in transistors 74, 76 AC coupling Capacitor 84 bias element

Claims (6)

(57) [Claims] A true output and a complement output;
And an external reference line for applying a predetermined voltage, an active load circuit for a logic output circuit provided with a reference voltage supply line, a collector connected to the true output, an emitter directly connected to the reference voltage supply line, and a base. A second pull-down transistor having a collector connected to the complement output, an emitter directly connected to the reference voltage supply line, and a base; and a first and a second pull-down transistor. A bias circuit having an input coupled to a base of a transistor and the external reference line for supplying a bias current to the first and second pull-down transistors, and having an output connected to the reference voltage supply line; A connection is made between the base of the first pull-down transistor and the complement output. A first charge-coupled device connected between and coupled to a charge therebetween, and a second charge-coupled device connected between the base of the second pull-down transistor and the true output and coupling charge therebetween. An active load circuit comprising: 2. The active load circuit according to claim 1, wherein said first and second charge-coupled devices are capacitors. 3. The bias circuit is connected to a first resistor connected from a base of the first pull-down transistor to a diode-coupled transistor, and connected to a base of the second pull-down transistor from the base of the second pull-down transistor to the diode-coupled transistor. And a second resistor that is
4. The active load circuit according to claim 1. 4. The first and second charge-coupled devices include respective capacitors and the first and second resistors, wherein the capacitors have a time constant in the range of 0.5 to 2.0 nanoseconds. Item 7. An active load circuit according to item 3. 5. The logic output circuit passes a current, and the active load circuit transmits the current to the first and second pull-down transistors and the bias circuit.
2. The active load circuit according to claim 1, wherein the signal is passed in a range of 1/10 to 1/100. 6. The active load circuit according to claim 1, wherein said reference voltage supply line is a negative voltage supply line.