JP2994678B2 - Multi-tone liquid crystal display device and its driving voltage generating circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-gradation liquid crystal display device and a driving voltage generation circuit therefor, for example, a color liquid crystal display device having a TFT active matrix structure for performing multi-color display by a digital method. It relates to technology that is effective to use.

[Conventional technology]

An active matrix color liquid crystal display device equipped with a TFT (thin film transistor) includes, for example, Nikkei McGraw-Hill Company, “Nikkei Electronics”, page 211, September 10, 1984, and the like.

[Problems to be solved by the invention]

The TFT liquid crystal display device is mainly used for a monitor or the like in a microcomputer system as a small and low power consumption display device, but there is a strong demand for multi-gradation and multi-color display as a display device in office automation equipment.

In order to use a liquid crystal display panel having a TFT active matrix structure to perform multi-gradation display as described above, it is necessary to use a linear region in the luminance-voltage characteristics of the liquid crystal. However, the luminance-voltage characteristic of the liquid crystal is
As shown in FIG. 31, it greatly varies depending on the vertical viewing angle. For example, from the transmittance of each gradation set at a viewing angle of 0 ° with respect to the display panel, a viewing angle that is a viewing angle range in which the color tone does not shift to 1/2 gradation or more is obtained. It turns out that it is narrow. As shown in the drawing, each gradation changes in a direction in which the transmittance becomes lower as a whole, in other words, in a direction closer to the black level. Therefore, for example, 51
In the case of multi-color display for the purpose of expressing a subtle color tone such as two colors, the color tone is greatly changed and the meaning of the multi-color display is lost.

Therefore, when the viewing angle changes as described above, it is conceivable to change the drive voltage corresponding to each gray level accordingly. In this case, according to the simplest idea, it is conceivable to make the drive voltage corresponding to each gradation display adjustable. However, such an adjustment method requires eight adjustments each time the viewing angle changes when displaying eight gradations, and the combination is enormous and cannot be put to practical use at all. For this reason, the conventional color liquid crystal display device produces eight colors by a combination of red, green, and blue single gradations without using the linear part of the luminance-voltage characteristics. In the case of such a single tone,
The drive voltage can be formed with a sufficient margin so as not to be affected by the fluctuation of the luminance-voltage characteristic due to the viewing angle as described above.

The present inventors have discovered that the luminance (transmittance) -voltage characteristic of the liquid crystal with respect to the vertical viewing angle changes with an approximately constant reference voltage. By using this reference voltage, a display drive voltage generation circuit that easily adjusts to a change in viewing angle when performing multi-gradation display using a region where the transmittance of the liquid crystal changes linearly. Has led to the development.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a multi-gradation liquid crystal display device which can easily and accurately adjust a multi-gradation display with respect to a change in a viewing angle in a vertical direction, and a driving voltage generating circuit thereof.

Another object of the present invention is to provide a multi-gradation liquid crystal display device which realizes high-quality multi-color display and a drive voltage generation circuit thereof.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[Means for solving the problem]

The outline of a typical invention disclosed in the present application will be briefly described as follows. That is,
Reference is made to a voltage that is approximately determined based on the intersection of straight lines extending along the slope of the luminance-voltage characteristic corresponding to at least two viewing angles that differ vertically with respect to a liquid crystal display panel having a TFT active matrix configuration. An operation in which a driving voltage for multi-tone display is formed in conjunction with a voltage that is changed in accordance with the viewing angle as a voltage, and a polarity is inverted in a circuit for generating the reference voltage and a voltage dividing circuit in accordance with an alternating signal of liquid crystal. Supply voltage. The reference voltage is automatically temperature compensated by a temperature compensation circuit corresponding to the temperature dependency. A mounting substrate on which a power supply circuit for generating a driving voltage for multi-gradation is mounted is arranged so as to sandwich a backlight on the back side of the liquid crystal display panel.

(Operation)

According to the above-described means, it is possible to change the driving voltage for multiple gradations for multiple gradations along the inclination of the luminance-voltage characteristic corresponding to the viewing angle by adjusting one location. The adjustment of the gradation display with respect to the change in the vertical direction becomes easy and accurate. Further, it is possible to prevent an increase in the size as viewed from the front side, despite having a mounting substrate for a multi-gradation drive voltage generation circuit, which is increased in size by mounting a relatively large number of elements.

〔Example〕

FIG. 1 is a characteristic diagram for explaining the principle of the viewing angle correction method in multi-tone display of liquid crystal according to the present invention.

In the figure, the vertical axis represents the luminance (liquid crystal transmittance) B,
The horizontal axis indicates the voltage V applied to both electrodes of the liquid crystal. The characteristic curve of θ = 0 ° is a characteristic diagram of the viewing angle corresponding to the front (normal line) of the liquid crystal, and the characteristic curve of θ = 40 ° is a viewing angle inclined upward by 40 ° with respect to the normal line. FIG. Thus, when the viewing angle changes from 0 ° to 40 °,
The region of the characteristic curve in which the luminance changes linearly shifts to the left as a whole. Thus, for example, when obtaining the eight gradations, the same luminance when the viewing angle is changed as, for example, the voltage V ₅ to the intermediate gradation 5 is obtained V _{5 '}
It is conceivable that it should be changed as follows. However, the characteristic curve of θ = 0 ° does not translate to the left when the viewing angle changes to 40 ° as described above.
Since the gradient of the luminance with respect to the voltage also changes, it is necessary to perform the voltage correction for each of the remaining seven gray scales as described above. I can't get it.

However, the inventors of the present invention have carefully observed the characteristic curve of θ = 0 ° and the characteristic curve of θ = 40 °. I discovered that That is, the viewing angle is θ =
With respect to the characteristic curve of 0 °, the characteristic curve of the visual angle θ = 40 ° shifts to the left as a whole, and changes so that the inclination becomes large. From the characteristic of the characteristic curve change due to such a change in the viewing angle, an area in which the luminance changes linearly in the two curves is approximated to a straight line and extended upward. Then, the two straight lines approximated as shown by the thin lines in the figure have an intersection P at the top of the characteristic diagram. Further, the two straight lines extend to the lower part of the characteristic curve and have an intersection with the horizontal axis.

A perpendicular to the horizontal axis (voltage axis) is drawn from the point P, and two right-angled triangles having the base as the base can be drawn.
That is, a voltage (V _OFF ) corresponding to the intersection P is set as a reference voltage, and a voltage (hereinafter, sometimes referred to as a viewing angle correction voltage) V _K0 obtained from an intersection with the horizontal axis (voltage axis) is set as a right angle. The hypotenuse of the triangle corresponds to the characteristic curve θ = 0 °.

The hypotenuse of the right-angled triangle formed by changing the viewing angle correction voltage to V _K40 with respect to the reference voltage (V _OFF ) corresponds to the characteristic curve θ = 40 °. The voltage V _K0 which is the height of the right triangle is thus
_Is obtained by dividing the hypotenuses of the above two right triangles at the same ratio by simply changing
Automatic such as, for example luminance are typically illustrated in Fig. (5 gradation) voltage V ₅ when the voltage V ₅ at the time of theta = 0 ° corresponding to B5 of theta = 40 ° _' It can be seen that it can be obtained in a proper way.

In other words, when the hypotenuse of a right triangle corresponding to a luminance (transmittance) of 0 to 100% is divided into eight equal parts to obtain eight gradations, it is obtained in a pseudo manner from a straight line approximating the slope of the characteristic curve. Just adjust the voltage V _K0 corresponding to the luminance 0 by one point corresponding to the change of the viewing angle like the voltage V _K40 ,
It is possible to obtain a liquid crystal driving voltage for obtaining eight gradations formed by the above-mentioned equal division. The reference voltage V _OFF is equal to the above voltage V _K0
It can be regarded as a kind of offset voltage with respect to the voltage _VK40 . Therefore, the reference voltage is represented as V _OFF in FIG.

In the above description, the characteristic curve of the region where the luminance of the liquid crystal changes linearly with the change in the voltage is approximated to a straight line. However, in the vicinity of the point where the luminance becomes 0, the luminance increases again when the voltage is increased. It has a bounce part. Since the rebound portion changes due to the change in the viewing angle, the voltage for obtaining one gradation corresponding to the luminance of 0 is not affected by the rebound portion, and is affected by the rebound characteristic of the characteristic curve as described above. internal use is for higher fixed voltage as voltages V ₁ takes sufficient margin. Therefore, as described above, the voltage V _K0 + V _OFF and the voltage V
_K40 + V _OFF has a meaning only as an adjustment voltage for correcting a viewing angle, and is not used as an actual liquid crystal drive voltage.

FIG. 2 is a basic circuit diagram showing an embodiment of a drive voltage generation circuit having a viewing angle correction function in multi-tone display.

Voltage V _H of the high-level side is used as the liquid crystal driving voltages V ₁ corresponding to the first gradation corresponding to the black level of transmittance of 0%.
This voltage _VH is connected to a series voltage dividing resistor
R ₁ to be supplied to the resistor R ₁ which is one end of R _7. These series voltage dividing resistor circuits R ₁ to R _{6 form six} liquid crystal driving voltages V ₂ to V ₇ corresponding to the second to seventh gradations from the respective interconnection points. Thus, the transmittance is 0%
When the eight gradations from the first gradation to the eighth gradation are obtained by dividing the transmittance 100% into seven equal to the above, the series resistance circuits R ₁ to R ₁
R ₆ is made to have a resistance value equal to each other. Resistance to this
R ₇ is, in the characteristic diagram of FIG. 1, the transmittance begins to change from 100%, as it were a liquid crystal visual threshold voltage V _TH0 and V
_This is for forming a voltage corresponding to _TH40 . For example, when theta = 0 ° corresponds to the voltage V _K0 + V _OFF, the voltage formed by dividing by the ratio of the resistance value and the to no resistor R ₁ in series combined resistance value due to R ₆ of the resistor R ₇ is, teeth This is set to a voltage corresponding to the threshold voltage V _TH0 . And
According to the ratio of the resistance values of the series resistors R ₁ to R ₆ , V _K0 + V
_OFF- V _TH0 voltage is divided into seven equal parts. Which is the other end of the series resistor divider resistors R ₇ side is connected to the voltage V _L of the low-level side through the voltage varying means 2 for forming the reference voltage V _OFF. The voltage V _L is used as the liquid crystal driving voltage V ₈ corresponding to the eight gradations to form a white level of 100% transmittance with a sufficient margin.

In this configuration, the voltage according to the change of the viewing angle θ such as the voltages V _K0 + V _OFF and V _K40 + V _OFF shown in FIG. Obtainable. As described above, the voltages V _K0 + V _OFF and V _K40 + V _OFF are not taken out as outputs because they are not used as actual liquid crystal drive voltages, but are actually voltages present in the variable voltage means 1. . The voltage is V _K0 + V by this variable voltage means 1
By changing the voltage to _OFF or V _K40 + V _OFF, the liquid crystal drive voltages V _{2 to} V ₇ corresponding to the above six gradations can be obtained in conjunction with the change by the series resistance circuit.

In the above description, in order to facilitate understanding of the invention,
It was described separately resistor R ₆ and R ₇ as described above, but a resistor R ₆
The threshold voltage V _TH0 as described above obtained from the connection point of R ₇
Are not used as the driving voltage of the liquid crystal. Therefore, in an actual circuit, it is replaced with one resistor as shown in FIG. 10 and the like later.

In this embodiment, the reference voltage V _OFF is set by the voltage variable means 2.
Is also adjustable. This is necessary not only for the variation in the element characteristics of the liquid crystal but also for temperature compensation as described later. Such temperature compensation will be described later in detail.

FIG. 3 shows an example of a luminance-viewing angle curve obtained by adjustment using the voltage varying means 1.

In the figure, the second to seventh gradations, which are the respective intermediate gradations, are used as parameters. As shown in the figure, the transmittance (luminance) with respect to the viewing angle θ is adjusted to a viewing angle range of about 52 ° and the color tone shift is within 1/2 gradation by adjusting one portion by the voltage varying means 1 as described above. Can be stored. This allows
The observer can easily adjust the color tone according to an arbitrary viewing angle within the range of the viewing angle by operating the voltage varying means 1 including a volume or the like.

FIG. 4 is a characteristic diagram for explaining the principle of the viewing angle correction method in consideration of the temperature characteristic in the multi-tone display of the liquid crystal according to the present invention.

In a liquid crystal, it is known that the luminance-voltage characteristics change even when the temperature changes as shown in FIG. The inventors of the present application have carefully observed a characteristic curve at a temperature of T = 25 ° C. and a characteristic curve at a temperature of T = 60 ° C., and even when the temperature changes, the change of the above-mentioned characteristic curve has a certain law as follows. Discovered that there was something special. That is, with respect to the reference voltage V _OFF1 obtained from the intersection P of two straight lines approximated to the characteristic curves of the viewing angle θ = 0 ° and the viewing angle θ = 40 ° at the temperature T = 25 ° C., the temperature T = 60 ° C. Even if it changes as described above, the above rule is maintained as it is, and the temperature T = 25
An intersection point P 'is formed by two straight lines approximated to characteristic curves of a viewing angle θ = 0 ° and a viewing angle θ = 40 ° at ° C. The reference voltage V _OFF2 is obtained from the intersection P ′. That is,
The inventor of the present application has found that when the temperature changes as described above, the reference voltage V _OFF also changes accordingly. In the drive voltage generation circuit shown in FIG. 2, the voltage variable means 2 can be used for temperature compensation as described above.

FIG. 5 shows an example of a luminance-viewing angle curve obtained by voltage adjustment using the voltage variable means 1 and 2. In the figure, the characteristic curve shown by the solid line, the voltage V ₁ of the first tone in the Figure 4 as 8V, the reference voltage V _OFF2 at a temperature T = 60 ° C. in the case of the 1.2V, the voltage variable Means 2
Is the viewing angle characteristic of each intermediate gray level when is adjusted. The viewing angle at which the shift of each intermediate gray level falls within 1/2 gray level is as wide as about 30 °. However, the reference voltage V _OFF1 set at T = 25 ° C. = 1.7 as shown by the broken line in the same gray scale in FIG.
If V is used as it is, the transmittance is remarkably reduced, and the color tone cannot be adjusted.

In the viewing angle correcting system in a multi-gradation display of the liquid crystal according to the present invention as described above, the drive voltage V ₁ of the black level is the lowest luminance and drive voltage V ₈ of the white level is the maximum luminance, as described above Since the fixed voltage is set with a sufficient voltage margin for the viewing angle change and the temperature change, it is irrespective of the change of the voltage variable means 1 and 2 for the correction of the viewing angle of the intermediate gradation and the temperature compensation as described above. Becomes Thus, even if the voltage variable means 1 or 2 is operated as described above, the maximum contrast in a monochrome display and the contrast of eight basic colors in a color panel are not reduced. The adjustment of the reference voltage V _OFF by the voltage variable means 2 for temperature compensation can be performed automatically by using a temperature compensation circuit as described later. This allows
Practically, the viewing angle correction in the multi-gradation display is performed by adjusting one point, and a liquid crystal multi-gradation display device which is extremely easy to use for the observer can be obtained.

FIG. 6 is a circuit diagram of a basic embodiment of a liquid crystal drive voltage generation circuit for multi-gradation display.

In a liquid crystal display device, since there is no direct current component in the drive voltage applied to the liquid crystal, it is necessary to perform an AC drive in which the drive voltage is alternately inverted between positive and negative polarities for each frame. Positive and negative drive voltages are required for such AC driving. Therefore, it is conceivable to provide two sets of the basic circuits shown in FIG. 2 to generate a drive voltage corresponding to the positive polarity and a drive voltage corresponding to the negative polarity.
However, in this case, the circuit scale becomes large, and the positive and negative drive voltages are not correctly matched due to the influence of the element characteristic variation. When the positive and negative drive voltages have such a variation, they are applied to the liquid crystal as a DC component, and there is a problem that the display life of the liquid crystal is extremely shortened.

In this embodiment, in order to solve the above-mentioned problem, a single basic circuit as shown in FIG. 2 is used to generate both positive and negative liquid crystal driving voltages.

The high-level voltage V _H and the low-level voltage _VL are equal to the resistance R ₈
And it is applied to the series circuit of the R _9, wherein the divided midpoint voltage is output as the drive voltage V _8. This midpoint voltage V ₈
The voltage variable means 2 is provided on the
V _OFF is formed and supplied to a resistor R ₆ of a series resistor circuit composed of resistors R ₁ to R ₆ forming six gradation voltages V ₂ to V ₇ . Voltage varying means 1 is provided to the resistor R ₁ which is the other end side of the series resistor circuit. Voltage variable means 1, in order to form a drive voltage for the AC as described above, the voltage V _L through the switch SW1 via the voltage V _H and the switch SW2 of the high level side of the low level side Are alternately switched and supplied. For example, for odd frames, switch SW1
There turned on, to no driving voltage V ₁ of the positive polarity by the high level V _H, the midpoint voltage V ₈ to form a V _8. Then, the switch SW2 is turned on when the even frame, to no driving voltage -V ₁ negative polarity by the low level V _L, the midpoint voltage V ₈ -
To form a V _8. In the figure, the driving voltages V ₁ to V ₈ is so switched in divided positive and negative when it is intended to omit the symbols indicating the polarity. The switch SW1
_VH and V supplied alternately by SW2 and SW2
_L is intended to be in the driving voltages V ₁ or -V ₁ corresponding to the first gradation.

In this configuration, the positive and negative drive voltages for AC drive of the liquid crystal can be formed from the common voltage variable means 1 and 2 for performing the above-described viewing angle correction and temperature compensation, and the series resistance. As a result, the circuit can be simplified and the positive and negative drive voltages can be correctly matched, so that no DC voltage is applied to the liquid crystal when driving alternately with positive and negative polarities.

FIG. 7 is a block diagram showing one embodiment of the TFT liquid crystal display device according to the present invention.

The liquid crystal display device shown in the figure is directed to 512 color display.

The interface unit corresponding to the microcomputer system or the like is configured by the timing converter TCON3. This timing converter uses standard color
Color data R0 to R5, G0 to G5 and B0 to B5 corresponding to R, G, B inputs of a CRT (cathode ray tube), and a horizontal synchronizing signal HSYN
C, receives a vertical synchronizing signal VSYNC, a display timing signal YDISP, etc., and converts it into a TFT liquid crystal driving signal for multi-color display. PLL is a phase locked loop circuit,
One dot clock pulse DOTCLK is formed.

The TFT panel is not particularly limited,
The scanning line electrodes are arranged to extend in the horizontal direction, and the signal line electrodes are arranged to extend in the vertical direction. One pixel is formed at the intersection of the scanning line electrode and the signal line electrode. 1
One pixel includes a pixel electrode and a TFT transistor. The gate of the TFT transistor is connected to a corresponding scan line electrode, and the drain of the TFT transistor is connected to a corresponding signal line electrode. Then, the source of the TFT transistor is connected to the pixel electrode. The TFT transistor is a MOSFET (insulated gate field effect transistor)
The signal is transmitted bidirectionally in the same manner as in the above. Therefore,
It is to be understood that the terms drain and source of the TFT transistor are for convenience.

The scanning line electrodes extending in the horizontal direction are sequentially selected by a gate driver. That is, the gate driver receives the frame signal FLM and the pulse CL3 corresponding to the scanning timing, and sequentially selects the scanning line electrodes from top to bottom. For this reason, the gate driver includes, but is not limited to, a dynamic shift register and a driver.

In this embodiment, although not particularly limited, the signal line electrodes extending in the vertical direction in the TFT panel are divided into an odd number and an even number, and a drain driver is provided corresponding to each. For example, the odd-numbered signal line electrodes are driven by a drain driver provided above the TFT panel, and the even-numbered signal line electrodes are driven by a drain driver provided above the TFT panel. By distributing the drivers up and down in this way, the pitch of the signal line electrodes as viewed from the driver side can be widened, and the mounting of the driver can be facilitated. Further, by allocating the signal line electrodes as described above, it is possible to easily adopt a configuration in which the odd and even signal line electrodes are supplied with drive voltages having polarities different from each other.

Timing converter TCON3 corresponds to the upper and lower drain drivers distributed as described above.
Upper data and output data are transferred by one signal bus. The clock pulses CL2U and CL2L are used for serially inputting data in units of 12 bits through the signal bus. That is, the clock pulse CL2U is supplied to the upper drain driver and the lower drain driver.
The upper data and the lower data are serially transferred in units of 12 bits in synchronization with the data and CL2L, respectively.

The clock pulse CL1 is the serially transferred 1
It is used to latch data for a line. That is, the clock pulse CL1 is generated when data transfer for one line is completed, holds the transferred data, forms a drive voltage for one line based on the data, and applies the drive voltage to the scanning line electrode selected by the gate driver. The data is written in parallel to the corresponding pixels for one line.

In parallel with the writing to the liquid crystal pixels as described above, serial capture of data corresponding to the next line is performed using the clock pulses CL2U and CL2L.

The power supply stabilization circuit receives two voltages, such as + 5V and -24V, and requires + 5V and -20V for the operation of the drive voltage generation circuit.
A stabilizing voltage as shown in FIG. The power stabilization circuit
Display control signal DISP / ON from timing converter TCON3
In response, the operation is validated.

The drive voltage generation circuit is basically composed of a circuit as shown in FIG. The variable resistor for adjusting the viewing angle constitutes the voltage varying means 1.

In this embodiment, as described above, the drain driver of the TFT panel is divided into odd-numbered signal line electrodes and even-numbered signal line electrodes, and the configuration is such that the polarity of the driving voltage is different, This is to simultaneously generate two types of drive voltages, positive and negative. The alternating signal M formed by the timing converter TCON3 is a signal that alternates between a high level and a low level for each frame, and instructs to switch the polarity of the driving voltage for AC driving of the liquid crystal. The drive voltage generation circuit receives the AC signal M and alternately switches the polarity of the lower driver drive voltage and the upper driver drive voltage. Explaining the basic circuit of FIG. 6, the AC signal M is used to control the alternate switching of the switches SW1 and SW2.

FIG. 8 is a block diagram showing an embodiment of a main part of the drain driver.

The drain driver in FIG. 3 exemplarily shows a circuit related to the two signal line electrodes Y2 and Y4 in the lower drain driver. Note that the upper drain driver is also formed of a similar circuit, and the corresponding signal line electrodes are shown in parentheses for reference.

In order to perform eight gradation display, data for one pixel is composed of three bits. Therefore, a signal bus for transferring 12-bit data is divided into three bits. Data D ₀
To D ₂ is taken into the latch circuit corresponding to the signal line electrode Y2 (2). Data D ₃ to D ₅ is taken into the latch circuit corresponding to the next signal line electrode Y4 (2). The remaining data D ₆ to D ₈ and the data D ₉ to D ₁₁ is an unillustrated signal line electrodes Y6
And the latch times (2) corresponding to Y8, respectively.
As a result, the color pixel data serially transferred in 12-bit units becomes 4 pixels in one cycle of the clock CL2L.
The signal is taken into the latch circuit corresponding to the signal line electrode.

For example, if the signal line electrodes of the TFT panel are each composed of 640 lines corresponding to R, G and B, the lower drain driver drives even numbered signal line electrodes composed of 320 × 3 lines. Data for one line is taken in by 3/4 = 240 (cycles). Since the upper drain driver also drives the odd-numbered signal line electrodes composed of 320 lines, data for one line such as 320 × 3/4 = 240 (cycles) is written within the same time as the lower driver. take in.

The color data for one line is stored in the latch circuit (2).
When 12 bits are input serially, they are transferred to the latch circuit (1) in parallel by the clock pulse CL1 during the horizontal retrace period. When the above-described parallel transfer is completed, the latch circuit (2) serially captures color data corresponding to the next line. The color data captured by the latch circuit (1) is supplied to a voltage selector. Voltage selector decodes the color data consisting of the three bits, to no driving voltages V ₁ corresponding to 8 gray-scale to form a selection signal corresponding to one of the drive voltage from the V _8. As a result, the drive voltage of the gradation corresponding to the color data is transmitted to the signal line electrode via the switch. TFT
In the panel, one scanning line electrode is selected by the gate driver, and the corresponding TFT transistor is turned on. Therefore, the driving voltage is applied to the pixel electrode via the turned on TFT transistor. Written.

As described above, the latch circuits (1) and (2) and the decoder circuit are constituted by logic circuits operating at 5V and 0V. In contrast, when the to no driving voltages V ₁ and the switch selectively convey the V ₈ is constituted by MOSFET, certain V ₈ to the voltages V ₁ does not need to tell without level losses by the gate voltage of the MOSFET. Therefore, the voltage selector, level of converting the optionally switch control signals formed by the logic levels of 5V system as described above, the gate voltage level of the MOSFET needed to convey the voltages V ₁ to V ₈ A conversion function is added.

FIG. 9 is a circuit diagram showing one embodiment of a motherboard in a multi-tone liquid crystal display device according to the present invention.
On the motherboard, a semiconductor integrated circuit device LSI that constitutes the timing converter TCON3, an IC 3 for a PLL and an IC 3 for a stabilized power supply, and discrete components such as a bipolar transistor, a resistor, a diode, and a capacitor, and an op amp are formed. A plurality of ICs are mounted.

This motherboard and the driver board on which the TFT panel is mounted are connected by a flexible wiring board FPC. The terminals PC, DU, and DL are terminals to which these flexible wiring boards FPC are connected. The terminal DU corresponds to the upper drain driver, and the DL corresponds to the lower drain driver.

The drive voltage generation circuit is composed of discrete components such as a bipolar transistor, a resistor, a diode and a capacitor as described above, and a plurality of ICs constituting an op-amp.

FIG. 10 is a circuit diagram of one embodiment of the drive voltage generation circuit. The circuit shown in FIG. 14 corresponds to a circuit in which only the drive voltage generating circuit is extracted from FIG.

The operating voltages of +5 V (Vcc) and -20 V (V _EE ) formed by the stabilized power supply circuit described in detail later are the high-level voltage _VH and the low-level voltage shown in FIG. _VL and corresponding. A resistor R ₈ that are disposed in series between the voltage resistance R ₉ form a midpoint voltage V _N as -7.5V.

Midpoint voltage V _N is transmitted to the node b via the operational amplifier circuit IC _4, which is the voltage follower configuration. The operational amplifier circuit IC ₄ performs an impedance conversion operation and outputs
The midpoint voltage V _N is a voltage source of low output impedance.

PNP transistor with emitter connected to positive voltage Vcc
And T2, NPN transistor T3 whose emitter is connected to the negative voltage V _EE corresponds to the switches SW1 and SW2 shown in the Figure 6. The inverter circuit IC ₂₀ and IC _21, a PNP transistor T1 and its collector resistance forms a control signal for complementarily switching operation in accordance with the AC signal M of the transistors T2 and T3. The AC signal M is supplied to the input of the inverter circuit IC ₂₀ , and the output signal is transmitted to the base of the transistor T1. The output signal of the inverter circuit IC ₂₀ is supplied to the base of the transistor T2 via the inverter circuit IC _21. As a result, the transistors T1 and T2 are turned on / off complementarily to the AC signal M. The collector output signal of the transistor T1 is transmitted to the base of the transistor T3.

When the AC signal M is at the high level, the output signal of the inverter circuit IC ₂₀ goes to the low level, turning on the PNP transistor T1. As a result, a current flows through the collector and the PNP transistor T3 is turned on. The inverter circuit IC ₂₀ according to the high level of the AC signal M
Output signal is made low level, so the inverter circuit IC
The output signal of ₂₁ is made high. This allows PNP
The transistor T2 is turned off. The above transistor T3
There when it is in the ON state, the negative voltage V _EE of -20V is transmitted to the node a via the transistor T3.

When the AC signal M is at a low level, the output signal of the inverter circuit IC ₂₀ is at a high level, and the PNP transistor T1 is turned off. As a result, since no current flows through the collector, the NPN transistor T3 is turned off. Since the output signal of the inverter circuit IC ₂₀ is set to the high level in accordance with the low level of the AC signal M, the output signal of the inverter circuit IC ₂₁ is set to the low level. As a result, the PNP transistor T2 is turned on. When the transistor T2 is turned on, the transistor T2
, A positive voltage Vcc of +5 V is transmitted to node a.

Such a node a, in response to high and low levels of the alternating signal M, on the basis of the midpoint voltage V _N at the node b and the positive voltage Vcc and negative voltage V _EE is conveyed et alternately switched .

In this embodiment, although not particularly limited, the node a
Between the reference voltage V _OFF and the viewing angle θ
A voltage generating circuit for generating a viewing angle correcting voltage V _K which is varied in accordance with are provided. Resistors R _13, R ₁₄ and R ₁₅ and the thermistor R _S1 as the temperature sensing element generates the viewing angle correcting voltage V _K. That is, the resistance R ₁₄ becomes a fixed resistor and a variable resistor are connected in series, to vary the angle correction voltage V _K by adjusting the variable resistor. This resistance R
₁₄ a series circuit of a resistor R ₁₅ and the thermistor R _S1 is provided in parallel to the. As can be seen from the characteristic diagram shown in FIG. 4, this thermistor R _{S1 not} only changes the reference voltage V _OFF due to a change in temperature, but also changes the gradient itself of the change in luminance approximated by the hypotenuse of a right triangle. I do. Therefore, it is intended to use the negative characteristic that the resistance value of the thermistor R _S1 is reduced in response to temperature increases, to decrease the visual angle correction voltage V _K. Combined resistance consisting of the resistor R ₁₄ resistor R ₁₅ and the thermistor R _S1 is the thermistor R _S1 in accordance with the above temperature is higher
Becomes smaller as the resistance value of the becomes smaller. Accordingly, the voltage formed by the resistance ratio of these combined resistance value and the resistance R ₁₃ is lowered. The divided voltage is further divided by the variable resistor R _14. Therefore, viewing angle correction voltage V _k decreases with increasing temperature acts to increase the inclination of the luminance.

Incidentally, in an actual circuit, the viewing angle compensation voltage V _K can be omitted. That is, the driving voltage V ₂ corresponding to the second gradation is changed to the viewing angle θ.
The operation equivalent to that described with reference to FIG. Therefore, in this embodiment it is intended to form a drive voltage V ₂ to perform direct viewing angle correcting operation by circuitry to not the resistor R ₁₃ as the voltage varying means 1 consisting of R ₁₅ and the thermistor R _S1. For this reason in which the driving voltage V ₂ corresponding to the direct second gradation from the variable voltage terminal of the variable resistor R ₁₄ is formed. The drive voltage is output is impedance conversion by the operational amplifier circuit IC ₂ which is a voltage follower configuration.

Resistors R _16, R ₁₇ and R ₁₈ and the thermistor R _S2 generates the reference voltage V _OFF. That is, the resistance R ₁₇ becomes a fixed resistance and the adjustment resistor is connected in series, in the assembly process and the inspection process of the liquid crystal display device, correcting variation such as a TFT panel and the resistive element by adjusting the adjustment resistor To set the reference voltage V _OFF . This adjustment resistor
The R ₁₇ series circuit of a resistor R ₁₈ and the thermistor R _S2 are provided in parallel. The thermistor R _S2 automatically corrects the reference voltage V _OFF according to the temperature dependency of the liquid crystal, as is clear from the characteristic diagram shown in FIG. That is, the reference voltage V _OFF is reduced by using the negative characteristic that the resistance value of the thermistor R _S2 decreases as the temperature increases. Resistor R ₁₇ and resistor R ₁₈ and thermistor R
Combined resistance consisting of _S2 is smaller in response to the resistance value of the thermistor R _S2 in accordance with the temperature rises is reduced. Accordingly, the voltage formed by the resistance ratio of these combined resistance value and the resistance R ₁₆ is lowered. The divided voltage is further divided by the adjusting resistor R _17. Therefore, the reference voltage V _OFF decreases as the temperature rises, and the temperature compensation as shown in FIG. 4 is automatically performed. The reference voltage V _OFF is output is impedance conversion by the operational amplifier circuit IC ₃ which is in the voltage follower configuration.

Viewing angle compensation voltage V _K can be replaced by a drive voltage V ₂ as described above. However, as described above with reference to FIG. 1, the reference voltage V _OFF is a reference voltage of two or more right triangles that are configured in response to a change in the viewing angle θ. It should be noted that this is the voltage that must actually be present in the series resistor circuit that forms the gray scale liquid crystal drive voltage.

Between the output terminal of the operational amplifier IC ₂ and the IC ₃ to no series resistor R ₁ form a V ₇ from the intermediate gray scale voltage V ₃ is R _{6 'is} provided. It not the resistor R ₁ R _5, the resistance R ₁ shown in FIG. 2
To be a resistive element having mutually equal resistance values corresponding to R _5. In contrast, the resistance R _{6 'is} to have a combined resistance value of the resistor R ₆ and R ₇ shown in Figure 1.

The output terminal of the operational amplifier circuit IC ₂ and the series resistor R ₁
To the intermediate gray scale voltage V ₂ to V ₇ are outputted from the interconnection point of the R ₆ through the IC ₅ to no operational amplifier circuit IC ₁₀ is in a voltage follower configuration, the liquid crystal drive voltage corresponding to the upper drain driver It is no V _2U is output as V _7U.

Further, the operational amplifier halftone voltage V ₂ to V ₇ to the output terminal of the IC ₂ and without the series resistor R ₁ is outputted from the interconnection point of the R ₆ are inverting amplifier circuit IC with voltage gain is 1
₁₇ through to IC _12, is outputted as V _7L to no liquid crystal drive voltage V _2L corresponding to the drain driver lower. The inverting amplifier circuit amplifying circuit IC ₁₇ to IC ₁₂ is made operational amplifier, an inverting input - an input resistor provided in, ()
Inverting input (-) and by resistance supplying the midpoint voltage V _N is provided to the feedback resistor and the non-inverting input (+) is arranged between the output terminal, each intermediate floor inputted from the respective output terminals it is intended to output a V _7L to no liquid crystal drive voltage V _2L polarity is inverted respectively adjusting the voltage V ₂ to V _7.

100% transmittance of the liquid crystal drive voltage V ₈ corresponding to the (white level)
Is, the midpoint voltage V _N is used. That is, the operational amplifier circuit
The voltage of the node b obtained through IC ₄ is supplied in common to the drain driver of the upper and lower liquid crystal drive voltage V ₈ as it is.

Drive voltage V ₁ corresponding to liquid crystal transmittance of 0% (black level)
, The voltage is switched to + 5V or -20V of the node a is formed is level-shifted by the bidirectional level shift circuit consisting of a Zener diode ZD ₁ and ZD ₂ and the diode D ₁ and D _2. That is, when the voltage of the node a is a positive voltage such as +5 V, the Zener diode ZD ₂
Diode D ₂ is turned on to determine the level shift amount by the Zener voltage and the diode forward voltage.
When the voltage of the node a is a negative voltage such as -20V is zener diode ZD ₁ diode D ₁ is turned on, to determine the level shift amount by the Zener voltage and the diode forward voltage. Resistor R ₁₂ which is provided in series with the level shift circuit is intended to flow the operating current of the level shift circuit.

The voltage at the node c, which has been level-shifted by the level shift circuit, is output as the liquid crystal drive voltage V _1U supplied to the upper drain driver via the operational amplifier circuit IC ₁₁ in the same manner as described above. It is output as the liquid crystal drive voltage V _1L supplied to the lower drain driver via the circuit IC ₁₈ .

The level shift circuit is provided for the following reason. A gate driver shown in FIG. 7, the above positive voltage Vcc and negative selection receives the voltage V _EE level is +5, the non-select level to form the output signal as a -20 V. That is, + 5V or -20V as described above is applied to the gate of the TFT transistor. By providing a level shift circuit as described above, the maximum voltage + V ₁ and a minimum voltage -V ₁ to TFT drain (or source) is applied to the signal line electrode coupled is set by the level shift circuit as described above by the level shift amount based on the midpoint voltage V _N is determined in the positive and negative symmetrically.

By setting the level shift amount larger than the threshold voltage of the TFT transistor, the drive voltage of the signal line electrode is transmitted to the selected pixel electrode without level loss when the TFT transistor is turned on. be able to.

Resistor R ₁₀ and R ₁₁ and a series circuit consisting adjustment resistor is input to the operational amplifier circuit IC ₁ which is a voltage follower configuration. The operational amplifier circuit IC ₁ 'forms a common voltage V _com supplied to the common electrode of the liquid crystal panel. That is, TFT
A pixel electrode provided via a transistor constitutes a capacitor equivalent to the common electrode, and a driving voltage transmitted when the TFT is in an ON state is applied with reference to the common voltage _com on the common electrode side, When the TFT is turned off, the driving voltage is maintained. Incidentally, and it operates by receiving and also all other operational amplifier Vcc and V _EE as the operational amplifier circuit IC ₁ and the operational amplifier circuit IC _4. By using such an operation voltage, the liquid crystal driving voltage V _1U ~V _7U being switched positive and negative with respect to the mid-point voltage V _N
And V _{1L to} V _7L can be formed.

FIG. 11 is a circuit diagram of another embodiment of the drive voltage generation circuit.

In this embodiment, a voltage dividing resistor circuit corresponds to the upper drain driver and the lower drain driver, respectively.
R _{1 to} R ₅ and R _{1 ′ to} R _{5 ′} are provided. The driving voltages V _{1U to} V _7U supplied to the upper drain driver and the driving voltages V _{1L to} V 7V supplied to the lower drain driver
_In order to reverse the polarity of _7L as in the embodiment of FIG. 10,
Voltages of opposite polarities are applied to the voltage dividing resistance circuits R _{1 ′ to} R _{5 ′} that form the driving voltage supplied to the lower drain driver. That is, the operational amplifier circuit IC _{2 ′} operating as an inverting amplifier circuit includes the resistors R ₁₃ , R ₁₄ and R ₁₅ and the thermistor R _S1 as a temperature sensing element based on the potential of the node b.
A voltage obtained by inverting the polarity of the correction voltage V _K (actually, as described above, the driving voltage V _2U corresponding to the second gradation) formed by the viewing angle correction voltage generating circuit, Supply to R _{1 '} side. Thereby, the operational amplifier circuit IC ₂
And IC _{2 '} output viewing angle correction voltages having polarities opposite to each other. An operational amplifier circuit IC that operates as an inverting amplifier circuit
_{3 ',} resistor R ₁₆ with respect to the potential of the node b, R ₁₇
And forming the reference voltage voltage obtained by inverting the polarity of the reference voltage V _OFF formed by generating circuit consisting of a thermistor R _S2 as R ₁₈ and the temperature-sensitive element, and supplies the voltage dividing resistors R _{5 'side.} Thus, the operational amplifier IC ₃ and IC _{3 'outputs} a reference voltage of opposite polarities. Therefore, the voltage dividing resistor circuit
Driving voltages V _{1U to} V _7U and V _{1L to} V _7L having opposite polarities can be formed from respective interconnection points of R _{1 to} R ₅ and R _{1 ′ to} R _{5 ′} . Therefore, in this embodiment, the operational amplifier circuit IC ₅ ~IC ₁₀ corresponding to the upper side of the drain driver
The operational amplifier circuit IC ₁₂ ~IC ₁₇ corresponding to the drain driver lower in the same manner as is also the voltage follower configuration. However, since the drive voltage V _1L is formed not by the voltage _dividing resistor circuit but by the level shift circuit as described above, the operational amplifier circuit IC _{18 that} operates as an inverting amplifier circuit is used.
Formed by

In this configuration, because it to an operational amplifier circuit resistance element unnecessary voltage follower configuration to form a driving voltage V _2L ~V _7L corresponding to the drain driver lower, resistor divider R _{1 '~} Even if the necessity of R5 _' is newly taken into consideration, the number of elements constituting the drive voltage generation circuit as a whole can be reduced.

The remaining circuit portions other than the above-described configuration are the same as those of the embodiment circuit shown in FIG. 10, and the description thereof will be omitted.

FIG. 12 shows a drive waveform diagram for explaining an example of the operation of the TFT panel. The upper side shows a waveform corresponding to the upper drain driver, and the lower side shows a waveform corresponding to the lower drain driver.

The gate driving waveform output by the gate driver is such that a low voltage of V _EE = −20 V is set to a non-selection level, and Vcc =
A high voltage of + 5V is set as the selection level.

Midpoint voltage between the high voltage Vcc and the low voltage V _EE V _N (-7.5V)
Is the center potential, and the positive voltages V _{1 to} V ₇ for AC driving the liquid crystal
Negative voltage V ₁ ~V ₇ is formed with. The drive voltage V ₈ is the midpoint voltage
Set equal to V _N. In the figure, an intermediate voltage for the multi-gradation display, and V ₂ and V ₇ are illustratively shown,
During both the voltages V ₂ and V ₇ is equal remaining intermediate voltage voltage V ₃ ~V ₆
Is formed. Voltage V ₈ corresponding to the voltage V ₁ and the white level corresponding to the black level for such halftone voltage V ₂ and V ₇
Is also set with a relatively large margin.

The polarity of the output voltage of the upper driver is opposite to the polarity of the output voltage of the lower driver as shown in FIG. For example, as shown in the figure, in the first frame, a negative driving voltage is output from the upper driver, and a positive driving voltage is output from the lower driver. In the next frame, the upper driver outputs a positive drive voltage,
A lower driving voltage is output from the lower driver.
Although not shown in the figure, such polarity switching is performed by the high level and the low level of the AC signal M.

FIG. 13 is a circuit diagram of an embodiment of the power supply stabilizing circuit. The circuit shown in FIG. 9 is obtained by extracting a power supply stabilizing circuit from the circuit diagram of the motherboard shown in FIG.

The control signal DISPON is a signal generated by the timing converter TCON3 and instructing the start of a liquid crystal display operation. That is, if an unstable voltage is supplied to the liquid crystal drive voltage generation circuit immediately after the power is turned on and before the timing converter TCON3 starts operating normally, an unsightly drive voltage is applied to the liquid crystal, causing an unsightly display. It is to prevent that.

That is, when the control signal DISP ON is low, the output signal of the inverter circuit IC ₂₂ becomes high level, to turn off the PNP transistor T4. This turns off the Darling-connected PNP transistors T6 and T7 that transmit a negative high voltage such as -24V. As a result, the PNP transistor T5 is turned on, and the transistors T7 and T6 are turned off. These transistors
Since the operating voltage is not supplied to the stabilized power supply IC 3 due to the OFF state of T7 and T6, a stabilized voltage such as -20 V is not output.

When the control signal DISP ON is at the high level, the output signal of the inverter circuit IC ₂₂ becomes low level, the PNP transistor T4 ON state. This allows the transistor
The collector potential of T4 becomes high level close to Vcc, turning off the transistor T5. Therefore, -24V is supplied to the base of the Darling-connected PNP transistor T7 that transmits a negative high voltage such as -24V, and turns on these transistors T7 and T6. The ON state of the transistors T7 and T6, the operating voltage of the low potential side is supplied to the stabilized power supply IC3, regulated voltage V _EE as -20V is formed.

Incidentally, the power supply stabilizing circuit of this embodiment, a negative voltage such as -24V is supplied before the positive voltage Vcc, such as + 5V is supplied, an emitter of the transistor T5 ground voltage through the diode D ₄ The transistor T5 is turned on, and the transistors T7 and T6 are turned off. This prevents a negative voltage such as −24 V from being supplied to the power stabilizing IC 3 first.

FIG. 14 is a rear mounting view of one embodiment of the multi-tone liquid crystal display device according to the present invention.

The figure shows a back view of the multi-tone liquid crystal display device. Although not particularly limited, a tab (TAB) is provided on the driver substrate which is formed in an inverted U shape corresponding to the upper and lower sides and the left side of the TFT panel (not shown), and the upper and lower tabs are semiconductors constituting a drain driver. An integrated circuit device is mounted, and a semiconductor integrated circuit constituting a gate driver is mounted on a left tab in FIG.

The tab is provided with a wiring pattern for connecting an output terminal of a semiconductor integrated circuit device such as a drain driver or a gate driver mounted on the tab to a corresponding signal line electrode and scanning line electrode of a TFT panel. Thus, the driver substrate on which the tab and the semiconductor integrated circuit device as described above are mounted and the TFT panel are assembled thin so as to form substantially the same plane.

In a conventional liquid crystal display device based on a single tone, the motherboard can be made relatively small because the drive voltage can be a binary voltage of white and black. As a result, in the conventional liquid crystal display device based on a single gray scale, it is arranged so as to form a substantially same plane as the TFT panel similarly to the driver substrate.

However, in a multi-gradation liquid crystal display device such as this embodiment, a large number of semiconductor integrated circuit devices and discrete components as shown in FIG. Implement For this reason, it is essential that the motherboard on which these electronic components are mounted be made larger than in the past. By arranging such a large motherboard on the substantially same plane as the TFT panel like the above driver board, the entire configuration of the liquid crystal display device has a large frame portion around the display screen. In addition, there arises a problem that left and right or up and down become asymmetric.

For this reason, in this embodiment, the motherboard and the driver board are connected by the flexible wiring board FPC, and the motherboard is placed on the back side of the TFT panel. That is, the TFT panel and the motherboard are configured to be overlapped so as to sandwich the backlight plate.

FIG. 15 is a front view of another embodiment of the multi-tone liquid crystal display device according to the present invention. In the figure,
In order to facilitate understanding of the structure, a flexible wiring portion is drawn out. In this embodiment, the TFT
A tab (TAB) is provided on the driver substrate, which is formed in an inverted U-shape corresponding to the upper and lower sides of the (LCD) panel, and a semiconductor integrated circuit device constituting a drain driver is provided on the upper and lower tabs. The semiconductor integrated circuit device constituting the gate driver is mounted on the left tab in FIG. The tab is provided with a wiring pattern for connecting an output terminal of a semiconductor integrated circuit device such as a drain driver or a gate driver mounted on the tab to a corresponding signal line electrode and scanning line electrode of a TFT panel. Thus, the driver substrate on which the tab and the semiconductor integrated circuit device as described above are mounted and the TFT panel are assembled thin so as to form substantially the same plane. Further, two flexible wiring FPCs are provided on the right side of the driver board, for connecting the driver board to the motherboard arranged on the rear side.

FIG. 16 is a side view of another embodiment of the multi-tone liquid crystal display device according to the present invention. The side view of FIG.
This corresponds to the front view shown in FIG. As in this embodiment, a TFT panel and a driver board are provided on the front side with the backlight therebetween, and a motherboard is provided on the back side. Then, both are connected by a flexible wiring FPC. In this case, the motherboard and the flexible wiring FPC
And are connected by a connector. Such a sandwich structure sandwiching the backlight is the same in the multi-tone liquid crystal display device shown in FIG. That is, in the embodiment of FIG. 14, the method of attaching the flexible wiring FPC is only slightly different.

FIG. 17 is a rear view of another embodiment of the multi-gradation liquid crystal display device according to the present invention. The rear view of the figure is
This corresponds to the front view shown in FIG. Also in this embodiment, as shown in the figure, the motherboard is provided so as to completely overlap the TFT panel and the driver board. That is, the driver board and the motherboard are overlapped so as to sandwich a backlight (not shown). Therefore, even if the size of the motherboard is increased in order to mount the voltage generation circuit for multi-gradation driving as described above, it is possible to prevent an increase in the overall size of the liquid crystal display device as viewed from the front side. .

Next, a TFT panel (LCD panel) used in the multi-tone liquid crystal display device according to the present invention will be described in detail.

FIG. 18A is a plan view showing an embodiment of one pixel and its peripheral portion of an active matrix type color liquid crystal display device to which the present invention is applied. FIG.
FIG. 2 shows a cross section of the embodiment along a section line IIB-IIB in the drawing and a cross sectional view near a seal portion of the display panel. 18th C
The figure shows a cross-sectional view of one embodiment taken along section line IIC-IIC in FIG. 18A. Fig. 19 (Plan view of main part)
Shows a plan view of one embodiment when a plurality of pixels shown in FIG. 18A are arranged.

(Pixel Arrangement) As shown in FIG. 18A, each pixel has two adjacent operation signal lines (gate signal lines or horizontal signal lines) GL and two adjacent video signal lines (drain signal lines or vertical signal lines). Line) DL
(In a region surrounded by four signal lines). Each pixel includes a thin film transistor TFT, a pixel electrode ITO1, and an additional capacitance Cadd. The scanning signal lines GL extend in the column direction, and a plurality of the scanning signal lines GL are arranged in the row direction. The video signal lines DL extend in the row direction and are arranged in a plurality in the column direction.

(Overall structure of panel cross section) As shown in FIG. 18B, a thin film transistor TFT and a transparent pixel electrode ITO1 are formed on the lower transparent glass substrate SUB1 side with respect to the liquid crystal layer LC, and on the upper transparent glass substrate SUB2 side,
A color filter FIL and a light shielding black matrix pattern BM are formed. The lower transparent glass substrate SUB1 side has a thickness of, for example, about 1.1 (mm).

The center part in FIG. 18B shows a cross section of one pixel portion, while the left side shows a cross section of a left edge portion of the transparent glass substrates SUB1 and SUB2 where an external lead-out line exists. The right side shows a cross section of a portion on the right side edge of the transparent glass substrates SUB1 and SUB2 where there is no external lead-out wiring.

Seal material SL shown on the left and right sides of FIG. 18B
Are configured to seal the liquid crystal LC, and the transparent glass substrates SUB1 and SU except for the liquid crystal filling port (not shown)
It is formed along the entire periphery of the edge of B2. Seal material SL
Is formed of, for example, an epoxy resin.

The common transparent pixel electrode IT on the upper transparent glass substrate SUB2 side
O2 is connected to the external lead-out wiring formed on the lower transparent glass substrate SUB1 side by the silver paste material SIL at at least one place. This external lead-out wiring is formed in the same manufacturing process as each of the gate electrode GT, the source electrode SD1, and the drain electrode SD2 described above.

Each layer of the alignment films ORI1 and ORI2, the transparent pixel electrode ITO1, the common transparent pixel electrode ITO2, the protective films PSV1 and PSV2, and the insulating film GI is formed inside the sealing material SL. With polarizing plate POL1
POL2 is lower transparent glass substrate SUB1, upper transparent glass substrate
It is formed on the outer surface of each of SUB2.

The liquid crystal LC is a lower alignment film ORI1 that sets the orientation of liquid crystal molecules.
And the upper alignment film ORI2, and is sealed by a seal portion SL.

The lower alignment film ORI1 is formed above the protective film PSV1 on the lower transparent glass substrate SUB1 side.

On the inner (liquid crystal side) surface of the upper transparent glass substrate SUB2, a light-shielding film BM, a color filter FIL, a protective film PSV2, a common transparent pixel electrode (COM) ITO2, and an upper alignment film ORI2 are sequentially laminated. .

In this liquid crystal display device, the respective layers on the lower transparent glass substrate SUB1 side and the upper transparent glass substrate SUB2 side are separately formed, and then the upper and lower transparent glass substrates SUB1 and SUB2 are overlapped, and the liquid crystal LC is sealed between the two. Assembled by

(Thin Film Transistor TFT) The thin film transistor TFT operates so that the channel resistance between the source and the drain decreases when a positive bias is applied to the gate electrode GT, and the channel resistance increases when the bias is set to zero.

The thin film transistor TFT of each pixel has 2 pixels in the pixel.
And a plurality of thin film transistors (divided thin film transistors) TFT1 and TFT2. Each of the thin film transistors TFT1 and TFT2 has substantially the same size (the same channel length and width). Each of the divided thin film transistors TFT1 and TFT2 mainly includes a gate electrode GT, a gate insulating film GI, and an i-type (intrinsic, intrinsic).
sic, not doped with conductivity determining impurities) Amorphous S
i Semiconductor layer AS, a pair of source electrode SD1 and drain electrode SD
It consists of two. It should be understood that the source and the drain are originally determined by the bias polarity between them, and the polarity of the circuit of the present display device is inverted during the operation, so that the source and the drain are switched during the operation. However, also in the following description, for convenience, one is fixed as a source and the other is fixed as a drain.

(Gate electrode GT) The gate electrode GT is shown in FIG. 20 (layers g1, g2 and AS in FIG. 18A).
Scan signal line as shown in detail in the plan view)
It is configured to protrude vertically (upward in FIGS. 2A and 4) from the GL (branched into a T-shape). The gate electrode GT is a thin film transistor TFT1, TFT2
Are formed so as to protrude to the respective formation regions. The respective gate electrodes GT of the thin film transistors TFT1 and TFT2 are integrally formed (as a common gate electrode) and are formed continuously with the scanning signal line GL. The gate electrode GT is formed of a single-layer first conductive film g1 so as not to form a large step in a region where the thin film transistor TFT is formed. The first conductive film g1 is, for example, a chromium (Cr) film formed by sputtering, and is formed of a thin film of about 1000 (Å).

As shown in FIGS. 18A, 18B, and 20, the gate electrode GT is formed to be larger than that (as viewed from below) so as to completely cover the semiconductor layer AS. Therefore, when a backlight BL such as a fluorescent lamp is mounted below the substrate SUB1, the opaque Cr gate electrode GT becomes a shadow and the semiconductor layer AS is not irradiated with the backlight, and the conductive phenomenon due to light irradiation, that is, Deterioration of off-characteristics of the TFT hardly occurs. Note that the original size of the gate electrode GT is the minimum necessary to extend between the source / drain electrodes SD1 and SD2 (including the alignment margin between the gate electrode and the source / drain electrodes).
It has a width, and its depth length that determines the channel width W is the ratio to the distance (channel length) L between the source and drain electrodes, that is, a factor that determines the transconductance gm
It is determined by the number of W / L.

The size of the gate electrode in this embodiment is, of course, larger than the original size described above.

Considering only from the function of the gate and the light shielding function of the gate electrode GT, the gate electrode GT and its wiring GL may be integrally formed in a single layer, in which case Al containing Si as an opaque conductor material, Al or the like containing pure Al and Pd can be selected.

(Scanning Signal Line GL) The scanning signal line GL is formed of a composite film including a first conductive film g1 and a second conductive film g2 provided thereon. The first conductive film g1 of the scanning signal line GL is formed in the same manufacturing process as the first conductive film g1 of the gate electrode GT, and is integrally formed. The second conductive film g2 is, for example, an aluminum (Al) film formed by sputtering,
It is formed with a thickness of about 4000 (Å). The second conductive film g2 is configured so that the resistance value of the scanning signal line GL can be reduced, and the signal transmission speed can be increased (the information writing characteristics of the pixel can be improved).

Further, the scanning signal line GL is configured such that the width of the second conductive film g2 is smaller than the width of the first conductive film g1. That is, the scanning signal line GL has a gentle step shape on the side wall.

(Gate Insulating Film GI) The insulating film GI is used as each gate insulating film of the thin film transistors TFT1 and TFT2. The insulating film GI is formed above the gate electrode GT and the scanning signal line GL. In the first example, the insulating film GI is formed to have a thickness of about 3000 (Å) using a silicon nitride film formed by plasma CVD.

(Semiconductor Layer AS) As shown in FIG. 20, the i-type semiconductor layer AS is used as each channel forming region of the thin-film transistors TFT1 and TFT2 divided into a plurality. The i-type semiconductor layer AS is formed of an amorphous silicon film or a polycrystalline silicon film, and has a thickness of about 1800 (Å).

This i-type semiconductor layer AS is made of Si ₃ N
_{Fourth, following} the formation of the gate insulating film GI, the gate insulating film GI is formed in the same plasma CVD apparatus without being exposed to the outside from the apparatus. Similarly, a P-doped N ⁺ layer d0 (FIG. 18B) for ohmic contact is continuously formed to a thickness of about 400 (Å). Thereafter, the lower substrate SUB1 is taken out of the CVD apparatus, and the N ⁺ layer d0 and the i layer
AS is patterned into independent islands as shown in FIGS. 18A, 18B and 20.

The i-type semiconductor layer AS is also provided between both intersections (crossover portions) of the scanning signal lines GL and the video signal lines DL, as shown in detail in FIGS. 18A and 20. The intersection i-type semiconductor layer AS is configured to reduce a short circuit between the scanning signal line GL and the video signal line DL at the intersection.

(Source / drain electrodes SD1, SD2) The source electrode SD1 and the drain electrode SD2 of each of the thin-film transistors TFT1, TFT2 divided into a plurality
As shown in detail in FIG. 18, FIG. 18B, and FIG. 21 (a plan view showing only the layers d1 to d3 in FIG. 18A), they are separately provided on the semiconductor layer AS.

The source electrode SD1 and the drain electrode SD2 are respectively connected to the first conductive film d1 and the second conductive film d1 from the lower side in contact with the N ⁺ type semiconductor layer d0.
The conductive film d2 and the third conductive film d3 are sequentially overlapped. The first conductive film d1, the second conductive film d2, and the third conductive film d3 of the source electrode SD1 are formed in the same manufacturing process as each of the drain electrode SD2.

The first conductive film d1 is formed of a chromium film formed by sputtering, and has a thickness of 500 to 1000 (Å) (in this embodiment, a thickness of about 600 (Å)). The chromium film is formed in a range that does not exceed about 2,000 (Å) because the stress increases when the chromium film is formed thick. The chromium film has good contact with the N ⁺ type semiconductor layer d0. The chromium film constitutes a so-called barrier layer that prevents aluminum of a second conductive film d2 described later from diffusing into the N ⁺ type semiconductor layer d0. As the first conductive film d1, a high melting point metal (Mo, Ti, Ta, W) film or a high melting point metal silicide (MoSi ₂ , TiSi ₂ , TaSi ₂ , WSi ₂ ) film in addition to the chromium film described above. It may be formed.

After patterning the first conductive film d1 by photo processing, the N ⁺ layer d0 is removed using the same photo processing mask or using the first conductive film d1 as a mask. That is, it remained on the i-layer AS
The portion of the N ⁺ layer d0 other than the first conductive film d1 is removed by self-alignment. At this time, since the N ⁺ layer d0 is etched so as to completely remove its thickness, the i layer AS is also slightly etched at its surface, but the degree may be controlled by the etching time.

Thereafter, the second conductive film d2 is formed to have a thickness of 3000 to 4000 (Å) by sputtering aluminum (in the present embodiment, 3000 to 4000 (Å)).
(Å) film thickness]. The aluminum layer has a smaller stress than the chromium layer and can be formed to have a large thickness, and the source electrode SD1 and the drain electrode SD2 can be formed.
And the resistance value of the video signal line DL is reduced. The second conductive film d2 may be formed of an aluminum film containing silicon (Si) or copper (Cu) as an additive in addition to the aluminum film.

After patterning the second conductive film d2 by a photoprocessing technique, a third conductive film d3 is formed. This third conductive film d3 is a transparent conductive film (Induim-Tin-Oxide) formed by sputtering.
ITO (Nesa film), and is formed to a thickness of 1000 to 2000 (Å) (in this embodiment, a thickness of about 1200 (Å)). The third conductive film d3 forms the source electrode SD1, the drain electrode SD2, and the video signal line DL, and also forms the transparent pixel electrode ITO1.

Each of the first conductive film d1 of the source electrode SD1 and the first conductive film d1 of the drain electrode SD2 is formed by an upper second conductive film d2 and a third conductive film d2.
It is deeper inside (into the channel region) than the conductive film d3. That is, the first conductive film d1 in these portions is configured so that the gate length L of the thin film transistor TFT can be defined regardless of the layers d2 and d3.

The source electrode SD1 is, as described above, a transparent pixel electrode ITO1.
It is connected to the. The source electrode SD1 is an i-type semiconductor layer AS
(The film thickness of the first conductive film d1, the film thickness of the N ⁺ layer d0, and i
Step equivalent to the film thickness obtained by adding the film thickness of the semiconductor layer AS)
It is configured along. Specifically, the source electrode SD1
Represents a first portion formed along the step shape of the i-type semiconductor layer AS.
A conductive film d1, a second conductive film d2 formed on the upper side of the first conductive film d1 and connected to the transparent pixel electrode ITO1 with a smaller size, and a first conductive film exposed from the second conductive film. And a third conductive film d3 connected to the film d1.
Since the second conductive film d2 of the source electrode SD1 cannot form a thick chrome film of the first conductive film d1 due to an increase in stress and cannot overcome the step of the i-type semiconductor layer AS, the second conductive film d2 is It is configured to get over. That is, the step coverage is improved by forming the second conductive film d2 to be thick. Since the second conductive film d2 can be formed thick, it greatly contributes to a reduction in the resistance value of the source electrode SD1 (the same applies to the drain electrode SD2 and the video signal line DL).
Since the third conductive film d3 cannot overcome the stepped shape caused by the i-type semiconductor layer AS of the second conductive film d2, the first conductive film exposed by reducing the size of the second conductive film d2
It is configured to connect to d1. The first conductive film d1 and the third conductive film d3 not only have good adhesiveness, but also have a small step at the connection between them, so that they can be reliably connected.

(Pixel Electrode ITO1) The transparent pixel electrode ITO1 is provided for each pixel, and constitutes one of the pixel electrodes of the liquid crystal display unit. Transparent pixel electrode ITO1 is a thin-film transistor divided into multiple pixels
It is divided into two transparent pixel electrodes (divided transparent pixel electrodes) E1 and E2 corresponding to TFT1 and TFT2, respectively. The transparent pixel electrodes E1 and E2 are connected to the source electrode SD1 of the thin film transistor TFT, respectively.

Each of the transparent pixel electrodes E1 and E2 is patterned so as to have substantially the same area.

In this manner, the thin film transistor TFT of one pixel is divided into a plurality of thin film transistors TFT1 and TFT2, and each of the plurality of divided thin film transistors TFT1 and TFT2 is connected to each of the plurality of divided transparent electrodes E1 and E2. Even if the divided part (for example, TFT1) becomes a point defect, it is not a point defect when viewed as a whole pixel (TFT2 is not a defect), so that the probability of a point defect can be reduced. Further, it is possible to make the defect hard to see.

Further, by forming each of the divided transparent pixel electrodes E1 and E2 of the pixel with substantially the same area, each liquid crystal formed by each of the transparent pixel electrodes E1 and E2 and the common transparent pixel electrode ITO2 is formed. The capacity (Cpix) can be made uniform.

(Protective film PSV1) On the thin film transistor TFT and the transparent pixel electrode ITO1,
A protective film PSV1 is provided. The protective film PSV1 is mainly formed to protect the thin film transistor TFT from moisture and the like, and uses a film having high transparency and good moisture resistance. The protective film PSV1 is formed of, for example, a silicon oxide film or a silicon nitride film formed by plasma CVD, and has a thickness of 8000
It is formed so as to have a film thickness of (Å).

(Light-shielding film BM) A light-shielding film BM is provided on the upper substrate SUB2 side so that external light (light from above in FIG. 18B) does not enter the i-type semiconductor layer AS used as a channel formation region. No.
The pattern is as shown by hatching in FIG.
FIG. 22 is a plan view illustrating only the ITO film, the layer d3, the filter layer FIL, and the light shielding film BM in FIG. 18A. The light-shielding film BM is formed of, for example, an aluminum film or a chromium film having a high light-shielding property. In this embodiment, the chromium film is formed to a thickness of about 1300 (Å) by sputtering.

Therefore, the common semiconductor layers AS of the TFTs 1 and 2 are sandwiched by the upper and lower light shielding films BM and the large gate electrodes GT, and the portions are not exposed to external natural light or backlight. The light-shielding film BM is formed around the pixel as shown by the hatched portion in FIG. That is, the light-shielding film BM is formed in a lattice shape (black matrix), and an effective display area of one pixel is partitioned by the lattice. Therefore, the outline of each pixel is made clear by the light shielding film BM, and the contrast is improved. That is, the light shielding film BM
Has two functions of shading the semiconductor layer AS and a black matrix.

The backlight can be attached to the SUB2 side, and SUB1 can be the observation side (externally exposed side).

(Common electrode ITO2) The common transparent pixel electrode ITO2 faces the transparent pixel electrode ITO1 provided for each pixel on the lower transparent glass substrate SUB1 side, and the optical state of the liquid crystal is between each pixel electrode ITO1 and the common pixel electrode ITO2. Changes in response to the potential difference (electric field) of. The common transparent pixel electrode ITO2 is configured to apply a common voltage Vcom. The common voltage Vcom is an intermediate potential between the low-level drive voltage Vdmin and the high-level drive voltage Vdmax applied to the video signal line DL.

(Color Filter FIL) The color filter FIL is formed by coloring a dye on a dyeing base material formed of a resin material such as an acrylic resin.
The color filter FIL is formed in a dot shape for each pixel at a position facing the pixel (FIG. 23) and is dyed separately (FIG. 23 shows the third conductive film d3, the black matrix layer BM and the color shown in FIG. 19). Only the filter layer FIL is drawn.
The R, G, and B filters are 45 °, 135 ° and cross hatched, respectively.)

The color filter FIL has a pixel electrode I as shown in FIG.
The light-shielding film BM is formed larger than the periphery of the pixel electrode ITO1 so as to cover all of the TO1 (E1, E2) and overlap the color filter FIL and the edge of the pixel electrode ITO1.

The color filter FIL can be formed as follows. First, a dyed base material is formed on the surface of the upper transparent glass substrate SUB2, and the dyed base material other than the red filter forming region is removed by photolithography. Thereafter, the dyed substrate is dyed with a red dye and subjected to a fixing treatment to form a red filter R. Next, by performing similar steps, a green filter G and a blue filter B are sequentially formed.

The protective film PSV2 is provided in order to prevent the dye obtained by dyeing the color filter FIL into different colors from leaking into the liquid crystal LC. The protective film PSV2 is, for example, an acrylic resin,
It is formed of a transparent resin material such as an epoxy resin.

(Equivalent Circuit of Entire Display Panel) FIG. 24 shows a connection diagram of an equivalent circuit of the display matrix portion and its peripheral circuits. The figure is a circuit diagram, but is drawn corresponding to an actual geometric arrangement. AR is a two-dimensional matrix array of a plurality of pixels.

In the figure, X means a video signal line DL, and suffixes G, B and R
Are added corresponding to the green, blue and red pixels, respectively. Y means a scanning signal line GL, and suffixes 1, 2, 3,.
End is added according to the order of the scanning timing.

The video signal lines X (subscripts omitted) are alternately connected to the upper (or odd) video signal drive circuit He and the lower (or even) video signal drive circuit Ho.

SUP is a power supply circuit for obtaining a plurality of divided and stabilized voltage sources from one voltage source, and information for a CRT (cathode ray tube) from a host (upper processing unit) for TFT liquid crystal display panels. This is a circuit that includes a circuit for converting to.

(Structure of additional capacitance Cadd) Each of the transparent pixel electrodes E1 and E2 is a thin film transistor T
The end opposite to the end connected to the FT is formed so as to overlap with the adjacent scanning signal line GL. This superposition is, as is clear from FIG. 18C, the transparent pixel electrode E
A storage capacitance element (capacitance element) Cadd in which each of the electrodes E1 and E2 is one electrode PL1 and the adjacent scanning signal line GL is the other electrode PL2. The dielectric film of the storage capacitor Cadd is formed of the same layer as the insulating film GI used as the gate insulating film of the thin film transistor TFT.

As is apparent from FIG. 20, the storage capacitor Cadd is formed at a portion where the width of the first layer g1 of the first layer g1 of the gate line GL is increased. The portion of the layer g1 that intersects with the drain line DL
Are thinned to reduce the probability of short circuit with the drain line.

A portion between each of the transparent pixel electrodes E1 and E2 overlapped to form the storage capacitor Cadd and the capacitor electrode line (g1) is similar to the source electrode SD1 when a transparent pixel is crossed over the stepped shape. An island region in which the first conductive film d1 and the second conductive film D2 are formed is provided so that the electrode ITO1 is not disconnected. This island region is configured to be as small as possible so as not to reduce the area (opening ratio) of the transparent pixel electrode ITO1.

(Equivalent Circuit of Additional Capacitor Cadd and Its Operation) FIG. 25 shows an equivalent circuit of the pixel shown in FIG. 18A.
In FIG. 25, Cgs is a dielectric film of a parasitic capacitance Cgs formed between the gate electrode GT and the source electrode SD1 of the thin film transistor TFT, and is an insulating film GI. Cpix is a transparent pixel electrode ITO1 (PI
X) and the liquid crystal capacitance formed between the common transparent pixel electrode ITO2 (COM). The dielectric films of the liquid crystal capacitor Cpix are the liquid crystal LC, the protective film PSV1, and the alignment films ORI1, ORI2. Vlc is the midpoint potential.

The holding capacitance element Cadd functions to reduce the influence of the gate potential change ΔVg on the midpoint potential (pixel electrode potential) Vlc when the TFT switches. When this state is expressed by an equation, ΔVlc = {Cgs / (Cgs + Cadd + Cpix)} × ΔVg. Here, ΔVlc represents a change in the midpoint potential due to ΔVg. The change ΔVlc causes a DC component applied to the liquid crystal, but the value can be reduced as the storage capacitance Cadd is increased.

In addition, the storage capacitor Cadd also has a function of prolonging the discharge time, and stores video information after the TFT is turned off for a long time. LCD L
The reduction of the DC component applied to C improves the life of the liquid crystal LC, and can reduce so-called image sticking in which a previous image remains when the liquid crystal display screen is switched.

As described above, the gate electrode GT is enlarged so as to completely cover the semiconductor layer AS, so that the source / drain electrode SD
1, The area of overlap with SD2 increases, so the parasitic capacitance C
As gs increases, the midpoint potential Vlc has an adverse effect of being easily affected by the gate (scan) signal Vg. However, this disadvantage can be eliminated by providing the storage capacitor Cadd.

The storage capacitance of the storage capacitance element Cadd is 4 to 8 times (4 · Cpix <) the liquid crystal capacitance Cpix due to the writing characteristics of the pixel.
Cadd <8 · Cpix), 8 to 32 for overlay capacity Cgs
It is set to a value of about double (8 · Cgs <Cadd <32 · Cgs).

(Connection method of additional capacitance Cadd electrode line) First stage scanning signal line GL used only as capacitance electrode line
(Y ₀ ) is a common transparent pixel electrode (Vc) as shown in FIG.
om) Connect to ITO2. Common transparent pixel electrode ITO2 is 18B
As shown in the figure, the periphery of the liquid crystal display device is connected to an external lead-out wiring by a silver paste material SL. In addition, some of the conductive layers (g1 and g2) of the external lead wiring are formed in the same manufacturing process as the scanning signal line GL. As a result, the last stage capacitor electrode line GL can be easily connected to the common transparent pixel electrode ITO2.

The first-stage capacitor electrode line Y ₀ is connected to the last-stage scan signal line Y _end , connected to a DC potential point (AC ground point) other than Vcom, or an extra scan pulse Y ₀ is supplied from the vertical scanning circuit V. It may be connected to receive.

In the above embodiment, an inverted staggered structure in which a gate electrode is formed, a gate insulating film is formed, a semiconductor layer is formed, and a source / drain electrode is formed is described.

FIG. 26 is a conceptual diagram for explaining another embodiment of the multi-tone liquid crystal display device according to the present invention.

If you increase the size of the TFT panel and, when viewing is brought closer eyes even relatively small size of the TFT panels, as shown in the figure, as the viewing angle theta ₁ with respect to the upper portion of the TFT panel relatively small but increases as the viewing angle theta ₂ is relative to the lower. This means that, as described with reference to FIG. 1, when the visual correction is performed on the upper part of the TFT panel, the lower part where the visual angle becomes larger from θ ₁ to θ ₂ ,
As a result, the area where the luminance of the liquid crystal changes linearly shifts to the left as a whole, and the gradation shifts toward the lower side of the TFT panel.

In the present inventor, when the TFT panel is enlarged as described above, or when there is a viewing angle difference between the upper and lower sides of the TFT panel, such as when the TFT panel is relatively small and the eyes are brought closer to each other. It has been found that this causes non-uniformity of gradation in a multi-gradation display of liquid crystal. And
Such non-uniformity of the gradation in the vertical direction of the TFT panel can also be caused by a difference in the vertical viewing angle. Therefore, the above-described characteristic of the change in the luminance characteristic curve of the liquid crystal with respect to the viewing angle change is used. I noticed that it could be dynamically corrected. That is, the inventor of the present application has considered a dynamic viewing angle correction method in which the viewing angle correction voltage is sequentially changed in synchronization with the vertical scanning timing of the TFT panel.

FIG. 27 shows a circuit diagram of an embodiment of a correction voltage generation circuit corresponding to a vertical viewing angle difference of a TFT panel.

In this embodiment, linear circuit technology is used. The operational amplifier OP1 forms an integrating circuit with its input resistance, feedback resistance, and capacitor, and inputs a frame pulse (vertical synchronization signal) FLM. This makes it possible to generate a sawtooth voltage synchronized with the frame period. In this case, since the integration circuit integrates the positive pulse FLM, the voltage decreases with time. By superimposing the voltage to the upper viewing angle theta ₁ correction voltage set based on the TFT panel, as the viewing angle as the viewing angle theta ₂ is increased, as described with reference to the Figure 1 viewing The correction voltage can be gradually reduced. Operational amplifier OP
2, the sawtooth formed by the integration circuit is used as a voltage amplifier for adjusting a voltage level and as a buffer amplifier. Sawtooth-shaped correction voltage d formed by such a correction voltage generation circuit
Is formed.

FIG. 28 is a circuit diagram of an embodiment of a drive voltage generation circuit including a correction voltage generation circuit corresponding to the vertical viewing angle difference of the TFT panel.

As the correction voltage waveform generation circuit, a correction voltage generation circuit using the integration circuit shown in FIG. 27 is used. The correction voltage waveform generating circuit sawtooth correction voltage d formed by the resistor and through a capacitor, the viewing angle compensation voltage generation whose AC component is composed of a resistor R ₁₃ to R ₁₅ and a thermistor R _S1 as described above It is superimposed on the DC correction voltage formed by the circuit. That is, the correction voltage d is superimposed on the correction voltage V ₂ corresponding to the second gradation is supplied to the input of the buffer amplifier IC ₂ of the voltage follower configuration (+). Thus, the liquid crystal driving voltage V ₂ ~V ₇ used in the actual display of the multi-tone is reduced and the display position in response to the above sawtooth correction voltage d as facing down is superimposed, above Such visual correction can be dynamically corrected in synchronization with the vertical scanning timing of the liquid crystal.

Note that the clock pulse CL1 input to the correction voltage waveform generation circuit in the figure is not used in the correction voltage generation circuit composed of the linear circuit shown in FIG.

FIG. 29 is a block diagram showing another embodiment of the correction voltage generation circuit corresponding to the vertical viewing angle difference of the TFT panel.

In this embodiment, digital circuit technology is used.
The counter is a binary counter for counting the clock pulse CL1, and its reset terminal RST has a frame pulse F1.
LM is inverted and supplied through an inverter circuit. Thus, the counter is reset every frame.
From the above counting operation and resetting operation, it will be understood that the counter counts the number of selected scanning lines of the TFT panel.

Count output C ₀ -C _n of the counter is input to the decoder circuit constituted by a ROM (read only memory), where it is converted into a digital signal D ₀ to D ₇ corresponding to the address of the scan line . That is, the address is converted into 256 kinds of addresses by the 8-bit signal as described above. For example, if the number of scanning lines on a TFT panel is about 500, conversion is performed so that one address is assigned to every two lines,
If the number is about 1000, conversion is performed so that one address is assigned to every four addresses.

Digital signal D ₀ to D ₇ of 8 bits converted by the ROM, the digital / analog conversion circuit (hereinafter, simply referred to as D / A converter) is input to. This D
The / A converter captures the input digital signal in synchronization with the clock pulse CL1, forms a similar saw-tooth analog voltage corresponding to the digital value, and outputs the analog voltage. In this D / A conversion operation, a down counter is used as a counter for counting the clock pulse CL1, or a ROM is used in order to form a saw-tooth voltage in which the voltage level decreases with the passage of time as in the above-described embodiment. and to perform a decoding operation that varies from the maximum value to the minimum value may be formed digital signal D ₀ to D ₇ as described above in.

The sawtooth voltage signal obtained from the output AO of the D / A converter is supplied to the drive voltage generating circuit in the same manner as described above as a dynamic viewing angle correction voltage d through an amplifier using an operational amplifier circuit. The amplifier is used not only as a buffer amplifier, but also for adjusting the visual angle correction amount dynamically by adjusting the gain.

As a method of setting the visual angle correction amount, a static correction voltage may be obtained in each of the upper part and the lower part, and a saw-tooth voltage may be formed such that the difference voltage has a peak. Alternatively, the adjustment may be performed by adjusting the gain of the amplifier circuit that outputs the sawtooth voltage while watching the display screen.

FIG. 30 is a schematic perspective view of one embodiment of a laptop (or book) microcomputer using the multi-tone liquid crystal display device according to the present invention.

The microcomputer of this embodiment includes a keyboard 30
As a main unit, and a liquid crystal module (hereinafter, referred to as
A multi-tone liquid crystal display device 10) can be opened and closed. That is, when not using or carrying the microcomputer, the multi-tone liquid crystal display device 10 is closed so as to overlap the keyboard portion. Then, when using the microcomputer, open the keyboard 30 and the multi-tone liquid crystal display device 10 as the main body,
It is set as shown in FIG.

At this time, in a place where the apparatus is used, lighting of a ceiling, scenery outside a bright window, and the like are often reflected on a display screen, which makes reading of characters and the like troublesome. In such a case, generally, the variable means 20 is operated to set the multi-gradation liquid crystal display device in a state close to vertical, in other words,
In many cases, the open angle of the multi-tone liquid crystal display device is reduced so that the display screen is viewed from above. At this time,
By operating the viewing angle adjustment volume as described above, the display screen can be viewed with the correct gradation for monochrome display and with the correct color tone for color display.

For example, assuming that the microcomputer is used on a desk, an angle sensor is provided in the variable means 20 for adjusting the open angle of the multi-tone liquid crystal display device with respect to the keyboard main body 30, and the sensor corrects the viewing angle correction voltage by a detection signal. Is automatically changed. In this way, when the same person uses the microcomputer, once the visual angle correction is performed by the above-described volume operation, the visual angle correction is automatically performed even when the opening angle of the multi-tone liquid crystal display device 10 is changed. Can be performed.

Further, when the screen of the multi-tone liquid crystal display device 10 is enlarged, the gradation or the color tone may change due to the difference in the vertical viewing angle, but the dynamic viewing angle correction as described above is performed. Is performed, it is possible to always perform display with correct gradation or color tone.

The operational effects obtained from the above embodiment are as follows. That is, (1) an approximate reference voltage is obtained from an intersection on an extension line of a straight line along a slope of a luminance-voltage characteristic corresponding to at least two viewing angles different from each other in a vertical direction with respect to the liquid crystal display panel, and the viewing angle is determined. And a driving voltage for multi-gradation display corrected by a divided voltage linked to this voltage is formed, thereby obtaining 1
By adjusting the location, a plurality of driving voltages for multiple gradations can be changed along the gradient of the luminance-voltage characteristic corresponding to the viewing angle, so that the gradation display can be easily adjusted with respect to the vertical change of the viewing angle. In addition, the effect of being able to be performed accurately is obtained.

(2) A voltage dividing circuit that forms a drive voltage for multi-tone display linked to a voltage that is changed in accordance with the viewing angle with respect to the reference voltage that is approximately determined, in accordance with an alternating signal of the liquid crystal. By supplying the operation voltage whose polarity has been inverted through the switch circuit, it is possible to obtain an effect that an AC drive voltage for the liquid crystal can be generated with a simple configuration.

(3) The multi-gradation drive voltage formed by the voltage dividing circuit is output through a voltage follower circuit and an inverting amplifier circuit that performs phase inversion, and the output voltage corresponds to every other signal line of the liquid crystal panel. By supplying each of the drive circuits corresponding to the vertically divided drive circuits, it is possible to obtain a write voltage with a simple configuration that is less affected by capacitive coupling.

(4) The voltage dividing circuit comprises two voltage dividing circuits. One of the voltage dividing circuits is supplied with an operating voltage whose polarity is inverted according to the AC signal through the switch circuit, and the other voltage dividing circuit is supplied with the polarity. Supply the operating voltage via the inverting amplifier circuit,
By supplying the divided output voltages of these two voltage divider circuits via the voltage follower circuit to the drive circuits divided up and down corresponding to every other signal line of the liquid crystal panel, respectively, the buffer amplifier is provided. The effect that simplification becomes possible is obtained.

(5) By automatically compensating the reference voltage by a temperature compensation circuit corresponding to the temperature dependency, it is possible to obtain an effect that the number of adjustment points can be substantially one.

(6) By supplying the operating voltage subjected to the viewing angle correction and the temperature compensation to the voltage dividing circuit via a buffer amplifier having a low output impedance, the voltage dividing circuit and the voltage compensating circuit and the temperature compensating circuit are compared with each other. Therefore, it is possible to easily set the respective voltages.

(7) The voltage passed through the switch circuit for forming the liquid crystal AC drive voltage is supplied to a level shift circuit for forming a bidirectional level shift voltage corresponding to the effective threshold voltage of the TFT transistor, By forming an absolute maximum driving voltage applied to the liquid crystal signal line via the level shift circuit, an effect that reliable writing to pixels can be obtained is obtained.

(8) The mounting substrate on which the power supply circuit for generating the driving voltage for multi-gradation is mounted is superposed on the back side of the liquid crystal display panel so as to sandwich the backlight, thereby providing a large size as viewed from the front side. The effect is obtained that it is possible to prevent the conversion.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention of the present application is not limited to the embodiment, and it can be said that various modifications can be made without departing from the gist of the invention. Not even. For example, the voltages of each gradation need not be equally divided, and may have an offset as needed. That is, the voltage dividing ratio of the voltage dividing resistance circuit may be slightly shifted. The gray levels may be set to 8 gray levels or 4 gray levels. For example, when four gradations are used, color display of 4 × 4 × 4 = 64 colors is possible.

The circuit for generating the reference voltage and the voltage for temperature compensation may be inserted in series with the voltage dividing circuit for generating the driving voltage for multiple gradations. In this case, a level shift circuit can be used as a reference voltage or a voltage generation circuit for temperature compensation.

The multi-tone liquid crystal display device may be used for a color television receiver. However, since the above-described drive voltage generating circuit is used, it is only necessary that the video signals separated into RGB are converted into digital signals of 3 bits each. In this case, since the video signal for television is formed in the interlaced mode, the video signal is temporarily stored in the frame memory, a positive voltage is written to the pixel corresponding to the odd frame, and the video signal is written in the even frame. A negative voltage may be written accordingly.

The reference voltage and the viewing angle correction voltage can also be used when writing an analog voltage to the liquid crystal. That is, the black level of the analog voltage is changed to the viewing angle correction voltage V _K as shown in FIG.
To adjust the white level to correspond to the threshold voltage _VTH . That is, the amplitude of the analog signal may be changed in the range of the voltage V _K ~V _TH. That is,
In the present invention, the analog signal as described above is also captured as one form of a substantial gradation display. Even in this case, the color tone can be easily and accurately corrected for the viewing angle.

INDUSTRIAL APPLICABILITY The present invention can be widely used for a multi-tone liquid crystal display device and a drive voltage generation circuit thereof.

〔The invention's effect〕

The effect obtained by the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, an approximate reference voltage is obtained from an intersection on an extension line of a straight line along the slope of the luminance-voltage characteristic corresponding to at least two viewing angles different from each other in the vertical direction with respect to the liquid crystal display panel, and the approximate reference voltage is obtained. To form a drive voltage for multi-tone display corrected by the divided voltage in conjunction with the voltage, thereby forming a plurality of voltages for multi-tone display by one adjustment. Since the drive voltage can be changed along the gradient of the luminance-voltage characteristic corresponding to the viewing angle, the gradation display can be easily and accurately adjusted with respect to the vertical change of the viewing angle. Then, an operation voltage whose polarity is inverted according to the AC signal of the liquid crystal is supplied to a voltage dividing circuit for forming a driving voltage for multi-gradation display through a switch circuit, so that the AC driving voltage can be easily configured. Can be generated.

[Brief description of the drawings]

FIG. 1 is a characteristic diagram for explaining the principle of a viewing angle correction method in multi-gradation display of a liquid crystal according to the present invention, and FIG. 2 is a drive voltage generating circuit having a viewing angle correction function in multi-gradation display. FIG. 3 is a luminance-viewing angle curve diagram obtained by adjustment using the voltage variable means 1, and FIG. 4 is a temperature characteristic in a multi-tone display of a liquid crystal according to the present invention. FIG. 5 is a characteristic diagram for explaining the principle of the viewing angle correction method in consideration of the above, FIG. 5 is a luminance-viewing angle curve diagram by voltage adjustment using the voltage variable means 1 and 2, and FIG. FIG. 7 is a circuit diagram showing a basic embodiment of a liquid crystal drive voltage for the present invention, FIG. 7 is a block diagram showing an embodiment of a TFT liquid crystal display device according to the present invention, and FIG. FIG. 9 is a block diagram showing an embodiment, and FIG. 9 is a multi-tone liquid crystal table according to the present invention. FIG. 10 is a circuit diagram showing one embodiment of the drive voltage generation circuit, and FIG. 11 is a circuit diagram showing another embodiment of the drive voltage generation circuit. FIG. 12, FIG. 12 is a driving waveform diagram for explaining an example of the operation of the TFT panel, FIG. 13 is a circuit diagram showing one embodiment of the power supply stabilizing circuit, and FIG. Rear view showing one embodiment of the multi-tone liquid crystal display device according to the present invention, FIG. 15 is a front view showing another embodiment of the multi-tone liquid crystal display device according to the present invention, and FIG. 17 is a side view of another embodiment of the liquid crystal display device, FIG. 17 is a rear view of another embodiment of the multi-tone liquid crystal display device, and FIG. 18A is an active matrix to which the present invention is applied. FIG. 18B is a plan view of one embodiment of one pixel and its peripheral portion of the system color liquid crystal display device. FIG. 18C is a cross-sectional view of an embodiment taken along the line IIC-IIC in FIG. 18A, and FIG. FIG. 18A is a plan view showing an embodiment in which a plurality of pixels are arranged, FIG. 20 to FIG. 22 are plan views depicting only predetermined layers shown in FIG. 18A, FIG. FIG. 19 is a plan view showing only a pixel electrode layer and a color filter layer shown in FIG. 19; FIG. 24 is an equivalent circuit diagram showing a liquid crystal display portion of an active matrix type color liquid crystal display device; FIG. 18A is an equivalent circuit diagram of the pixel shown in FIG. 18A, FIG. 26 is a conceptual diagram for explaining another embodiment of the multi-tone liquid crystal display device according to the present invention, FIG. FIG. 28 is a circuit diagram showing one embodiment of a correction voltage generating circuit corresponding to the viewing angle difference in the direction, FIG. FIG. 29 is a circuit diagram showing an embodiment of a drive voltage generation circuit including a correction voltage generation circuit corresponding to an angle difference. FIG. 29 is another circuit diagram of a correction voltage generation circuit corresponding to a vertical viewing angle difference of a TFT panel. FIG. 30 is a block diagram showing an embodiment, FIG. 30 is a schematic perspective view showing an embodiment of a laptop microcomputer using the multi-tone liquid crystal display device according to the present invention, and FIG. FIG. 4 is a characteristic diagram for explaining. V _OFF … Reference voltage, V _K … Viewing angle correction voltage, V _TH … Threshold voltage, V _{1 to} V ₈ … Multi-grayscale drive voltage, SW1, SW2… Switch, TCON3… Timing converter, FPC: Flexible wiring, OP1, OP2: Operational amplifier circuit, ROM: Decoder SUB: Transparent glass substrate, GL: Scanning signal line, DL: Video signal line, GI: Insulating film, GT: Gate Electrode, AS ... i
Type semiconductor layer, SD: Source electrode or drain electrode, PSV
… Protective film, LS… Shielding film, LC… Liquid crystal, TFT… Thin film transistor, ITO… Transparent electrode, g, d… Conductive film, Cadd
…… Retention capacitance element, Cgs …… Overlapping capacitance, Cpix …… Liquid crystal capacitance (subscripts of numbers after English letters are omitted).

──────────────────────────────────────────────────続 き Continued on the front page (72) Nobutake Konishi 4026 Kuji-cho, Hitachi City, Ibaraki Prefecture Inside Hitachi Research Laboratory, Hitachi, Ltd. (56) References JP-A-63-135995 (JP, A) JP-A-62-2 34133 (JP, A) (58) Field surveyed (Int. Cl. ⁶ , DB name) G02F 1/133 G09G 3/36

Claims (12)

(57) [Claims] 1. A liquid crystal display panel having a TFT active matrix configuration is approximately determined based on intersections on extensions of straight lines respectively extending along slopes of luminance-voltage characteristics corresponding to at least two viewing angles different vertically. A circuit for generating a required reference voltage; a voltage dividing circuit for forming a driving voltage for multi-gradation display interlocked with the reference voltage and a correction voltage that is changed in accordance with the viewing angle; And a switch circuit for supplying a voltage-reversed operating voltage to the voltage dividing circuit. 2. The multi-gradation driving voltage formed by the voltage dividing circuit according to claim 1,
The driving voltage supplied to the voltage follower circuit and the inverting amplifier circuit for receiving the output voltage and inverting the phase is supplied to the signal follower circuit and the inverting amplifier circuit. A multi-gradation liquid crystal display device, which is supplied in correspondence with drive circuits that are allocated up and down in response to the above. 3. The voltage dividing circuit according to claim 1, wherein the voltage dividing circuit comprises two voltage dividing circuits, and one of the voltage dividing circuits is supplied with an operating voltage whose polarity is inverted according to an AC signal through the switch circuit. The operating voltage is supplied to the voltage dividing circuit via a polarity inversion amplifier circuit, and the divided output voltages of these two voltage dividing circuits are respectively applied to every other signal line of the liquid crystal panel via a voltage follower circuit. A multi-gradation liquid crystal display device, which is supplied corresponding to a drive circuit which is correspondingly divided up and down. 4. The multi-gradation liquid crystal display device according to claim 1, wherein the reference voltage is automatically temperature-compensated by a temperature compensation circuit corresponding to the temperature dependency. 5. The multi-gradation liquid crystal display device according to claim 1, wherein an operating voltage is supplied to said voltage dividing circuit via a buffer amplifier having a low output impedance. 6. The liquid crystal display according to claim 1, wherein a voltage passed through a switch circuit for forming the liquid crystal alternating drive voltage is a bidirectional level corresponding to an effective threshold voltage of the TFT transistor. A multi-tone liquid crystal display device, which is supplied to a level shift circuit for forming a shift voltage, and forms an absolute maximum drive voltage applied to a liquid crystal signal line via the level shift circuit. . 7. A voltage for switching polarity through a switch circuit controlled by an alternating signal of the liquid crystal according to any one of claims 1 to 3, is supplied to a viewing angle correction or temperature compensation voltage generation circuit. A multi-gradation liquid crystal display device wherein the generated voltage is supplied to a voltage dividing circuit for forming a multi-gradation driving voltage through a buffer amplifier having a low output impedance. 8. A liquid crystal display panel having a TFT active matrix configuration having a group of gate lines and a group of drain lines, and gate line driving means for driving the group of gate lines.
In the multi-tone liquid crystal display device comprising the drain line driving means for driving the drain wiring group, each driving voltage corresponding to the halftone display luminance is generated from the voltage dividing means, and the driving voltage of the maximum and the minimum amplitude is generated. The voltage is generated without passing through the voltage dividing means. Further, these driving voltages are supplied to the drain line driving means, and the driving voltage having the maximum amplitude and the driving voltage for halftone display are periodically generated. And a switch means disposed outside the drain line driving means so as to switch between two-level voltages. 9. A multi-gradation liquid crystal display device according to claim 8, wherein said voltage dividing means comprises a plurality of resistance elements connected in series. 10. A liquid crystal display panel having a TFT active matrix configuration having a group of gate lines and a group of drain lines, and gate line driving means for driving the group of gate lines.
In the multi-tone liquid crystal display device comprising the drain line driving means for driving the drain wiring group, each driving voltage corresponding to the halftone display luminance is generated from the voltage dividing means, and the driving voltage of the maximum and the minimum amplitude is generated. Voltages are generated without passing through the voltage dividing means.Furthermore, these driving voltages are supplied to the drain line driving means, and the driving voltages having the maximum and minimum amplitudes are respectively set to minimum and maximum display brightness. Correspondingly, the driving voltage having the maximum amplitude corresponding to the minimum display luminance is not affected by the rebound characteristic of the characteristic curve that the display luminance increases as the amplitude of the driving voltage increases near the display luminance of zero. A multi-gradation liquid crystal display device characterized by setting with a sufficient margin. 11. A liquid crystal display panel having a TFT active matrix configuration having a group of gate lines and a group of drain lines, and gate line driving means for driving the group of gate lines.
In the multi-tone liquid crystal display device comprising the drain line driving means for driving the drain wiring group, each driving voltage corresponding to the halftone display luminance is generated from the voltage dividing means, and the driving voltage of the maximum and the minimum amplitude is generated. The voltage is generated without passing through the voltage dividing means.Furthermore, these driving voltages are supplied to the drain line driving means, and all of the maximum amplitude driving voltage and the halftone display driving voltage are A multi-gradation liquid crystal display device wherein a voltage is set to a positive side or a negative side with respect to the driving voltage having the minimum amplitude also in a driving time. 12. The first driving period according to claim 11, wherein an operation period in which each of the driving voltage having the maximum amplitude and the driving voltage for halftone display is periodically switched between two-level voltages by the switching means is included in the first driving period. An operation period in which each of the maximum amplitude drive voltage and the halftone display drive voltage is set to the first voltage so as to be set to the positive side with respect to the minimum amplitude drive voltage. In the second drive period, which alternates with the first drive period, each of the drive voltage having the maximum amplitude and the drive voltage for halftone display is a negative voltage with respect to the drive voltage having the minimum amplitude. A multi-level liquid crystal display device, comprising: an operation period in which each of the second voltages is set so as to be set.