JP2993342B2 - Microprocessor control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor as a core of an information processing system.

[0002]

2. Description of the Related Art Generally, a microprocessor is provided with a plurality of registers, performs arithmetic processing using data in a main memory or a register, and executes a program by writing an arithmetic result to the main memory or a register. . These registers are collectively called a register file. Usually, the total number of registers in the register file is 32, that is, about 32 words. CISC (Complex Instruction)
In a processor using an architecture called an "ion Set Computer" architecture, data in a main memory can be specified by an operation instruction, and an operation can be directly performed using data on the specified memory. On the other hand, RISC (Reduced Instrument)
Microprocessor using an architecture called an “action set computer” architecture or a load / store architecture is
Processing between main memory and registers is limited to load and store. That is, data in the main memory can be accessed only by load / store instructions. The arithmetic processing is performed by designating the data loaded in the register by an arithmetic instruction and performing the processing. In either type of architecture, access to data on the main memory is performed in units of words or less specified by instructions. Here, the word is the size of a register in the architecture, and is usually 32 bits or 6 bits.
It is 4 bits.

Regardless of the architecture of a microprocessor, a small-scale buffering memory (hereinafter referred to as a buffer memory) generally called a cache memory is generally provided between a main memory and a register. The buffer memory speeds up program execution by utilizing the fact that a small memory device can be accessed faster than a large memory device and that locality exists in access to the main memory. It is used to convert This was conceived because the access time to the main memory is longer than the instruction processing time of the microprocessor, and the access time to the main memory is a cause of performance degradation. Generally, a buffer memory is composed of a plurality of buffer lines,
When certain data on the main memory is accessed by, for example, a load instruction or the like, an area having a size corresponding to a buffer line including the data is copied from the main memory and held in the buffer memory. At this time, data actually accessed by a load instruction or the like is loaded from the buffer memory to the register. Which buffer line holds the copied main memory area is determined by using a part of the main memory address. The unit of data transfer between the buffer memory and the register is limited to the word unit or less since the access to the main memory is specified in the word unit or less.

When a program to be executed is composed of several procedures, and a procedure is called between the procedures, a conventional microprocessor needs to execute the following procedure when using a register file. is there. In the following, the parent procedure refers to the calling procedure, and the child procedure refers to the called procedure.
First, when a procedure is called, it is necessary to save variables used by the parent procedure by allocating the registers to the stack area in the main memory. This is to prevent the values of these variables from being rewritten by the child procedure. Furthermore, the parent procedure must write the arguments to be passed to the child procedure in the register file or in the stack area described above. The child procedure performs processing using these arguments. At the end of the procedure call, the variables of the parent procedure saved in the stack area are restored to the registers.
As described above, when a procedure is called, a stack area in the main memory is frequently accessed. In many cases, the stack area is copied to the buffer memory, so that access to the buffer memory occurs frequently.

[0005]

A first problem of the prior art microprocessor relates to the transfer bandwidth of data transfer between the register file and the buffer memory. This will be described below.

In the conventional microprocessor, as described above, data is moved between the register file and the buffer memory in units of one word or less specified by an instruction.

On the other hand, with the development of semiconductor integrated circuit technology,
The buffer memory is integrated on a single integrated circuit chip together with a register file and the like as a part of the microprocessor. In general, when two certain circuit blocks are present on separate integrated circuit chips or when they are integrated on one integrated circuit chip, physical constraints on the transfer bandwidth of signal transfer between these circuit blocks are different. Are very different. When integrated on separate integrated circuit chips, the connection path between these circuit blocks must pass through the boundary between the integrated circuit chips. That is, since the external input / output pins of the integrated circuit chip must pass through, it is difficult to secure a wide transfer bandwidth due to a problem generally called a pin neck. Specifically, the number of external input / output pins per integrated circuit chip is one.
The number is about 500 as of 993, and it is expected that the number will gradually increase with the progress of the packaging technology in the future, but it is difficult to improve it by, for example, about one digit. Further, even if it is technically possible to increase the number of external input / output pins, it is inevitable that mounting costs and power consumption increase by increasing the number of external input / output pins. In other words, the cost of transfer bandwidth between separate integrated circuit chips is very high. On the other hand, in the case of circuit blocks integrated in the same integrated circuit chip, the connection path between the circuit blocks is closed in one integrated circuit chip,
By using the fine wiring technology of the semiconductor integrated circuit, a wide transfer bandwidth can be easily secured. In other words, the transfer bandwidth cost of signal transfer within the same integrated circuit chip is very low. More specifically,
The distance between the wirings in the integrated circuit chip is about 1-2 microns, while the distance between the external input / output pins is 100-
It is about 200 microns, and there is a two-digit difference in area per unit transfer bandwidth.

A first problem with the prior art microprocessor is that the buffer memory and the register file can be integrated on one integrated circuit chip, and the transfer bandwidth of data transfer between the two as described above. Is that the transfer bandwidth is limited to one word size due to architectural constraints, despite the fact that it is physically easy to increase the bandwidth. In other words, the conventional microprocessor technology is in an era when the integrated circuit technology is still underdeveloped, and has a problem that the development of the integrated circuit technology cannot be used effectively. Considering that the improvement in processor performance is limited by the data transfer capability of loading data from memory to the register, rather than the computational capability of the computing unit, as generally said by the term memory neck, It can be said that solving this problem is very important for improving the performance of the microprocessor.

A second problem with prior art microprocessors is that it takes a long time to execute the procedure call procedure. As can be seen from the procedure call procedure already described, in the prior art microprocessor, it is necessary to frequently access the buffer memory at the time of the procedure call, which degrades the performance of the microprocessor. In order to solve such a problem, a method called a register window, which is one of the prior arts, has been proposed. Regarding the register window, for example, “Computer Architecture:
A Quantitative Approach,
John L. Hennessy & David A. P
atterson, Morgan Kaufmann
Publishers Inc. In the register window method, the register file is made up of several register windows. Each register window is made up of the following four parts. That is, a part shared with the register window on the left side, a part unique to the register window, a part shared with the register window on the right side, and a part shared by all the register windows in the register file. Use a different register window.Since each register window has a unique part, it is not necessary to perform a variable save / restore process by holding a unique variable in this part. Write the argument in this part using the part shared by By using the register window method, it is possible to frequently access the buffer memory or main memory when executing the procedure call procedure. Can be solved.

However, even in the case of a procedure call using the register window method, there is a problem that the register window overflows or underflows. The number of register windows existing in the register file is fixed to the number implemented as hardware. If the procedure call is deeper than this number, register window overflow and underflow problems will occur. In such a case, the register window method is such that the operating system generates an interrupt, saves the contents of the register window to the main memory when an overflow occurs, and saves the saved contents to the main memory when the underflow occurs. The recovery process is performed. Such an interrupt by the operating system causes a large overhead in processing such as switching the execution environment of the microprocessor from the program being executed to the operating system, and causes a decrease in the performance of the microprocessor.

An object of the present invention is to unify the problems of the buffer memory and the register file in the conventional microprocessor as described above.

[0012]

In order to achieve the above object, a microprocessor control method according to the present invention has the following features.

A microprocessor according to the present invention includes a register file and a buffer memory, wherein the register file includes a plurality of independent register banks.
Register bank selecting means, wherein the register bank comprises a plurality of registers of the same number, respectively, wherein the buffer memory comprises a plurality of buffer lines and buffer line selecting means, and wherein the buffer line comprises the register bank. The register file and the buffer are defined by defining a frame as data having a bit width of the register bank or the buffer line, and defining a word as data having a bit width of the register. A first data transfer means for mutually transferring data in a frame unit between the buffer memory and the register file; and a main memory existing outside the microprocessor and the buffer memory. Between the frame The second data transfer means for mutually transferring data following beam unit or a word unit, and the buffer memory and the main memory.

Further, the first data transfer means in the microprocessor has a transfer bandwidth capable of transferring the frames at once.

In the microprocessor control method according to the present invention, in the microprocessor, a frame address is specified as an address for uniquely specifying the frame, and a register bank number is specified as a number for uniquely specifying the register bank. Indicating the frame address and the register bank number, loading the frame in the buffer memory specified by giving the frame address to the buffer line selecting means from the buffer memory, and setting the register bank number to Storing the loaded frame in the selected register bank by giving it to the register bank selecting means; indicating the frame address and the register bank number; and setting the register bank number to the register bank. Reading the frame from the register bank selected by applying the frame address to the register bank, and reading the frame into the frame in the buffer memory specified by applying the frame address to the register bank selecting unit. And in each of the loading and storing operations,
When the frame specified by the frame address does not exist in the buffer memory, the frame is transferred from the main memory to the buffer memory via the second data transfer unit.

[0016]

In the microprocessor of the present invention, the register file and the buffer memory are respectively constituted by a register bank and a buffer line having the same bit width.
Data stored in a register is called a word, and data stored in a register bank or a buffer line is called a frame. Since the frames have the same bit width, the frames stored in the register bank can be stored in the buffer line as they are, and vice versa. The first data transfer unit that connects the register file and the buffer memory is a transfer unit that can transfer frames all at once or has a wide transfer bandwidth equivalent thereto. The present invention solves the above-mentioned first problem of the related art by loading or storing data between the buffer memory and the register file in frame units via the first data transfer means.

Further, according to the present invention, the procedure call procedure can be speeded up by utilizing a wide transfer bandwidth between the buffer memory and the register file. That is, the parent procedure specifies a certain register bank, and stores the frame stored in this register bank from the register file to the buffer memory. As a result, the variables used by the parent procedure are saved in the buffer memory. The recovery of the saved variables is executed by loading a frame including the variables from the buffer memory to the register frame in frame units. As a result, the procedure calling procedure can be sped up as compared with the prior art in which the save / restore processing is performed one word at a time. Further, in this method, even when the depth of the procedure call is deep, there is no problem of the interruption by the operating system as in the case of using the conventional register window method. This is because saving and restoring from the buffer memory to the main memory can all be automatically executed by hardware.
That is, the frame in which the variable is stored is saved to the buffer memory via the first data transfer means, and the frame which cannot be stored in the buffer memory becomes the main data under the hardware management via the second data transfer means. Saved in memory. As described above, the buffer memory and the register frame are connected by the data transfer means having a wide bandwidth, and the saving / restoring process of the variable is performed by using the data transfer means. The procedure can be speeded up.

[0018]

FIG. 1 is a block diagram showing an embodiment of a microprocessor according to the present invention, showing parts related to the present invention. In FIG. 1, in the embodiment of the present invention, as an example, the register file 110 includes four register banks 120, and one register bank includes eight words. That is, it is assumed that the total number of registers constituting the register file 110 is 32 as an example. In FIG. 1, the register file 110 includes four register banks 120 and register bank selecting means 130 for selecting the register bank 120 using the register bank number input from the register bank number input terminal 111. 120 includes eight registers 125. Further, the buffer memory 150 stores the register bank 1
A plurality of buffer lines 160 having the same bit width as 20
And a buffer line selection means 170. In the present embodiment, an example is shown in which the buffer memory 150 employs a system generally called a direct map system. Buffer line selection means 170
Uses the frame address input from the frame address input means 151 to uniquely select a buffer line 160 to store or read a frame from,
It is determined whether or not the frame stored in the selected buffer line 160 is specified by the frame address. The first data transfer means 180 connects between the register file 110 and the buffer memory 150. The first data transfer means 180 has a transfer bandwidth sufficient to transfer frames at one time, and transfers data in the direction of phase in units of frames or words or less. Here, the word or less refers to a word, half word, byte, or the like, which is generally designated as a processing unit of a microprocessor. The buffer memory 150 and the main memory connection terminal 191 are connected by the second data transfer means 190. The main memory connection terminal 191 is connected to a main memory existing outside the microprocessor.

FIG. 2 is a block diagram showing an embodiment of the detailed configuration of the register file 110, the buffer memory 150, and the first data transfer means 180 of the embodiment shown in FIG. In the present embodiment, the register file 110 is configured using a memory array of a semiconductor integrated circuit, particularly, a static RAM. In this embodiment, one word has a 32-bit configuration. In FIG. 2, the register bank 12 in the register file 110
0 is composed of 32 register subbanks 220 0 to 220 31 corresponding to each bit forming a word. In one register sub-bank 220, there are eight memory cells 225 corresponding to the number of words constituting one register bank 120 being eight. The memory cell 225 is connected to a word line 221 and a bit line pair 222, and the word line 221 is connected to an output of the register bank selecting means 130. A register number, which is an input of the register bank selection means 130, is input from a register number input terminal 111. Each bit line pair 22 is connected to a read / write circuit 235.
The read / write circuit 235 reads / writes the register file via the bit line pair 222 in units of frames or words. Which unit is to be used for reading / writing is specified by decoding the register selection control signal input from the register selection control signal input terminal 213 by the decoder 230 and supplying the decoded signal to the read / write circuit 235. When this is performed in word units, the position of the word is similarly designated from the decoder 230 to the read / write circuit 235. Note that the bit line pairs 222 are indicated by bold lines in the figure, but this is to indicate that details have been omitted in order to avoid redundancy in the drawing.

In the buffer memory 150, the buffer line 160 has 32 buffer sub-lines 2600 to 260 as in the case of the register bank 120.
31. One buffer subline 260
Is eight in the same manner.
The word line 261 is connected to the buffer line selection means 170. The buffer line selection unit 170 selects a word line 261 corresponding to one buffer line 160 using the frame address input from the frame address input terminal 151. In addition, buffer line selecting means 1
70 determines whether the selected buffer line 160 is truly specified by the frame address, and sends the result to the read / write circuit 275 as a control signal. The read / write circuit 275 is connected to the bit line pair 262. If the selected buffer line 160 is truly specified by the frame address, the read / write circuit 275 is connected to the bit line pair 262 in frame units or word units. Read / write data. If the selected buffer line 160 is not truly specified by the frame address, the correct frame is transferred from the main memory to the buffer memory 150 and stored in the buffer line 160 selected by the buffer line selecting means 170, Thereafter, the same operation as above is performed. The second data transfer unit 190 shown in FIG. 1 is used for transferring the frame. The first data transfer means 180 is connected to the read / write circuit 2 in the register file 110 by the 256 bit transfer lines 282.
35 and a read / write circuit 275 in the buffer memory 150 are connected. One bit transfer line 282
Reads 1-bit information read by the read / write circuit 235 or 275,
75 or 235 respectively. One bit transfer line corresponds to one set of bit line pairs 222. As a result, the register file 110 and the buffer memory 1
A data transfer means having a wide bandwidth of 256 bits between 50 is realized. In FIG. 2, the bit transfer line 282
Pass through the shift circuit 280. Shift circuit 280
Works as follows for the transfer of data in units of frames or words or less. When transferring data in frame units, the signal on the bit transfer line 282 is transferred as it is. For data transfer in units of words or less,
The signal on the bit transfer line 282 is shifted and transferred in the horizontal direction so that data below the requested word is transferred to the requested position. Whether to transfer in frame units,
A shift direction and a shift width in the case of performing transfer in units of words or less are input from a shift control signal input terminal 281.

FIG. 3 is an explanatory diagram for explaining an embodiment of a microprocessor control method according to the present invention, using one embodiment of the microprocessor according to the present invention shown in FIG. FIG. 3 shows a list of instructions used in the first and second embodiments of the microprocessor control method according to the present invention and abbreviations used in the list of instructions. The load frame instruction as the first instruction is stored in the buffer memory 15.
This is an instruction for loading one frame from 0 into the register file 110. The abbreviation of this instruction is lf. The register bank number is specified as the first argument of the If instruction, and the frame address is specified by the set of the second and third arguments. The third argument specifies the register number of the register that stores the base of the frame address.
The frame address is obtained by adding the immediate value specified by the argument. In FIG. 3, the third argument is enclosed by []. The frame specified by the frame address is loaded from the buffer memory 150 and stored in the register bank 120 specified by the first argument. The second instruction, s
The store frame instruction is an instruction for storing one frame from the register file 110 in the buffer memory 150. The abbreviation of this instruction is sf. sf
The structure of the argument of the instruction is the same as that of the lf instruction. The frame stored in the register bank 120 specified by the first argument is stored in the buffer line 160 corresponding to the frame address specified by the second and third arguments. The third through sixth instructions are those that are also present in prior art microprocessors. In the present embodiment, these instructions are defined in accordance with an instruction format defined by an architecture called MIPS architecture defined by MIPS Corporation in the United States. Details of these instructions can be found in the previously cited document "Computer Architecture:
A Quantitative Approach "is described in the literature and the description is omitted.
It should be noted that the jump and link instruction writes the return instruction address to the 31st register which is not explicitly specified as an argument of the instruction at the time of execution.

In FIG. 3, a load frame instruction and a store frame instruction are instructions which characterize the microprocessor control method according to the present invention. Hereinafter, as an example, a more detailed operation of the load frame instruction will be described with reference to FIGS. load
When the frame instruction is issued, the frame address obtained from the second and third arguments is stored in the buffer memory 150.
, And one buffer line 160 is selected by the buffer line selecting means 170. Selected buffer line 160
Is stored by the buffer line selecting means 170 to determine whether or not the frame is truly stored in the frame specified by the frame address. If so, the frame is read out via the read / write circuit 275 and the first The data is transferred to the register file 110 all at once via the data transfer means 180. If the designated frame has not been stored, the frame is transferred from the main memory via the second data transfer means 190, the frame is stored in the buffer line 160, and the frame is transferred to the first data transfer section. The data is transferred to the register file 110 all at once via the means 180. On the other hand, load f
The register bank number of the first argument of the "rame" instruction is inputted from the register bank input terminal 111 of the register file 110, and the register bank 120 is selected by the register bank selecting means 130. The frame transferred from the buffer memory 150 is stored in the selected register bank 120.

In the microprocessor control method according to the present invention, in addition to these instructions, the instructions used in the conventional microprocessor are used together to control the microprocessor. The description is omitted in this embodiment because it is sufficiently disclosed.

FIG. 4 is an explanatory diagram of the first embodiment showing a microprocessor control method according to the present invention using the instructions shown in FIG. For the program code shown on the left side in FIG. 4, an instruction sequence on the right side in the figure is generated using the previously described instructions, and the program code is executed by controlling the microprocessor using this. In FIG. 4, the program code is described in the c language. This program code adds vectors x and y each having eight elements, and makes the result a vector z. Further, in the instruction sequence shown in FIG.
Mean the register bank number 2, the register bank number 3, etc., respectively. Also, R8, R24, etc. mean register number 8, register number 24, etc., respectively. In addition,
Hereinafter, the register bank designated by the register bank number 2 is referred to as register bank 2, and the register designated by the register number 8 is referred to as register 8. Further, R4 is the address of x [0], R5 is the address of y [0], R6
Is assumed to hold the address of z [0], and the vectors x, y, and z are respectively aligned at the frame boundaries. In this instruction sequence, first, the vector x and the vector y are loaded into the register bank 3 and the register bank 2 by the load frame instruction, respectively. Next, addition is performed by an add instruction for each word of the frame stored in the register bank 3 and the register bank 2, and the result is written in each register in the register bank 1. Here, the correspondence between the register number and the register bank number is as follows. Register 0 to register 7 are in register bank 0, register 8 to register 15 are in register bank 1, register 16 to register 23 are in register bank 2, and register 24 is register 24. Therefore, the register 31 is included in the register bank 3. Finally, the frame stored in the register bank 1 is stored in the vector z using the store frame instruction.
As described above, according to the microprocessor control method of the present invention, the number of accesses to the buffer memory is reduced as compared with the case of using words as a unit by loading or storing data collectively in units of frames. You can do it. In the embodiment of FIG. 4, the buffer memory access is required a total of 24 times in the conventional microprocessor control method, whereas the control method of the present invention requires a total of three times. FIG. 5 is an explanatory diagram of a second embodiment showing a microprocessor control method according to the present invention using the instructions shown in FIG. This embodiment shows a procedure calling procedure by the microprocessor control method according to the present invention. The program code in the c language shown on the left side in FIG. 5 calls a procedure called foo from a procedure called main. The argument of foo is two integers, and main gives the values of the external integer variables x and y as this argument. The corresponding instruction sequence is shown on the right side of the figure. In this instruction sequence, it is assumed that the addresses of the variables x and y are stored in the registers 16 and 17. It is also assumed that the frame stored in register bank 1 is being used to store variables used by main. In this instruction sequence, first, x and y are loaded into the registers in the register bank 2 by a load word instruction. next,
In order to save the variables used by main, the frame stored in register bank 1 is stored in the frame specified by the frame address stored in R29.
Store using the frame instruction. Furthermore, the argument is f
In order to transfer the frame to oo, the frame of the register bank 2 in which x and y are stored is stored in the frame specified by the frame address stored in R30 by using the storeframe instruction, and foo is called by the jump and link instruction. foo calls a frame from a frame address specified by R30 by a load frame instruction, stores the frame in the register bank 2 , and receives a variable from main. foo is finally jump regis
ter instruction returns to main, and main loads the frame saved in the buffer memory to register bank 2.
Recover using the frame instruction. In this case, if the transfer of the argument can be performed only by the register, the foo can be used directly without storing the frame stored in the register bank 1 in the buffer memory as in the present embodiment.

As described above, in the microprocessor control method of the present invention, the procedure call procedure is executed by loading or storing data collectively in units of frames, as compared with the case of using units of words. In this case, the number of accesses to the buffer memory can be reduced.

In the embodiment described above, FIG.
In the embodiment of the configuration of the microprocessor according to the present invention, the description of the connection between the register file 110 and the arithmetic unit in the microprocessor is omitted, but this is because the connection method is sufficiently disclosed by the prior art. It is. For example, in the configuration example of the register file 110 shown in FIG. 2, the memory constituting the register file 110 is a multi-port memory, and each port is used to store a read port for supplying data to an arithmetic unit and an arithmetic result. Write port. Also,
Although the configuration of the buffer memory 150 was not described in detail except for parts related to the present invention, this is because it is sufficiently disclosed by the prior art. Further, in the embodiment of FIG. 1, the configuration of the buffer memory 150 includes a direct map, the number of words in the register file 110 is 32 words, and the number of register banks 120 is 4 register banks. This is an example, and the microprocessor according to the present invention can be realized by various other configurations.

[0027]

As described above, according to the microprocessor and the control method thereof according to the present invention, the buffer memory and the register file constituting the microprocessor are connected by the data transfer means having a wide transfer band, and the register bank or the register bank is connected. By loading and storing data in units of frames each having a buffer line size and consisting of a set of a plurality of words, the number of accesses to the buffer memory can be reduced and the performance of the microprocessor can be improved. . In particular, during execution of the procedure call procedure, the number of times of buffer memory access can be reduced by saving / recovering variables and passing arguments in units of frames, thereby reducing the number of accesses to the register. There is an effect that there is no problem of the overhead due to the overflow of the window as in the case of the window system.

The structure of the first data transfer means shown in FIG. 2 as one embodiment of the microprocessor according to the present invention is as follows.
This shows how a wide bandwidth can be easily secured when the register file and the buffer memory are integrated on the same integrated circuit chip. In FIG. 2, the bit transfer lines 282 constituting the first transfer means 180 are arranged at a ratio of one bit line pair 222 or 262 per bit line pair.
As described above, the first data transfer unit 180 can be provided simply by arranging the register file 110 and the buffer memory 150 side by side and connecting each other with finely spaced parallel wiring.
Has been realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a part related to the present invention in one embodiment of a microprocessor according to the present invention.

FIG. 2 shows the microprocessor of the embodiment shown in FIG.
FIG. 4 is a block diagram showing a more detailed configuration of a register file, a buffer memory, and connection means between them.

FIG. 3 is an explanatory diagram for explaining a microprocessor control method according to the present invention.

FIG. 4 is an explanatory diagram showing a first embodiment of a microprocessor control method according to the present invention.

FIG. 5 is an explanatory diagram showing a second embodiment of the microprocessor control method according to the present invention.

[Explanation of symbols]

 Reference Signs List 110 register file 120 register bank 130 register bank selecting means 150 buffer memory 160 buffer line 170 buffer line selecting means 180 first data transfer means 190 second data transfer means 111 register bank number input terminal 151 frame address input terminal 191 main memory Connecting terminal

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G06F 12/08 G06F 9/30-9/355 G06F 9/40-9/42

Claims (2)

(57) [Claims] 1. A register file comprising a register file and a buffer memory, wherein the register file comprises a plurality of independent register banks and register bank selecting means, and the register bank comprises a plurality of registers of the same number. Wherein the buffer memory comprises a plurality of buffer lines and buffer line selecting means,
The buffer line is configured to have the same bit width as the register bank, a frame is defined as data having the bit width of the register bank or the buffer line, and a word is defined as data having the register bit width. A first data transfer unit having a transfer bandwidth capable of transferring the frames at one time and transferring data between the register file and the buffer memory in units of the frames;
Said buffer memory and said Rejisutafu § yl and are connected, the frame between the main memory existing outside of the buffer memory and the microprocessor,
Alternatively, a microprocessor in which the buffer memory and the main memory are connected by second data transfer means for mutually transferring data in word units or less.
A control method, wherein a frame address is defined as an address uniquely specifying the frame, a register bank number is defined as a number uniquely specifying the register bank, and the frame address and the register bank number are defined as The frame in the buffer memory designated by giving the instruction and giving the frame address to the buffer line selecting means is loaded from the buffer memory, and the frame is selected by giving the register bank number to the register bank selecting means. Storing the loaded frame in the register bank, indicating the frame address and the register bank number, and providing the register bank number to the register bank selecting means from the selected register bank. The frame Read the beam, and to store the frame in which the read buffer line <br/> in the designated said buffer memory by providing the frame address to the buffer line selecting means, wherein
In the loading operation, when the frame specified by the frame address does not exist in the buffer memory, transferring the frame from the main memory to the buffer memory via the second data transfer unit. Characteristic microprocessor control method. 2. The microprocessor control method according to claim 1, further comprising, when calling a procedure calling a child procedure from a parent procedure, saving variables used by said parent procedure to said buffer memory; The restoration process to the register file is performed by storing and loading the frame between the buffer memory and the register file via the first data transfer means, and from the parent procedure via the buffer memory to the child The passing of the argument to the procedure is performed by the parent procedure storing the frame in which the argument is written in the buffer memory, and loading the frame in which the argument is written into the register file by the child procedure. A method for controlling a microprocessor, comprising: