JP2992178B2 - Image processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus,
In particular, the present invention relates to an image processing device such as an object sensor for automatically specifying an object, a door phone camera, a videophone, a video conference device, a monitoring device, and a user interface device.

[0002]

2. Description of the Related Art Conventionally, devices for detecting a person include an infrared sensor for detecting infrared rays emitted from a human body, an ultrasonic wave,
There are sensors using an active sensor using radio waves or light. These devices are devices that indirectly sense a person by assuming predetermined constraints. For example, in the case of using infrared light, the property that the wavelength of radiation moves to the shorter wavelength side because the temperature of the human body is higher than the surrounding temperature is used, and detection is performed by monitoring at the infrared wavelength corresponding to that temperature. is there. Devices that use ultrasonic waves, radio waves and light use the reflection efficiency of the human body,
Some use the blocking properties of the human body. Meanwhile, CCD
As for an image processing apparatus using an area sensor such as (Charge Coupled Device), Yamamoto et al. (IEEE HPM 14, 5 1991) proposes an image processing apparatus described below. This image processing apparatus stores an old frame image, calculates a difference between the old frame image and a newly input new frame image, sets an area having a large difference value as a human area,
The face area is extracted from the width of the area. FIG.
FIG. 2 is a block diagram showing a configuration of the conventional image processing apparatus.

In FIG. 42, an image processing apparatus includes an A / D
A conversion unit 101, an image memory 102, an absolute difference unit 103,
Comparator 104, crown detector 105, width detector 1
06, a comparator 107, and a face coordinate output unit 108.

An A / D converter 101 is supplied with a line-sequentially scanned analog image signal, converts the analog image signal into a digital signal, and stores the analog image signal in an image memory 102 and an absolute difference device 10.
Output to 3. The image memory 102 includes the A / D converter 10
The digital image signal output from 1 is delayed by k frames and output to the absolute differentiator 103. Absolute difference device 10
3 calculates the difference between the image delayed by k frames and the current input image. When there is a moving object in the image, a luminance difference occurs between the two pieces of image data at a certain position of the moving object. Therefore, the position of the moving object is determined by binarizing the image data by the comparator 104. FIG. 3 shows a process of generating the binarized image data of the absolute difference. As shown in FIG. 3, in the detected moving object, a portion having a strong edge is emphasized. The width w of the detected moving object depends on the speed v on the screen of the moving object and the time t between two frame image data. expressed.

W = vt (33) Based on the above equation, a predetermined threshold value wn is appropriately set,
It is possible to determine whether or not there is a moving object. That is, the width detector 106 detects the width w of the moving object and its X-axis (horizontal axis) coordinates, and the comparator 107 determines the threshold wn.
If it is larger, it is determined that a moving object has been detected and "1" is output. The output of the comparator 104 is input to the parietal detector 105, and the parietal detector 105 outputs the first Y coordinate initially determined as a moving area in the Y-axis (vertical axis) scanning direction as the parietal coordinate. The face coordinate detection unit 108
The coordinate data output by the crown detector 105 and the width detector 106 are output as valid only when the output of the comparator 107 is “1”. With the above processing, the conventional image processing apparatus can output the face coordinates of the moving object in accordance with the movement of the moving object.

[0006]

With the above-mentioned apparatus utilizing infrared rays or the like, humans, dogs and cats cannot be distinguished.
Further, even if it is determined that a person is a person, it is not possible to determine the position of the face of the person. Therefore, there is a problem that an arbitrary target object cannot be specified.

Further, in the image processing apparatus using the above-mentioned area sensor, animals, vehicles, plants, people, and the like cannot be distinguished, and an arbitrary object cannot be specified. In addition, when the movement of the target object is slow, since the movement of the target object is detected based on the difference from the image data delayed by a certain amount, a sufficient motion detection signal cannot be obtained, and many detection omission operations are performed. There has been a problem that the detection of the top of the head has many malfunctions, and an arbitrary target object cannot be specified.

An object of the present invention is to solve the above-mentioned problem, and an object of the present invention is to provide an image processing apparatus capable of obtaining good image data for specifying an arbitrary target object.

[0009]

An image processing apparatus according to claim 1, wherein :
The apparatus is configured to execute a predetermined process based on the input image data and the input image data.
Difference image data from the reference image data input before
Data, binarize the difference image data, and
And a binarization means for outputting a signal,
Length detection means for detecting the perimeter of a region
Vertical length to detect the vertical length of the area extracted from the signal
Detection means and the area of the region extracted from the motion detection signal
Area detection means to detect, perimeter, vertical length and
Based on the area, in the area extracted from the motion detection signal
A motion determining means for determining whether the amount of motion of an object is equal to or greater than a predetermined value;
And an image processing device.

[0010] The invention according to claim 2 provides the invention according to claim 1.
In addition to the configuration of the invention, the binarizing means includes an output of the motion determining means.
Between the input image data and the reference image data based on the force
Control the frame interval.

[0011] The invention according to claim 3 is the invention according to claim 1 or 2.
In addition to the configuration of the invention described in the above, the binarizing means includes an input image
Based on the luminance value of each pixel in the data,
Threshold value, and based on the threshold value, the difference image
Binarize the data.

An image processing apparatus according to a fourth aspect of the present invention is the first aspect of the invention.
In addition to the constitution of the invention described in any one of the above-mentioned items,
The row shows a difference image between the input image data and the reference image data.
Create data, binarize differential image data, and detect motion
Differential image data binarization means for outputting a signal, and motion detection
Binary image dilation means for dilating the signal.

According to a fifth aspect of the present invention, there is provided a method as set forth in the fourth aspect.
In addition to the configuration of the invention, the binary image dilation means includes a motion detection signal.
By performing a predetermined operation on each pixel of the signal, the motion detection signal
The luminance value of each pixel of the signal is propagated to the adjacent pixels,
Dilation means for generating dilated image data, and dilated image data
And a dilated image binarization means for binarizing the image with a predetermined threshold value.
Including.

[0014] The invention according to claim 6 is the invention according to claim 4.
In addition to the configuration of the invention, the binary image dilation means includes a motion detection signal.
The rising timing of the luminance value is detected for each row of the signal.
The rising edge detection means and the brightness of each line of the motion detection signal.
Fall detection means for detecting the fall timing of the degree value
And the time between the rising timing and the falling timing
Time difference measurement means to measure the difference, and adapted to the time difference,
Dilation for expanding the motion detection signal and creating dilated image data
Expansion means and binarize the dilated image data at a predetermined threshold value.
Expansion image binarization means.

The invention according to claim 7 is the invention according to claims 1 to 6.
In addition to the configuration of the invention described in any of the above, the motion detection signal
The timing when the first information in the direct direction is detected is defined as the starting point.
Counting means for performing a counting operation, and
For detecting the first start position and the first end position in the direction
Position detecting means and the low frequency component of the signal at the first start position.
Extract and circulate its output to obtain the signal of the second start position
First converting means for converting the signal at the first end position to a low level.
The frequency component is extracted, its output is circulated, and the second end position
Second conversion means for converting the signal into a second signal, and a second start position
Value calculating means for calculating a difference value between the first and second end positions
And the difference value and the count value of the counting means.
Control means for controlling the operation of the first and second conversion means based on the
And further included.

The invention according to claim 8 is the invention according to claim 7.
In addition to the configuration of the invention, edges are extracted from input image data
Edge extracting means, and a vertical line component of the motion detection signal and the edge.
Logical processing means for calculating a logical product of minutes and logical processing means
Of the input image data projected in the horizontal direction
Conversion means for converting to a signal, and the signal converted by the conversion means
And a detecting means for detecting the peak position.

According to the ninth aspect of the present invention, there is provided an image forming apparatus according to the eighth aspect.
In addition to the configuration of the present invention, the edge extracting means may further include input image data.
First differentiating means for differentiating the luminance value of the pixel in the horizontal axis direction;
Second differentiation for differentiating the luminance value of the force image data in the vertical axis direction
Means and a difference value between outputs of the first and second differentiating means.
The absolute value of the difference value based on the sign of the difference value.
A means to determine the vertical or horizontal line component of the
Edge binary to binarize line and horizontal line components respectively
Means.

The invention according to claim 10 is the invention according to claim 9.
In addition to the configuration of the invention, the edge binarizing means further includes a vertical
Line components and horizontal line components are determined by the luminance value of the input image data.
And normalization means for normalizing. The invention according to claim 11
Is added to the configuration of the invention according to any one of claims 8 to 10.
Based on the vertical and horizontal line components of the edge.
Extraction method for extracting feature information of target object in force image data
Non-linear with a predetermined analysis function for steps and feature information
Feature information conversion means for performing conversion and converting to intermediate feature information
After applying a certain weight to the intermediate feature information,
Evaluation data creation that creates evaluation data by adding
Object and target object in image data based on evaluation data
And a specifying means for specifying

[0019]

In the image processing apparatus according to the first aspect, the object
Based on the perimeter, vertical length, and area of the area,
It is determined whether the movement of the object is sufficient or not.
Whether it moves more than the specified value, whether it moves slowly or fast
Can be determined stably.

The invention according to claim 2 is the invention according to claim 1.
In addition to the action and effect of light, based on the output of the motion judgment means
Control the frame interval when creating difference image data
It is. Therefore, regardless of the amount of movement of the target object,
Motion information of the target object can be obtained.

The third aspect of the present invention is the first or second aspect.
In addition to the functions and effects of the invention described in
Binarization threshold is calculated based on the brightness value of force image data
Can be Therefore, it is not affected by the fluctuation of the brightness value,
And stable motion information
You.

The invention according to claim 4 is the invention according to claims 1 to 3.
In addition to the actions and effects of the invention described in
The number is subjected to an expansion process. Therefore, the lack of motion detection signal
Can fill in the gaps and obtain stable motion information
it can.

The invention according to claim 5 provides the invention according to claim 4.
In addition to the actions and effects of the invention, the motion detection signal
The signal is blurred and expanded, and expanded by the expanded image binarization means.
Small binary image data can be obtained.
Binary image data expanded over a large area on a road scale
Can be obtained.

The invention according to claim 6 is the invention according to claim 4.
In addition to the functions and effects of the invention, the rising edge of the binary image signal
In response to the time difference between the
Since the value image signal is expanded, the expansion adapted to the time difference
Can be obtained.

[0025] The invention according to claim 7 provides the invention according to claims 1 to 6
In addition to the functions and effects of the invention described in
The signal of the first start position and the signal of the first end position
A stable second starting position by the first and second conversion means
Into a signal at the second end position and a signal at the second end position.
The difference between these signals and the count of the counting means.
Comparing the operation of the first and second determination means based on the comparison result.
Control to obtain stable coordinates of both ends of the target object
Can be.

[0027] The invention according to claim 8 is the invention according to claim 7.
In addition to the functions and effects of the invention, a binarized motion detection signal
AND of the vertical line component of the edge with the horizontal axis of the image
By detecting the peak position of the projected signal,
Obtain the coordinates of both ends of the target object in the image in the horizontal axis direction.
To obtain accurate coordinates of both ends of the target object in the horizontal axis direction
Can be.

[0027] The invention according to claim 9 is the invention according to claim 8.
In addition to the action and effect of Ming, the first and second differentiating means
More isolated noise components, and the absolute value of the difference value
The vertical line component and the horizontal line component of the edge are determined based on the edge. This
By removing isolated noise components,
Edge signal, and less affected by noise
An edge signal can be obtained.

The invention according to claim 10 is the invention according to claim 9.
In addition to the functions and effects of the invention, the edge component is represented by a luminance value.
Normalization eliminates the effect of fluctuations in luminance values
Edge signal can be output, making it powerful for shooting
Edge signals can be obtained. Claim 11
Akira is the operation of the invention according to any one of claims 8 to 10,
In addition to the effect, the nonlinear conversion means performs a predetermined nonlinear conversion.
The processing is simplified by using the analysis function
Since the shape addition means requires a small amount of calculation, the image
Can be specified.

[0029]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an image processing apparatus according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram illustrating a configuration of an image processing apparatus according to an embodiment of the present invention.

In FIG. 1, the image processing apparatus includes an A / D converter 1, a timing generator 2, a motion detector 3, an edge detector 4, a first area limiter 5, a second area limiter 6, and a third area limiter. An area limiting circuit 7, a fourth area limiting circuit 8, a maximum moving object detecting circuit 9, a parietal coordinate detecting circuit 10, a moving feature amount extracting circuit 11, a precise cheek coordinate detecting circuit 12, a feature extracting circuit 13,
Switching circuits 14 to 16, evaluation determination circuit 17, motion determination circuit 18, tracking target coordinate output circuit 19, mode setting circuit 2
0, an enlargement display circuit 21, a D / A conversion circuit 22, and a display 23.

The A / D converter 1 includes a fixed camera and T
A line-sequential-scanning analog image signal output from a V-video device or the like is supplied, and the line-sequential-scanning analog image signal is converted into a digital signal and supplied to the motion detection unit 3, the edge detection unit 4, and the enlarged display circuit 21 I do.

The motion detecting section 3 generates a motion detecting signal based on the digital image signal output from the A / D converting section 1 by a predetermined process described later, and generates a first area limiting circuit 5 and a second
It outputs to the area limiting circuit 6, the third area limiting circuit 7, the fourth area limiting circuit 8, and the maximum moving object detecting circuit 9.

Hereinafter, the motion detecting section 3 will be described in more detail with reference to the drawings. FIG. 2 is a diagram illustrating a configuration of the motion detection unit 3. In FIG. 2, the motion detection unit 3
It includes a smoothing circuit 301, a frame memory 302, an absolute difference unit 303, a comparator 304, a horizontal expansion circuit 305, a vertical expansion circuit 306, a constant magnification circuit 307, and a frame memory control unit 308.

The digital image signal input from the A / D converter 1 has its noise component suppressed by a smoothing circuit 301.
The output is a frame memory 302, an absolute difference device 303,
Then, the signal is output to the comparator 304 via the constant multiplier 307.

A write mode control signal output from the mode setting circuit 20 is input to the frame memory control unit 308, and controls the operation of the frame memory 302 in response to the write mode control signal. In the first frame n, it is assumed that the mode of the mode setting circuit 20 is “0”. When the mode is “0”, the write mode control signal of the mode setting circuit 20 becomes “H”, and the image data of the n-th frame is stored in the frame memory 302 in the motion detector 3. In the next frame, the mode of the mode setting circuit 20 becomes “1”, the write mode control signal becomes “L”, and the frame memory 30 in the motion detecting section 3
2 is a read-only operation. Frame memory 302
Is input to one input terminal of the absolute differentiator 303, and the other input terminal receives the image data of the (n + 1) th frame from the smoothing circuit 301 in the order of scanning of the image. . Absolute difference unit 303
Generates difference image data that is motion information based on the input data, and outputs the difference image data to the comparator 304.

The comparator 304 has the difference image data of the absolute difference unit 303 and a predetermined magnification α by the constant magnification circuit 307.
A luminance signal of the current frame image multiplied by (0 ≦ α <1.0) is input. The comparator 304 converts the binary data into motion information obtained by further binarizing the motion information normalized by the luminance value based on the input data, into a horizontal expansion circuit 305.
Output to FIG. 3 shows a process of creating the binarized image data of the absolute difference created by the above processing. By the above processing, a binarized image reflecting the motion as shown in FIG. 3 is obtained.

[0037] As described above, temporarily stores the digital video signal input by the frame memory 302, the absolute difference unit 303, the newly inputted digital video signal and n previous field of the video signal output from the frame memory 302 , And output as a motion detection signal binarized by the comparator 304. The luminance signal of the digital video signal is added to the comparator 304. As a result, motion information normalized by the luminance signal is obtained. The scale can be reduced.

The above-described motion detection method is not applied only to the present embodiment, but is applied to an image processing apparatus using motion information such as a TV phone, a door phone camera, a video integrated type, a monitoring device, and a specific object detection device. It is possible to apply.

Next, the smoothing circuit 301 will be described in more detail with reference to the drawings. FIG. 4 is a diagram showing a configuration of the smoothing circuit 301.

Referring to FIG. 4, the smoothing circuit 301 has 1H
It includes delay lines 401 and 402, flip-flop circuits 403 to 408, and an adder 409.

The smoothing circuit 301 shown in FIG. 4 is a 3 × 3 two-dimensional smoothing filter. The input digital image signal is supplied to the flip-flop circuit 403, and a signal delayed by one clock is output from the flip-flop circuit 403. The output of the flip-flop circuit 403 is further delayed by one clock in the flip-flop circuit 404 in the subsequent stage. On the other hand, the digital image signal is also supplied to the 1H delay line 401, and an image signal delayed by 1H is output from the 1H delay line 401. By the same operation, the 1H delay lines 401, 402,
By the flip-flop circuits 403 to 408, a 3 × 3 image matrix is obtained. Assuming that these nine pieces of image luminance data are A (0 , 0) to A (−2 , −2), y1 = ΣΣa (─i, -j) / 8 (1) I = 0-2, j = 0-2, where i = 1 and j
= 1 is excluded. The average luminance value is obtained as
9 is output.

The smoothing circuit 301 is limited to the above configuration.
Instead of a 2x2 or nxn image matrix
Or a weighting factor w (−i,−
A weighting filter using j) may be used.

[0043] y1 = ΣΣw (-i, -j) × a (-i, -j) ... (2) where, i = 0 to n, j = a 0 to n the above process, the smoothing circuit 301 , And outputs a smoothed average luminance value.

Next, the frame memory 302 and the absolute difference unit 303 will be described in more detail.

As described above, the writing and reading of the image in the frame memory 302 is controlled by the frame memory control unit 308. When the luminance signal output from the smoothing circuit 301 is input, in the first frame, the frame memory control unit 308 sets the frame memory 302 to the write mode and stores the frame image data. Next, when the luminance signal of the second frame is input, the frame memory control unit 308 puts the frame memory 302 into the reading mode, reads the first frame image, and connects the absolute differentiator connected to the next stage. At 303, the difference is calculated as:

[0046] ^{dy = | y n -y m |} ... (3) where, y ⁿ is the current frame image data, y ^m represents the image data before being stored in the frame memory 302.

[0047] For example, the camera is stationary, when the object moves in the image being captured is not present, y ⁿ =
y ^m and dy = 0. Conversely, when an animal, such as a human is present in the image being photographed, where the present, is y ⁿ ≠ y ^m, the dy> 0. This difference value dy is input to one input terminal of the comparator 304 in the next stage.

On the other hand, the luminance signal smoothed by the smoothing circuit 301 is multiplied by α by the constant-magnification circuit 307 and input to the other input terminal of the comparator 304. If the difference value dy is larger than the smoothed and multiplied by α, the output of the comparator 304 is output in a state of “1”, indicating that a moving object is present. On the other hand, in other cases, “0” is output,
Indicates that there is no moving object in the image being shot. The above output of the comparator 304 is further enlarged by a horizontal expansion circuit 305 and a vertical expansion circuit 306 at the subsequent stage so that the detected motion area is enlarged and output as a motion detection result.

Next, the horizontal expansion circuit 305 will be described in more detail with reference to the drawings. FIG. 5 is a block diagram showing the configuration of the horizontal expansion circuit 305 .

In FIG. 5, the horizontal expansion circuit 305
Are flip-flop circuits 501 and 502, OR circuit 5
03 is included. The binary data output from the comparator 304 is input to the flip-flop circuit 501 and the OR circuit 503. The flip-flop circuit 501 delays the input binary data by one clock and outputs the delayed data to the OR circuit 503. The flip-flop circuit 502 further delays the signal delayed by the flip-flop circuit 501 by one clock, and outputs the delayed signal to the OR circuit 503. The OR circuit 503
The logical sum of the input signals is output as an output signal, and a motion detection signal MOV2, which is expanded image data in the horizontal direction, is output.

Next, the vertical expansion circuit 306 will be described in more detail with reference to the drawings. FIG. 6 is a block diagram showing the configuration of the vertical expansion circuit 306.

In FIG. 6, a vertical expansion circuit 306 is provided.
Are multipliers 601, 605, adder 602, comparator 60
3, including a divider 604 and a 1H delay line 606.

In FIG. 6, if the input signal to the multiplier 601 is a (i, j), the output signal O of the adder 602
(I, j) is represented by the following equation.

O (i, j) = {8 × a (i, j) + 7 × O (i, j−1)} / 8 (4) The above processing is performed as a recursive low-pass filter in the vertical direction of the image. And the output signal O (i, j) is
3, and is compared with a predetermined threshold value and output as dilated binary image data.

FIG. 7 shows the vertical expansion circuit 30 shown in FIG.
6 shows the signal waveform of FIG. The horizontal axis in FIG. 7 indicates the time axis taken in the vertical direction of the image. As shown in FIG. 7 , the input signal input to the multiplier 601 is blurred by the above-described recursive low-pass filter and output by the adder 602. The output signal of the adder 602 is compared with a predetermined threshold value and output from the comparator 603 as binary data. With the above processing, the vertical expansion circuit 306 functions to fill in the defect of the motion detection signal.

As described above, in the vertical dilation circuit shown in FIG. 6, the input binary image data is blurred by the two-dimensional recursive low-pass filter and output as expanded binary image data by the binarizing means. Therefore, it is possible to realize a binary expansion circuit over a large area with a small circuit scale.

Next, a second embodiment of the vertical expansion circuit will be described with reference to the drawings. FIG. 8 is a block diagram showing the configuration of the vertical expansion circuit according to the second embodiment.

In FIG. 8, the vertical expansion circuit is adjustable.
Sankai path 701,1H delay line 702, the comparator 70
3 inclusive.

The vertical expansion circuit shown in FIG. 8 has the same effect as the vertical expansion circuit shown in FIG.
1H by the H delay line 702 and the addition / subtraction circuit 701
An operation equivalent to the number of up-down counters equal to the number of pixels per minute is performed.

FIG. 9 is a circuit diagram showing the configuration of the addition / subtraction circuit 701. In FIG. 9, an addition / subtraction circuit 701 includes a NOR
Gates 801-803, AND gates 804-806,
813, OR gates 807 to 810, NAND gate 8
11, 812. The addition / subtraction circuit 701 has a 4-bit configuration as shown in FIG. 9. When the INC / DEC signal is “1”, the addition / subtraction circuit 701 adds 1 when the INC / DEC signal is “0”, and subtracts 1 when the INC / DEC signal is “0”. S0 to S3 are output. The NAND gates 811 and 812 limit the up / down operation, and stop at “0” during the down operation and do not count up to “10” or more during the up operation. . Addition / subtraction circuit 701
Performs the operation described above, and compares the output signal with the comparator 70.
Enter 3 The comparator 703 compares the predetermined threshold value with the output signal of the addition / subtraction circuit 701, and outputs the comparison result as dilated binary image data.

FIG. 10 shows signal waveforms of the vertical expansion circuit shown in FIG. The horizontal axis in FIG. 10 indicates the time axis taken in the vertical direction of the image. As shown in FIG. 10, the waveform of the input signal input to the addition / subtraction circuit 701 is converted by the above-described processing and is compared with a predetermined threshold value.
03 is output as binary data. By the above processing, the vertical expansion circuit functions to fill in the defect of the motion detection signal. As with the vertical expansion circuit shown in FIG. 6, the vertical expansion circuit shown in FIG. 8 can realize a binary expansion circuit over a large area with a small circuit scale.

The above two vertical expansion circuits are not applied only to the present embodiment, but expand the binary image data of a TV phone, a door phone camera, a video integrated movie, a monitoring device, a specific object detection device and the like. The present invention can be similarly applied to an image processing apparatus using expanded dilated image data.

Next, the operation when the movement of the moving object in the photographed image is slow will be described. When the motion of the moving object in the captured image is slow, if the content of the frame memory 302 is updated for each frame, the difference value dy is very small, so that a motion detection signal may not be obtained. In such a case, if the frame memory 302 is updated every k frames, a sufficient motion detection signal can be obtained. In the present embodiment, a frame memory control unit 308 is provided so that the frame memory 302 can be updated according to the speed of movement of the target moving object. That is, the motion detecting section 3, the maximum moving object detecting circuit 9, the first area limiting circuit 5, the parietal coordinate detecting circuit 10, the second area limiting circuit 6, the motion feature extracting circuit 11, the switching circuits 14, 15, the motion determining circuit At 18, it is determined whether or not the target object has sufficiently moved from the motion detection signal of the motion detecting section 3. If the result of the motion determination is sufficient, the mode of the mode setting circuit 20 is changed from "1" to "2". Update to In the mode “2”, the write mode control signal is “L”, the frame memory 302 is in the read mode while holding the image data of the n-th frame, and the absolute differentiator 303 is in the read mode between the next (n + 2) -th frame. Is detected as a motion detection signal, and is output from the motion detection unit 3 . With the above processing, a sufficient motion detection signal can be obtained even when the motion of the moving object in the captured image is slow.

Next, the edge detecting section 4 will be described in detail. FIG. 11 is a block diagram illustrating a configuration of the edge detection unit 4.

In FIG. 11, the edge detection unit 4 is 1H
Delay lines 901, 902, pixel delay unit 903, X
Differentiator 904, Y differentiator 905, FIX differentiator 906,
907, comparators 908 and 909, and a divider 910.
The pixel delay unit 903 includes flip-flops 911 to
916.

The digital image signal output from the A / D converter 1 is transmitted through 1H delay lines 901 and 902.
An image signal having a delay of one line and a delay of two lines is generated. The current image data, the one-line delay data, and the two-line delay data are represented by a (0, 0) and a, respectively.
If (0, -1) and a (0, -2), the generated a
(0, 0), a (0, -1), and a (0, -2) are input to a pixel delay unit 903 that generates a delay in pixel units.
(0,0), a (-1,0), a (-2,0), a
(0, -1), a (-1, -1), a (-2, -1),
a (0, -2), a (-1, -2), a (-2, -2)
Are output. Of the nine delayed signals,
The central luminance data a (−1, −1) is input to a divider 910, is divided by a division coefficient B, and is output to a comparator 90 at the subsequent stage.
8, 909. In this case, when the division coefficient B is a power of two, a simple bit shift is sufficient, and the configuration of the divider 910 is simplified.

On the other hand, the nine delay signals are input to an X differentiator 904 and a Y differentiator 905, and the X differentiator 904 and the Y differentiator 905 perform the following calculation. Assuming that the output of the X differentiator 904 is DX and the output of the Y differentiator 905 is DY, the output is expressed by the following equation.

DX = | a (0,0) + 2 × a (0, −1) + a (0, −2) −a (−2,0) −2 × a (−2, −1) −a ( DY = | a (0,0) + 2 × a (−1,0) + a (−2,0) −a (0, −2) −2 × a (− 1,6) -a (-2, -2) | (6) where DX means the vertical line component of the image,
The meaning of Y can be regarded as a horizontal line component of the image.

Next, an X differentiator 90 for executing the above calculation
4. The Y differentiator 905 will be described.

FIG. 12 is a block diagram showing the configuration of the X differentiator 904. In FIG. 12, X differentiator 904 is
It includes adders 920 and 921 and an absolute difference unit 922. Input signal a (0,0), 2 × a (0, −1), a (0, −
2) is input to the adder 920, added, and output to the absolute differentiator 922. Delayed signal a (-2,0), 2
× a (−2, −1) and a (−2, −2) are adders 921
The signal is added to the input signal, and is output to the absolute differentiator 922 after the addition. The absolute differentiator 922 includes an adder 920 and an adder 9
The absolute difference output from 21 is obtained, and an output signal DX is output. With the above operation, it is possible to output the output signal DX based on the above calculation formula.

FIG. 13 is a block diagram showing the configuration of the Y differentiator 905. In FIG. 13, the Y differentiator 905 is
It includes adders 923 and 924 and an absolute difference unit 925. The configuration of Y differentiator 905 is the same as the configuration of X differentiator 904 shown in FIG.

With the above X differentiator 904 and Y differentiator 905, it is possible to execute the above formula and obtain output signals DX and DY.

Next, the operation of the FIX differentiators 906 and 907 will be described. The FIX differentiators 906 and 907 perform the following calculations. The output of the FIX differentiator 906 is
Assuming that the output UY of the X, FIX differencer 907 is calculated by the following equation.

UX = DX−DY (DX> DY) (7) UX = 0 (DX ≦ DY) (8) UY = DY−DX (DY> DX) (9) UY = 0 (DY ≦ DX) (10) FIGS. 14 and 15 show the configurations of the FIX differentiator 906 and the FIX differentiator 907 for performing the above calculations. As shown in FIG. 14, the FIX differentiator 906 includes a differentiator 926, AN
D gate 927 is included. Similarly, in FIG.
The X differentiator 907 includes a differentiator 928 and an AND gate 929.
including. The output signal DX of the X differentiator 904 and the output signal DY of the Y differentiator 905 are input to the differentiator 926.
After the difference processing is performed, it is output to the AND gate 927. AND gate 927 outputs a logical product of the input signals as output signal UX. The same applies to the FIX differentiator 907. According to the above operation, the FIX differentiators 906 and 907 can output the output signals UX and UY based on the above calculation formula. As a result, it is possible to obtain an output signal UX of a vertical line component and an output signal UY of a horizontal line component in which isolated noises are canceled each other and edge components are emphasized.

The output signals UX, UY of the FIX differentiators 906, 907 are connected to one input terminals of the comparators 908, 909, respectively.
Is input to the other terminal, and a signal obtained by dividing a luminance value a (-1, -1), which is an output signal of the divider 910, by a predetermined value B is input. As a result, the output signal EDGEX of the comparator 908 is expressed by the following equation.

EDGEX = 1 (UX> a (−1, −1) / B) (11) EDGEX = 0 (UX ≦ a (−1, −1) / B) (12) According to the above calculation, It is possible to output a signal obtained by normalizing a signal in which an edge component is emphasized by a luminance value as binary data. Similarly, the output signal EDGE of the comparator 909
Y is also calculated by the following equation.

EDGEY = 1 (UY> a (−1, −1) / B) (13) EDGEY = 0 (UY ≦ a (−1, −1) / B) (14) As described above, The vertical line component and the horizontal line component are normalized by the luminance value, and an edge detector that is strong in shooting is obtained. In addition, since the binarization is performed at the same time, there is an advantage that the subsequent processing is simplified and the circuit scale is reduced.

The edge detector 4 employs the above-described SOBEL operator to detect an edge. Instead of the Sobel operator, a PREWITT operator or Roberts (R) operator is used.
The same effect can be obtained by employing an OBERTS) operator or the like.

In the above-mentioned edge detecting section 4 , FIX
The absolute difference by the differentiators 906 and 907 is performed, and
Although the normalization based on the luminance value is performed by the comparators 908 and 909 and the divider 910, in the former, a pure edge signal in which an edge component is enhanced by removing an isolated noise component can be obtained. Edge detection with little influence can be realized, and in the latter case, edge detection that is strong in shooting can be realized by normalizing with a luminance value. Therefore, only one of them may be applied to the edge detection unit 4 .

The application of the edge detecting section 4 is not limited to the present embodiment, and an edge component is obtained from image data of a TV phone, a door phone camera, a video integrated movie, a monitoring device, a specific object detecting device, and the like. The present invention can be similarly applied to an image processing apparatus for detecting.

Next, the timing generator 2 will be described in detail. FIG. 16 is a circuit diagram showing a configuration of the timing generator 2.

In FIG. 16, the timing generator 2
Counters 1301, 1302, NAND gate 130
3, 1304, and an AND gate 1305. The pixel clock signal CLK, the horizontal synchronization pulse HD, and the vertical synchronization pulse VD supplied from a TV camera or the like are input to the timing generation unit 2. Here, the pixel clock signal CLK
To the clock input terminals of the counters 1301 and 1302,
The horizontal synchronizing pulse HD is supplied to the clear terminal of the counter 1301 and the input terminal of the AND gate 1305 to the vertical synchronizing pulse V
D is input to the clear terminal of the counter 1302. The counter 1301 is cleared by the horizontal synchronization pulse HD,
It counts up with the pixel clock signal CLK. Once mosquito <br/> down data 1301 which counts up to 255 When an 8-bit configuration, NAND gate 1303
Becomes "L", the counter 1301 is disabled, and the counting operation is stopped. When the HD pulse is input again, the above operation is repeated. That is, the counter 1301 outputs an address XADR assigned to each pixel in the X-axis direction of the image.

The counter 1302 receives the vertical synchronizing pulse VD
And is counted up every time one horizontal synchronization pulse HD is input. That is, the counter 1302 stores the address YADR assigned to the pixel in the Y-axis direction.
Becomes

FIG. 17 shows an image and addresses XADR and YAD.
The correspondence with R is shown. As shown in FIG. 17, the address XADR increases from left to right of the image, and the address YADR increases from top to bottom of the image.
Therefore, it is possible to specify a predetermined position of the image by the addresses XADR and YADR.

Next, the maximum moving object detecting circuit 9 will be described below. FIG. 18 is a diagram illustrating each mode of the mode setting circuit 20. When the mode of the mode setting circuit 20 is “1”, the output of the motion detection unit 3 is binarized motion information, which is input to the maximum motion object detection circuit 9. The maximum moving object detection circuit 9 accumulates the motion information on the X axis and detects the largest area of the moving object in the X axis direction (lateral direction) as shown in FIG. FIG.
3 is a diagram showing a configuration of a maximum moving object detection circuit 9. FIG.

In FIG. 19, the maximum moving object detection circuit 9
Represents an adder 1401, a line memory 1402, a selector 1403, a low-pass filter 1404, a peak detection circuit 1405, and comparators 1406, 1415, 1419, and 14.
21, rising detection circuit 1407, falling detection circuit 1
408, flip-flops 1409, 1410, 141
2, 1413, subtractors 1411, 1414, AND gate 1416, down counter 1417, OR gate 14
18, 1422 and an up counter 1420.

In the selector 1403, the terminal 1 and the terminal 4 are connected in the mode “1” except during the blanking period, and the adder 1401 stores the motion detection signal at the position corresponding to the same address XADR in the line memory 1402. Will be done. When the scanning of the image area ends and the vertical blanking period starts, the selector 1403 sets the terminal 2 and the terminal 4
Is connected, and every time the address XADR is updated, the motion accumulated value read from the line memory 1402 is smoothed by the low-pass filter 1404, and the line memory 140
Returned to 2. The address XADR scans in the up direction on the first line in the vertical blanking period, but in order to maintain symmetry in the X-axis direction, the second line scans the address XADR in the reverse direction and applies a low-pass filter. Multiply. At this time, an address XAD R in reverse scan, can be easily realized if passed an inverter address XADR. In the third line, the scan at the address XADR is returned in the reverse direction, and the peak value is detected by the peak detection circuit 1405 from the accumulated data in the line memory. The fourth line is a threshold value proportional to the detected peak value, and binarizes data read from the line memory 1402. The binarized one-dimensional motion information is supplied to a rising detection circuit 140.
7 and the falling pulse are input to the falling detection circuit 1408, and the rising pulse is input to the enable terminal of the flip-flop 1409, and the X coordinate at that time is obtained by holding the address XADR. Also, when the binarized one-dimensional motion information changes from “H” to “L”, the flip-flop 14
Numeral 10 holds the address XADR to obtain the falling X coordinate. In the initial state, the flip-flops 1412 and 1413 are reset to “0”. These outputs are input to a subtractor 1414, the difference between them is obtained, and the output of the subtractor 1414 is "0", which is input to the b input terminal of the comparator 1415.

On the other hand, the positions on the right and left sides of the X coordinate of the moving object output first are respectively indicated by flip-flops 14.
09 and 1410, and the size of the moving object is obtained by the difference between the flip-flops 1409 and 1410. That is, the output of the subtractor 1411 outputs the size of the moving object and is input to the a input terminal of the comparator 1415. At this time, since the signal input to the a input terminal of the comparator 1415 is larger than the signal input to the b terminal,
The output of the comparator 1415 becomes “1”, and the AND gate 1
A signal of “1” is input to one input terminal of 416.
On the other hand, when the address XADR counts up to the right end position of the object, the falling detection circuit 1408 operates,
"1" is output for one clock, and an AND gate 141 is output.
6 to the other terminal of the AND gate 1416
Is "1" for one clock. As a result, the flip-flops 1412 and 1413 are enabled,
The coordinate data of the flip-flops 1409 and 1410 are transferred to the flip-flops 1412 and 1413. If the difference between the flip-flops 1412 and 1413 is smaller than the difference between the flip-flops 1409 and 1410, the output of the comparator 1415 is “0”, and AND
The output of the gate 1416 also becomes “0”, and the flip-flops 1412 and 1413 are not updated. That is, only the coordinates of the largest moving object in the X-axis direction remain in the flip-flops 1412 and 1413, and the output signals Xa1 and Xb1
Is output as

Next, the applicable expansion function of the maximum moving object detection circuit 9 will be described. Comparator 1 which is a motion detection signal
From falling below rising detection circuit 1408 at the timing of rising falling under the output of 406 by one clock and outputs "1", the output of the subtractor 1411 is loaded into down counter 1417. The output of the subtractor 1411 at this time is the size of the moving object, and if data proportional to this output is given to the down counter 1417, the expansion width can be determined according to the size of the object. . In this case, the subtractor 14
When the output of 11 is “16”, by loading “2” shifted by 3 bits into the down counter 1417,
When counting down until “2” becomes “0”, OR
The output of the gate 1418 becomes "0" and the down counter 1417 is disabled. Accordingly, in this case, the output of the comparator 1406 is output from the OR gate 1422 as a pulse having a width of 18 by expanding a pulse having a width of 16 by two. FIG. 20 shows the waveform of each part of the maximum motion object detection circuit 9 by the above operation.

Next, in the fourth line, the selector 1403
Connects the terminal 3 and the terminal 4, and adaptively expanded data is written to the line memory 1402.

Next, on the fifth line, the operation is the same as that on the fourth line, except that the scan direction of the address XADR is reversed. On the fifth line, adaptive expansion is performed in the direction opposite to the fourth line. On the sixth line,
The operation is similar to that of the fourth line.
The only difference is that 2 is not updated.

The output of falling detection circuit 1408 is input to up counter 1420, and counts the number of falling pulses. The number of falling pulses is equal to the number of moving objects, and it is determined by comparator 1421 whether the number is sufficient. If the number is less than a predetermined number, "1" is output. The determination result is output as the object number determination result. The object width of the coordinates of the largest object stored in the flip-flops 1412 and 1413 is calculated by the subtractor 1414, and “1” is output by the comparator 1419 when the size is equal to or larger than a predetermined size. This judgment result is
Output as the maximum object determination result.

With the above operation, the maximum moving object detection circuit 9 can create dilation data adapted to the connection length of the binary image data.

The application of the maximum motion object detection circuit 9 is as follows.
The present invention is not limited to this embodiment, and is applied to, for example, an image processing device using an adaptive expansion signal in binary image processing such as a TV phone, a door phone camera, a video integrated movie, a monitoring device, and a specific object detection device. It is possible.

Next, the operation of the mode setting circuit 20 corresponding to each mode will be described. When the mode of the mode setting circuit 20 is “1”, the judgment result output from the maximum moving object detecting circuit 9 is judged by the motion judging circuit 18, and the number of moving objects is equal to or less than a predetermined number, and When the size is equal to or larger than the predetermined width, "1" is output, and the mode of the mode setting circuit is set to "2". "0" otherwise
Is output, and the mode is kept at “1”. When the mode is “1”, the frame memory 30 in the motion detection unit 3
Since 2 is not updated, the image of the m-th frame is stored. When the motion determination result is "0", the mode "1" is repeated again, and the motion information reflects the motion between the m-th frame and the (m + 2) -th frame. When the motion of the moving object is extremely slow, the motion determination result in each frame is continuously “0”, the contents of the frame memory are not updated, and the motion information is sufficient for the m-th frame and the (m + k) -th frame. Until it moves, it will not change to the next mode. The mode of the mode setting circuit 20 becomes "2" only when the moving object has sufficiently moved and the result of the motion determination becomes "1".

When the mode of the mode setting circuit 20 becomes “2”, the switching circuit 14 connects the terminal “a”, and the coordinate values Xa 1 and Xb 1 of the maximum moving object are input to the first area limiting circuit 5. On the other hand, a signal indicating the address XADR in the X-axis direction of the image is input from the timing generation unit 2, and a motion detection signal MOV 1 is input from the motion detection unit 3 to the first area limiting circuit 5. The first area restriction circuit 5 restricts the motion detection signal MOV1 in the X-axis direction and outputs the motion detection signal MOV1 to the parietal coordinate detection circuit 10. That is, as shown in FIG. 18B, only the region in the X-axis direction of the largest moving object detected in mode “1” is to be detected, and the top coordinate Ytop of the moving object in that region is the top coordinate. It is detected by the detection circuit 10.

Next, the first area limiting circuit 5 will be described in detail below. FIG. 21 is a diagram showing a configuration of the first area limiting circuit 5.

In FIG. 21, the first area limiting circuit 5
Subtractors 1701, 1704, 1713, multiplier 170
2, 1712, adders 1705, 1714, comparator 17
06, 1708, 1715, 1716, AND gate 1
703, 1709, 1711, 1717, OR gate 1
710.

When the mode is "2", the mode signal MOD
A signal of “0” is supplied as E, and the AND gate 170
The output of 3 becomes "0", and the input signals Xa1 and Xb1 of the subtractor 1704 and the adder 1705 connected at the subsequent stage are output as they are and input to the comparators 1706 and 1708. Further, since the mode signal MODE also supplies "0" to the OR gate 1710, the OR gate 1710 becomes "1" and enables the AND gate 1709. Since the address XADR is input to the other terminals of the comparators 1706 and 1708, Xa1 ≧ XAD
When R ≧ Xb1, the outputs of the comparators 1706 and 1708 become “1”, the AND gate 1709 becomes “1”, and A
Enable the ND gate 1711. That is, the figure
As shown in FIG. 18B, as the image address XADR, the motion detection signal MOV1 of only the region from the coordinates Xa1 to Xb1 is to be processed.

Next, the parietal coordinate detecting circuit 10 will be described in detail below. FIG. 22 is a diagram showing a configuration of the parietal coordinate detection circuit 10.

In FIG. 22, the top coordinate detecting circuit 10
Includes a Y-axis projector 191, a labeling connection unit 192, and a parietal coordinate detection unit 193.

The Y-axis projector 191 includes the first area limiting circuit 5
Are cumulatively added in the scanning line direction, that is, in the X direction, to perform Y-axis density projection. This is shown in FIG. Top coordinate detection circuit 10
Has the same configuration as that of the maximum moving object detection circuit 9 and can be shared. The labeling connection portion 192 is Y
A low-pass filter is applied to the motion detection signal that is density-projected on the axis, a peak is detected, binarization is performed according to the peak value, expansion is performed, and labeling is performed. The top coordinate detection unit 193 detects the top coordinate Ytop position of the largest object in the Y-axis direction based on the output of the labeling connection unit 192, and outputs the same. This operation is completed by the operation of one field, and the mode of the mode setting circuit 20 becomes "3".

When the mode of the mode setting circuit 20 becomes "3", the second area limiting circuit 6 and the motion feature amount extracting circuit 1
1, and the motion determination circuit 18 is enabled. Second
A motion detection signal MOV of the motion detection unit 3 is
1. X coordinate Xa1, Xb1 and top coordinate Ytop of the target object detected in mode "1" and mode "2", and address XAD output from timing generation section 2
R and YADR are input, and the motion detection signal is
(C) as shown in FIG.

FIG. 23 shows the structure of the second area limiting circuit 6. Since the second area limiting circuit 6 has the same configuration as the first area limiting circuit 5 shown in FIG. 21, the description thereof will be omitted.

The masked motion detection signal is input to the motion feature extraction circuit 11. In the motion characteristic amount extraction circuit 11, the perimeter YL of the motion area, the vertical length L0 of the motion area, and the area S
0, X-end coordinates Xa2 and Xb2 of the motion area are extracted. FIG. 24 is a diagram showing the perimeter YL of the motion area.
FIG. 26 is a diagram showing the vertical length L0 of the motion region, and FIG. 26 is a diagram showing the area S0 of the motion region.

When the address YADR of the image on the vertical axis is j, the leftmost coordinate MXLj and the rightmost coordinate MXRj of the X-axis address for which the motion detection signal MOV1 is "1", and Y for which the motion detection signal is detected first Assuming that the coordinate is jmin and the Y coordinate at which the motion detection signal is finally detected is jmax, the peripheral length YL0, the vertical length L0, and the area S0 are represented by the following equations.

YL = MXR _jmin −MXL _jmin + MXR _jmax −MXL _jmax + Σ (| MXR _{j −MXR j + 1} | + | MXL _j −MXL _{j + 1} |) (15) (where Σ is j = jmin to L0 = jmax−jmin (16) S0 = Σ | MXR _j −MXL _j | (17) The motion of the walking person moves substantially in the horizontal direction with respect to the camera. Therefore, since the temporal change is large near the vertical position of the cheek, it easily appears as a motion detection signal, and the detection signal near the face is expressed as an area shown in FIG. In the motion feature amount extraction circuit 11, YL, L0, S
0 is calculated and output to the motion determination circuit 18. FIGS. 27 and 28 show a first example of the motion detection signal when the motion is insufficient.
And a second diagram. When the movement of the target object is small, the motion detection signal includes many isolated islands as shown in FIG. 27, the perimeter YL is large, and the area S0 is small. In addition, as shown in FIG. 28, only one edge portion may be vertically elongated. The above case is evaluated by a value calculated by the following equation.

A = S0 / YL (18) b = L0 / sqr (S0) (19) c = S0 / Xlen / Xlen (20) When the motion of the object is large, the value of a is large. , B
Is small, and the value of c is large. Predetermined threshold a
0, b0, c0 are set, and a> a0 and b <b0,
When c> c0, it can be determined that the target object has sufficiently moved. In the motion determination circuit 18, the input motion feature values YL, L0, S0 and the input Xlen = Xb1-Xa1 input from the maximum motion object detection circuit 9 are obtained.
From the above, and when it is determined that the movement of the target object is sufficient, the mode of the mode setting circuit 20 is set to “4” and the process proceeds to the next determination mode. In other cases, the mode is set to "1", and the moving object is measured again after waiting for the moving object to move further. That is, when the movement of the target object is very slow, the mode “1”,
It repeats "2" and "3" and waits without updating the contents of the frame memory 302 until a sufficient motion has occurred for the first frame. When it is judged that the motion is sufficient, the next mode is "4". Operate to move forward. When the movement of the target object is large, the mode immediately proceeds to the mode “4” after the mode “3”. By the above operation, even slow moving objects,
It is possible to accurately determine whether or not a fast-moving object has sufficiently moved.

The motion amount judging means composed of the motion characteristic amount extracting circuit 11 and the motion judging circuit 18 is not applied only to the present embodiment, but includes a TV phone, an intercom camera, a video integrated movie, The present invention is also applicable to other image processing devices such as a device and a specific object detection device.

In the mode "3", in addition to the above-described determination of the amount of motion, the coordinates Xa of both ends of the target object are obtained from the motion detection signal.
2. Detect Xb2. The mode “3” is shown in FIG.
An outline of the operation will be described. In a region surrounded by the coordinates Xa1 and the coordinates Xb1, Y in which the motion detection signal detected first exists
The process proceeds in the scanning direction from the coordinates, that is, Ytop, and the coordinates where the motion detection signal detected first on the same horizontal line exists are XL (j), and the coordinates detected last are XR
Assuming (j), the two detected coordinates Xa2 and Xb2 are represented by the following equations.

Xa2 (j) = XL (j) × (1-k) + Xa2 (j−1) × k (21) Xb2 (j) = XR (j) × (1-k) + Xb2 (j−1) ) × k (22) where k is a cyclic coefficient and 0 <k <1 j = Ytop + 1 to Ytop + (Xb1 + Xa1) / 2 Xa2 (Ytop) = XL (Ytop) Xb2 (Ytop) = XR (Ytop) A detection circuit for the coordinates Xa2 and Xb2 included in the motion feature amount extraction circuit 11 that performs the above calculation will be described. FIG. 29 is a block diagram illustrating a configuration of a detection circuit included in the motion feature amount extraction circuit 11 .

In FIG. 29, the detection circuit includes a top coordinate detection section 261, a Xa2 (j) detection section 262, and an Xb2 (j)
A detection unit 263 and recursive filters 264 and 265 are included. The motion detection signal output from the second area limiting circuit 6 is input to the parietal coordinate detection unit 261 and is output as the coordinate Ytop2 at which the motion detection signal first appears in the Y-axis direction. j) Detector 262, Xb2
(J) Output to the detection circuit 263. The Xa2 (j) detection circuit 262 and the Xb2 (j) detection circuit 263 start operating in response to the trigger signal, detect Xa2 (j) and Xb2 (j), and output them to the cyclic filters 264 and 265. In the recursive filters 264 and 265, the above calculation is performed to obtain the coordinates Xa2 and Xb2 at both ends of the target object.

In mode "4", as shown in FIG. 18D, Xa2, Xb2, Yt detected in mode "3"
By op2, the processing target area is further narrowed, and the cheek position values Xa3 and Xb3 of the person are detected more precisely by using the motion detection signal and the vertical edge signal therein. In other words, the position of the moving object and where the vertical edge is tight is regarded as the position of the cheek. The motion detection signal output from the motion detection unit 3 and the vertical edge signal detected by the edge detection unit 4 are input to a third area limiting circuit 7.

Next, the third area limiting circuit 7 will be described in detail. FIG. 30 is a block diagram showing a configuration of the third area limiting circuit 7.

In FIG. 30, the third area limiting circuit 7
Subtracters 271, 273, multipliers 272, 278, 28
5, switch 284, adders 274, 279, comparator 2
75, 276, 280, 281, AND gate 282,
283.

The cheek coordinates Xa2 detected in the mode “3”,
Xb2 is the difference × len2 = Xb2-X in a subtractor 271.
a2 is calculated. In this mode, the switch 284 is connected to the divider 272 and the divider 272
len2 is divided by 2 and input to the terminal b of the subtractor 273. Since the cheek coordinates Xa2 are input to the terminal a of the subtractor 273, the subtracter 273 outputs Xa2- (Xb2-Xa
2) / 2 = (3 × Xa2−Xb2) / 2 is output. The output of the subtractor 273 is input to the terminal b of the comparator 275, and the address signal XADR is input to the terminal (a) of the comparator 275. When the value of the address signal XADR is (3 × Xa2
-Xb2) / 2, the comparator 275 outputs "1". Since Xb2 is input to one input of the adder 274 and (Xb2-Xa2) / 2 is input to the other input, the adder 274 outputs Xb2 + (Xb2-Xa2) / 2.
= (3 × Xb2−Xa2) / 2 is output to the terminal b of the comparator 276. Since the address signal XADR is input to the other a terminal of the comparator 276, the comparator 276 eventually outputs the address XADR of (3 × Xb2-Xa2) /
"1" is output while it does not exceed 2. In the Y-axis direction, if the address YADR exceeds the coordinate Ytop2 by the same operation, the comparator 280 outputs “1” and the address YADR
While DR does not exceed Ytop + (Xb2−Xa2) × 3/4, the comparator 281 outputs “1”. Comparator 27
5, 276, 280, 281 are connected to AND gate 2
The logical product is obtained at 82 and output to the AND gate 283. Since the motion detection signal and the vertical edge detection signal are applied to the other input terminals of the AND gate 283,
The output of the AND gate 283 is output to the precision cheek coordinate detection circuit 12 as a vertical edge signal with movement limited to a region surrounded by a rectangle as shown in FIG. By the above processing, the motion feature amount extraction circuit 11 and the third area restriction circuit 7 set the top coordinate Y as stable object coordinates.
Top2, left coordinate Xa2, and right coordinate Xb2 can be detected.

The above-mentioned motion feature quantity extraction circuit 11 and third
The detection of the moving object coordinates by the area limiting circuit 7 is not applied only to the present embodiment, and the image for detecting the moving object coordinates of a TV phone, a door phone camera, a video integrated movie, a monitoring device, a specific object detecting device, etc. It is equally possible to apply to a processing device.

Next, the precise cheek coordinate detection circuit 12 will be described in detail. FIG. 31 is a block diagram showing the configuration of the precision cheek coordinate detection circuit 12.

In FIG. 31, the precision cheek coordinate detecting circuit 12
Are adders 291, 296, AND gates 292, 29
4, 295, memory 293, divider 297, comparator 29
8, including peak detection circuits 299 and 300, and flip-flops 301 and 302.

FIG. 32 shows the operation timing of the precision cheek coordinate detection circuit 12. In the cumulative memory reset timing area 1 shown in FIG. 32, the reset signal / RESET (hereinafter, “/” indicates an inverted signal) output from the timing generator 2 is used while scanning the line of which the address YADR is 0. "0" is applied to the AND gate 292,
The AND gate 292 outputs “0” and supplies it to the terminal I of the memory 293. Read-write signal R / W and the address XADR is supplied from a timing generator 2, address XADR is incremented for each pixel, the read write signal R / W is one cycle supplied to each pixel. Therefore, when the scanning for one line is completed, all the contents of the memory 293 are cleared. The cumulative addition timing area 2 is a timing for accumulating the motion and vertical edge signals (movement × vertical edge signal) restricted by the third area restriction circuit 7 in the image area in the Y-axis direction. In the above two areas, the reset signal / RESET becomes "1", and the read / write signal R / W is also supplied for one cycle for each pixel. At this time, the contents of the memory 293 and the result of the addition of the moving and vertical edge signals are returned to the memory 293, and the moving and vertical edge signals corresponding to the same address XADR are cumulatively added and stored at the corresponding address of the memory 293. You. In the peak position detection timing area 3, the memory 2
A peak value of the value accumulated in 93 is searched for, and an address XADR corresponding to the peak value is extracted. The cheek coordinates Xa2 and Xb2 detected in the mode “3” are supplied from the switching circuit 16 to the adder 2
96, and the adder 296 outputs Xa2 + Xb2
, And halved by the divider 297 , and (Xa2 + Xb2) / 2 is supplied to the terminal b of the comparator 298. Since the address XADR is supplied to the terminal a of the comparator 298, the address XADR is set at the center coordinates (Xa2 + Xb) of the face.
If the value is smaller than 2) / 2, the output of the comparator 298 becomes "0" and the gate 294 is turned on. Gate 29
4 turns on, the peak detection circuit 299 and the flip-flop 301 become operable. When the largest value is input, the peak detection circuit 299 generates one pulse, and the address XA corresponding to the connected flip-flop 301 is output.
Latch DR. When the address XADR becomes larger than the center coordinate (Xa2 + Xb2) / 2 of the face, the gate 295 is set.
Is turned on, and the peak detection circuit 300 and the flip-flop 302 operate. At this time, the address XADR corresponding to the peak position of the memory 293 is stored in the flip-flop 3
02 latches. The coordinates stored in the flip-flops 301 and 302 are respectively the coordinates corresponding to the left cheek.
a3, the coordinates corresponding to the right cheek are output as Xb3.
The above peak detection operation is completed during one line. An outline of the operation in the mode “4” is shown in FIG.
Through the above operation, it is possible to detect the precise left and right coordinates of the moving object. Above precision cheek coordinate detection circuit 1
Detection of precise left coordinates and right coordinates of the animal body by 2 is not intended to apply only to this example, TV telephone, intercom camera, a video integrated movies, monitor, animal body, such as a specific object detection device The present invention can be similarly applied to an image processing device that detects precise left and right coordinates of the image processing device.

In the mode "4", the fourth area limiting circuit 8 and the feature extracting circuit 13 operate at the same time. In FIG.
4 shows a configuration of a fourth area limiting circuit 8. In FIG. 33 , a fourth area limiting circuit 8 includes subtractors 311, 313 and a divider 3
12, 317, 318, adders 314, 319, 32
0, comparators 315, 316, 321, 322 and AND gates 323, 324, 325 are included. The configuration of the fourth area limiting circuit 8 is the same as that of the third area limiting circuit 7 shown in FIG. 30. The difference is that the limited area in the Y-axis direction is different, and the signal to be limited is a vertical edge. That is, there are two systems, a signal and a horizontal edge signal. The reason why the top coordinate of the Y axis is Ytop + Xlen / 4 is that the characteristics of the hair vary from person to person, so the hair part is masked,
This is for extracting only the features near the eyes.

Next, the feature extracting circuit 13 will be described in detail. The feature extraction circuit 13 accumulatively adds the limited edge signals in the Y-axis direction as shown in FIG. 18E, and calculates the coordinates Xa3 and Xb3 detected by the precision cheek coordinate detection circuit 12 as n.
Divided and, further integrated in each of the divided blocks, the vertical edge feature quantity SX ₀ ~SX _n-1, the lateral edge feature quantity SY ₀ to S
Yn _-1 is obtained.

FIG. 34 shows the configuration of the feature extraction circuit 13.
In FIG. 34 , the feature extraction circuit 13 includes an adder 331,
334, 339, AND gates 332, 335, 33
8, memories 333 and 336, selector 337, flip-flop 340, operation unit group 341, comparator group 342, O
R gates 343 and 344, flip-flop group 345,
346.

The reset signal / RESET is supplied from the timing generator 2 to the AND gate 332.
FIG. 35 shows the operation timing of the feature extraction circuit 13.
In the cumulative memory reset timing area 1 shown in FIG. 35, the reset signal / RESET is “0”, and
The output of the gate 332 becomes "0", and the contents of the memory 333 are cleared. In the cumulative addition timing area 2, a vertical edge signal is added to the data read from the memory 333.
At 31, the value is added and written into the memory 333 again. This operation is performed during one pixel, and the vertical edge signal corresponding to the same address XADR is accumulated in the memory 333. The configurations of the adder 334, the AND gate 335, and the memory 336 are the same as those of the adder 331, the AND gate 332, and the memory 333, and the horizontal edge signal is accumulated in the memory 336 in the same manner. The arithmetic unit group 341 calculates the weighted sum Si as shown in the following equation from Xa3 and Xb3 detected by the precise cheek coordinate detection circuit 12.

[0125]

(Equation 1)

The weighted sum Si is input to each terminal b of the comparator group 342. The weighted sum Si is Xa3 and Xb
3 represents n-divided coordinates, and each terminal a of the comparator group 342 is supplied with the X-axis address XADR. Therefore, the output of the comparator group 342 generates a corresponding sequential pulse of the address XADR. Pulses corresponding to the weighted sum S ₀ ~S _n-1 is synthesized by an OR gate 343, weighted sum S ₁
The pulses corresponding to .about.S _n are combined by the OR gate 344. The OR gate 343 sets the AND gate 338 to "0" as a clear signal, and the OR gate 344 supplies a transfer pulse to the enable terminals of the flip-flop groups 345 and 346.

When the address XADR becomes the weighted sum S ₀ , the output of the OR gate 343 becomes “1”, and the AND gate 338 becomes “0”. Assuming that the selector 337 is connected to the terminal A, the projection value of the vertical edge corresponding to the address XADR on the X axis is supplied to the terminal a of the adder 339, and is taken into the flip-flop 340 as it is. When the clock advances by one pixel, the address XADR also increases by 1, the OR gate 343 becomes “0”, the output of the flip-flop 340 is supplied to the terminal b of the adder 339, and the vertical edge is added to the projection value on the X axis. Is written to the flip-flop 340 again. The output of the flip-flop 340 is output to the flip-flop groups 345 and 34 at the subsequent stage.
6 are supplied to the "1" for each timing of the OR gate 344 is S ₁ to S _n, and the sequence integrated feature quantity SX ₀ ~SX _n-1 flip-flop group 345
Will be transferred to FIG. 36 shows the above series of operations.

In the horizontal line feature extraction timing area 4 shown in FIG. 35, the selector 337 is connected to the terminal B, calculates the horizontal edge feature quantities SY _{0 to} SY _n−1 by the same operation as described above, and outputs the flip-flop group 345. , 346. With the above-described operation, a feature amount near the eyes of the face can be obtained.

Timing of horizontal line feature extraction timing area 4
And then the above feature SX₀~ SX _n-1, SY₀~ SY
_n-1Is input to the evaluation determination circuit 17 and is determined to be a human
Is not determined.

Next, the evaluation judgment circuit 17 will be described in more detail. FIG. 37 is a block diagram illustrating a configuration of the evaluation determination circuit 17.

In FIG. 37, the evaluation judging circuit 17 includes nonlinear converters 351 to 356, multipliers 357 to 362, a constant generator 363, an adder 364, and a comparator 365.

The feature values SX _{0 to} SX _n−1 and SY _{0 to} SY
_n-1 is supplied from the feature extraction circuit 13 and input to the m nonlinear converters 351 to 356. Nonlinear converter 35
In steps 1 to 356, the conversion of the analysis function system is performed. For example, such as normalization operation _{U0 = SX 0 / (SX 0} + S
_{X 1 + ... + SX n-} 1), U1 = SX 0 / SY 0, U2 =
Non-linear conversion in which the relationship between input and output is fixed in advance such as SX ₀ / SX _n-1 is performed. When a neural network is used, the weighting factor is determined by learning, and the relationship between input and output is a non-linear transformation based on learning alone. Therefore, the data used for learning requires an enormous amount, and the amount of calculation required for learning is also enormous. However,
In the present embodiment, since known constraint conditions and known knowledge, such as left-right symmetry, physical conditions in which the direction changes, and normalization, can be incorporated into the nonlinear conversion units 351 to 356, learning data is small. I can do it. Also, in learning, since the method of finding the coefficient of the linear sum using the least squares method of the error results in a problem of releasing the simultaneous linear equations, the amount of calculation for determining the constant is very small.
If Lagrange's undetermined constant method is used, it is possible to further add a constraint condition at the learning stage.

Non-linear converters 351 to 356 output output signals U _{0 to} U _m−1 , respectively, and are multiplied by predetermined coefficients WX _{0 to} WX _m−1 by multipliers 357 to 362, and each output is multiplied by a coefficient WX
_m is calculated by the adder 364 as follows.

Y = ΣWX _i × U _i (28) where i = 0 to _m , U _m = 1,0 The coefficient WX _i is a constant determined by learning based on previously given data. Can be determined. For example, the feature amount of the class of a person is SX ₀ , j to S
X _n−1 , j, SY ₀ , j to SY _n−1 , j (j = 0 to p−
1), SX ₀ , k to S
_{X n-1, k, SY} 0, k~SY n-1, k (k = 0~q-
Assuming that 1), the evaluation value of the average value of a person corresponds to “0”, and the evaluation value of the average value of a person other than a person corresponds to “1”.
9) It is sufficient to determine WX _i that minimizes the expression.

[0135]

(Equation 2)

That is, the above (30), (31),
WX _i is determined from the (m + 2) -dimensional simultaneous equation of equation (32).

When the constant WX _i learned as described above is applied to the multipliers 357 to 362 and the constant generator 363, the evaluation value W is close to “1” when the target object is a person, and otherwise, The evaluation value Y approaches "0". in this case,
If the threshold value of the comparator 365 is set to 0.5, the discrimination becomes possible. When the evaluation value Y is close to "1", the comparator 36
5 outputs “1”, and when the evaluation value Y is close to “0”, the comparator 365 outputs “0”, and the mode setting circuit 2 in the next stage
0.

As described above, the evaluation judging circuit 17 includes not only a nonlinear conversion group for obtaining a single evaluation value and a linear addition / summing circuit, but also a circuit for obtaining a plurality of evaluation values, a plurality of comparators, and an appropriate OR. A gate and an AND gate may be used for evaluation judgment from a plurality of evaluation values.

By the operation described above, the evaluation judgment circuit 17
Since it is composed of non-linear conversion means using a simple analysis function and linear addition means with a small amount of calculation, it is possible to accurately determine a specific target with a much smaller calculation amount than when using a neural network. Become.

The evaluation determining circuit 17 is not applied only to the present embodiment, but is applied to a TV phone, a door phone camera,
The present invention can be similarly applied to an image processing device that determines a specific target, such as a video-integrated movie, a monitoring device, and a specific object detection device.

Next, when the output of the evaluation judging circuit 17 is "1", the mode becomes "5" in the next frame.
When the output of the evaluation determination circuit 17 is "0", the next frame is "0".

In mode "5", switching circuit 1 shown in FIG.
4 and 16 select the terminal b, and the coordinate Xa3 detected in the previous frame is replaced with the coordinate Xb instead of the coordinates Xa1 and Xa2.
1, coordinates X detected in the previous frame instead of Xb2
b3 is supplied. Also, the write mode control signal becomes “1”, and the frame memory 30 in the motion detection unit 3
2 is in read and write mode. In the write mode of the frame memory 302, the first half cycle is read out in one pixel cycle, and the write operation is performed in the second half cycle. At this time, the second region restriction circuit 6, the motion feature amount extraction circuit 11, the third region restriction circuit 7, the precise cheek coordinate detection circuit 1
Second, the fourth area limiting circuit 8, the feature extracting circuit 13, and the area determining circuit 17 operate simultaneously. In mode "4", the coordinates Xa3 and Xb3 of the face and the top coordinate Ytop2 are already known, and since the moving speed of the face is slower than the frame rate, the face does not move so much in the next frame. By utilizing this characteristic, the coordinates Xa3, X
A search range is provided based on b3 and Ytop2. FIG.
It is a figure showing an example of a search range. FIG. 38 shows an example in which the search range is set to 1/8 of Xb3-Xa3. The motion feature amount is processed only by the second area limiting circuit 6 within the search range. When the mode is "5", the mode signal MODE becomes "1" and the comparator 18 shown in FIG.
Xa3-Xlen / 8 for 06, X for comparator 1808
b3 + Xlen / 8, the comparator 1813 has Ytop-X
len / 8, the comparator 1814 has Ytop + Xlen ×
9/8 is input, and the motion detection signal MOV1 is limited only in a predetermined area by the AND gates 1809 and 1811. FIG. 39 shows an area restricted by the second area restriction circuit 6. The restricted motion detection signal MOV1 is supplied to the motion feature amount extraction circuit 11, and extracts and determines the motion feature amounts YL, L0, S0, and Ytop2 as in the mode "3".

On the other hand, in the third area limiting circuit 7, the switch 284 shown in FIG. 30 is connected to the divider 285, and moves from the coordinates Xa3, Xb3 and Ytop2 detected in the previous frame to a rectangular area as described above, and moves vertically. Limit edge signals. FIG. 40 shows an area restricted to a rectangular area by the third area restriction circuit 7. The precision cheek coordinate detection circuit 12 newly detects the coordinates Xa3 and Xb3 as in the mode “4”.
The fourth area limiting circuit 8, the feature extracting circuit 13, and the evaluation judging circuit 17 operate in the same manner as in the mode "4". Motion judgment circuit 1
When the tracking target has sufficiently moved by 8 and the tracking target is determined to be a person, the process proceeds to mode “6”. Mode "6"
The operation of is that the frame memory 302 of the motion detection section 3 is in the read-only mode, and the reference image is not updated, but the second area restriction circuit 6, the motion feature amount extraction circuit 11, the motion determination circuit 18, the third area restriction circuit 7, the operations of the precise cheek coordinate detection circuit 12, the fourth region restriction circuit 8, the feature extraction circuit 13, and the evaluation determination circuit 17 are the same.

FIG. 41 is a diagram for explaining the operation in each mode. FIG. 41 shows a state transition of a mode change of the mode setting circuit 20. Modes "0" to "3" are routines for waiting until the moving object moves. Mode "4" is a determination mode for determining whether or not a person is a person. This is a human detection operation mode for detecting. The mode “5” and the mode “6” are human tracking operation modes for tracking a detected person, which will be described later.

When the above-described human tracking operation mode continues, the top coordinate Ytop2 detected by the motion feature amount extraction circuit 11 and the cheek coordinate Xa3 detected by the precise cheek coordinate detection circuit 12 with the movement of the person being photographed. Xb3 is input to the tracking target coordinate output circuit 19, and the tracking target coordinate output circuit 19 generates a control signal for clipping and enlarging the image, and outputs the control signal to the enlarged display circuit 21. On the other hand, the digital image signal output from the A / D converter 1 is subjected to a predetermined delay operation and a complementary operation in the enlarged display circuit 21, and is output to the D / A conversion circuit 22. This digital image signal is supplied to a D / A conversion circuit 2
Display 23 after being converted into an analog image signal in step 2
Is displayed with. Through a series of these operations, it is possible to detect a person from a captured image, track the person, and enlarge and display the person's face as a center.

As described above, in this embodiment, since the motion detection is performed while judging the motion, a stable moving object can be detected, and the characteristic edge component of the image information is used. Therefore, it is possible to accurately recognize the target object.

[0147]

According to the image processing apparatus of the first aspect,
Is based on the perimeter, vertical length, and area of the target area.
To determine whether the movement of the object in the elephant area is sufficient
Therefore, even if the object moves slowly or fast,
It is possible to determine stably whether or not it has moved.

In the image processing apparatus according to the second aspect,
Create difference image data based on the output of the motion determination means
Frame interval at the time of transmission is controlled. Therefore, the target object
Regardless of the amount of movement of the target object,
Can be

In the image processing apparatus according to the third aspect,
For each pixel, binary based on the brightness value of the input image data
An activation threshold is determined. As a result, the shadow
Stable motion information that is not affected and is strong in shading
Obtainable.

In the image processing apparatus according to the fourth aspect,
Expansion processing is performed on the motion detection signal. Therefore, motion detection
Outgoing signal defects can be filled and stable motion information
Obtainable.

In the image processing apparatus according to the fifth aspect,
The motion detection signal is blurred and expanded by the expansion means, and the expansion is performed.
It is possible to obtain binary image data expanded by the image binarizing means.
So that it can be spread over a large area with a small circuit scale.
To obtain dilated binary image data.

In the image processing apparatus according to the sixth aspect,
Rising timing and falling timing of binary image signal
The binary image signal in response to the time difference
Therefore, it is possible to obtain dilated image data adapted to the time difference.
Wear.

In the image processing apparatus according to the seventh aspect,
Signal of first start position and first end position of motion information
The signal of the second position is stabilized by the first and second conversion means.
Convert to start position signal and second end position signal
The difference between these signals and the counting means
Numerical values are compared with each other, and the first and second determination means are
Since the operation of the step is controlled, the coordinates of both ends of the target object are stable.
Can be obtained.

In the image processing apparatus according to the eighth aspect,
Logic between binarized motion detection signal and vertical line component of edge
The product is projected in the horizontal direction of the image, and the peak position of the projected signal is
By detecting the position, the horizontal axis of the target object in the image
The coordinates of both ends can be obtained, and the precise horizontal axis of the target object can be obtained.
The coordinates of both ends of the direction can be obtained.

In the image processing apparatus according to the ninth aspect,
An isolated noise component by the first and second differentiating means
And the vertical line component of the edge based on the absolute value of the difference value
And horizontal line components. As a result, the isolated noise component
To get a pure edge signal
It is possible to obtain edge signals that are less affected by noise.
Wear.

In the image processing apparatus according to the tenth aspect,
Is obtained by normalizing the edge component by the luminance value.
Output edge signals that are not affected by fluctuations in brightness
To get a strong edge signal for shooting
Can be. In the image processing device according to claim 11,
The non-linear conversion means generates an analysis function for performing a predetermined non-linear conversion.
This simplifies the processing and makes the linear addition
Since the calculation amount is small, the target included in the image with a small calculation amount
The object can be specified.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a configuration of an information processing apparatus according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating a configuration of a motion detection unit of the information processing apparatus according to one embodiment of the present invention.

FIG. 3 is a diagram illustrating a generation process of binarized image data of an absolute difference.

FIG. 4 is a diagram illustrating a configuration of a smoothing circuit of a motion detection unit of the information processing apparatus according to one embodiment of the present invention.

FIG. 5 is a diagram illustrating a configuration of a horizontal expansion circuit of a motion detection unit of the image processing apparatus according to one embodiment of the present invention.

FIG. 6 is a diagram illustrating a configuration of a first vertical expansion circuit of a motion detection unit of the image processing apparatus according to one embodiment of the present invention.

FIG. 7 is a diagram illustrating a signal waveform of a first vertical expansion circuit.

FIG. 8 is a diagram illustrating a configuration of a second vertical expansion circuit of the motion detection unit of the image processing device according to one embodiment of the present invention.

FIG. 9 is a diagram illustrating a configuration of an addition / subtraction circuit of a second vertical expansion circuit of the motion detection unit of the image processing apparatus according to one embodiment of the present invention.

FIG. 10 is a diagram showing a signal waveform of a second vertical expansion circuit.

FIG. 11 is a diagram illustrating a configuration of an edge detection unit of the image processing apparatus according to one embodiment of the present invention.

FIG. 12 is a diagram illustrating a configuration of an X differentiator of an edge detection unit of the image processing device according to one embodiment of the present invention.

FIG. 13 is a diagram illustrating a configuration of a Y differentiator of an edge detection unit of the image processing device according to one embodiment of the present invention.

FIG. 14 is a diagram illustrating a configuration of a first FIX differentiator of the edge detection unit of the image processing apparatus according to one embodiment of the present invention.

FIG. 15 is a diagram illustrating a configuration of a second FIX differentiator of the edge detection unit of the image processing apparatus according to one embodiment of the present invention.

FIG. 16 is a diagram illustrating a configuration of a timing generation unit of the image processing apparatus according to one embodiment of the present invention.

FIG. 17 is a diagram showing the correspondence between an image and addresses XADR and YADR.

FIG. 18 is a diagram illustrating each mode of the mode setting circuit.

FIG. 19 is a diagram showing a configuration of a maximum moving object detection circuit of the image processing apparatus according to one embodiment of the present invention.

FIG. 20 is a diagram showing waveforms at various parts of the maximum motion object detection circuit.

FIG. 21 is a diagram illustrating a configuration of a first area limiting circuit of the image processing apparatus according to one embodiment of the present invention.

FIG. 22 is a diagram illustrating a configuration of a top coordinate detection circuit of the image processing apparatus according to one embodiment of the present invention.

FIG. 23 is a diagram illustrating a configuration of a second area limiting circuit of the image processing apparatus according to one embodiment of the present invention.

FIG. 24 is a diagram showing a perimeter YL of a motion area.

FIG. 25 is a diagram illustrating a vertical length L0 of a motion area.

FIG. 26 is a diagram showing an area S0 of a motion region.

FIG. 27 is a first diagram illustrating a motion detection signal when the motion is insufficient.

FIG. 28 is a second diagram illustrating a motion detection signal when motion is insufficient.

FIG. 29 is a diagram illustrating a configuration of a detection circuit of a motion feature amount extraction circuit of the image processing apparatus according to one embodiment of the present invention.

FIG. 30 is a diagram showing a configuration of a third area limiting circuit of the image processing apparatus according to one embodiment of the present invention.

FIG. 31 is a diagram showing a configuration of a precise cheek coordinate detection circuit of the image processing apparatus according to one embodiment of the present invention.

FIG. 32 is a diagram showing the operation timing of the precision cheek coordinate detection circuit.

FIG. 33 is a diagram illustrating a configuration of a fourth area limiting circuit of the image processing apparatus according to one embodiment of the present invention;

FIG. 34 is a diagram showing a configuration of a feature extraction circuit of the image processing apparatus according to one embodiment of the present invention.

FIG. 35 is a diagram showing the operation timing of the feature extraction circuit.

FIG. 36 is a timing chart illustrating the operation of the feature extraction circuit.

FIG. 37 is a diagram illustrating a configuration of an evaluation determination circuit of the image processing apparatus according to one embodiment of the present invention.

FIG. 38 is a diagram showing an example of a search range.

FIG. 39 is a diagram illustrating an area restricted by a second area restriction circuit.

FIG. 40 is a diagram showing an area restricted to a rectangular area by a third area restriction circuit.

FIG. 41 is a diagram illustrating the operation of each mode.

FIG. 42 is a block diagram illustrating a configuration of a conventional image processing apparatus.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 A / D conversion part 2 Timing generation part 3 Motion detection part 4 Edge detection part 5 1st area restriction circuit 6 2nd area restriction circuit 7 3rd area restriction circuit 8 4th area restriction circuit 9 Maximum motion object detection circuit 10 Top Coordinate detection circuit 11 Motion feature extraction circuit 12 Precise cheek coordinate detection circuit 13 Feature extraction circuit 14-16 switching circuit 17 Evaluation judgment circuit 18 Motion judgment circuit 19 Tracking target coordinate output circuit 20 Mode setting circuit 21 Enlarged display circuit 22 D / A Conversion circuit 23 Display

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G06T 7/20

Claims (11)

(57) [Claims] 1. An input image data, said input image data
From the reference image data input before the predetermined frame
Create difference image data and binarize the difference image data
And a binarizing means for outputting a motion detection signal, and detecting a perimeter of a region extracted from the motion detection signal.
Peripheral length detecting means, and the vertical length of the region extracted from the motion detection signal.
Vertical length detecting means for detecting, and detecting an area of a region extracted from the motion detection signal
Area detecting means , based on the perimeter, the length in the vertical direction, and the area
The motion of the object in the region extracted from the motion detection signal.
Motion determining means for determining whether the displacement is equal to or greater than a predetermined value.
An image processing device. 2. The method according to claim 1 , wherein said binarizing means includes:
The input image data and the reference image data based on the output.
The method according to claim 1, wherein a frame interval between the frame and the frame is controlled.
Image processing device. 3. The apparatus according to claim 2, wherein said binarizing means includes a step of :
Based on the luminance value of each pixel
Determining a threshold value and, based on the threshold value,
The image according to claim 1, wherein the image data is binarized.
Processing equipment. 4. The binarizing means according to claim 1 , wherein said binarizing means calculates said difference from said input image data and said reference image data.
Create differential image data and binarize the differential image data
Differential image data binarizing means for outputting a motion detection signal
And a binary image expanding means for performing expansion processing on the motion detection signal;
The image processing apparatus according to claim 1, wherein
Place. 5. The binary image expanding means according to claim 1 , wherein each of the pixels of the motion detection signal is subjected to a predetermined operation.
The luminance value of each pixel of the motion detection signal
Expansion means for creating expanded image data
And dilation for binarizing the dilated image data with a predetermined threshold value
The image processing apparatus according to claim 4, further comprising: an image binarizing unit.
Place. 6. The binary image expanding means includes a rising edge of a luminance value for each row of the motion detection signal.
Rising detection means for detecting the timing of the falling edge of the luminance value for each row of the motion detection signal.
Falling detection means for detecting the timing,
A time difference measuring means for measuring a time difference; and expanding the motion detection signal in accordance with the time difference.
Dilation means for generating dilated image data, and dilation for binarizing the dilated image data with a predetermined threshold value
The image processing apparatus according to claim 4, further comprising: an image binarizing unit.
Place. 7. The first information in the vertical direction of the motion detection signal.
The counting operation is performed with the timing at which the
Counting means; a first start position in the horizontal direction of the motion detection signal;
Position detecting means for detecting an end position; extracting a low-frequency component of the signal at the first start position;
Is output and converted to a signal at the second start position.
First converting means for extracting a low-frequency component of the signal at the first end position;
A second circuit that circulates the output and converts it to a signal at the second end position
Converting means for calculating a difference value between the second start position and the second end position.
A difference value calculating means for calculating, and the count value of said counting means and said difference value is compared, comparing binding
Controlling the operation of the first and second conversion means based on the result
7. The method according to claim 1, further comprising a control unit.
Image processing device. 8. An edge is extracted from the input image data.
Edge extraction means, and a logical product of the motion detection signal and a vertical line component of the edge.
A logical processing means for calculating for the horizontal of the input image data the calculation result of the logic processing unit
Converting means for converting into a signal projected in the axial direction, and detecting a peak position of the signal converted by the converting means
The image processing apparatus according to claim 7, further comprising:
Equipment. 9. The first edge extracting means for differentiating a luminance value of the input image data in a horizontal axis direction.
And a second means for differentiating the luminance value of the input image data in the vertical axis direction
And a differential value between outputs of the first and second differentiating means are calculated.
And, based on the sign of the difference value, the absolute value of the difference value
Means for converting a vertical line component or a horizontal line component of the edge, and binarizing the vertical line component and the horizontal line component of the edge, respectively.
9. The image according to claim 8, further comprising:
Processing equipment. 10. The edge binarizing means converts a vertical line component and a horizontal line component of the edge into the input image data.
Including a normalization means for normalizing by the brightness value of the data
An image processing apparatus according to claim 9. 11. A vertical line component and a horizontal line component of the edge.
Based on the characteristic information of the target object in the input image data.
Extracting means for extracting information Non-linear transformation of the feature information by a predetermined analysis function
Feature information conversion means for performing conversion and converting to intermediate feature information
When, After performing predetermined weighting on the intermediate feature information,
Evaluation data creation that creates evaluation data by adding
Means, A target object in the image data based on the evaluation data;
11. The method according to claim 8, further comprising specifying means for specifying.
An image processing apparatus according to any of the preceding claims.