JP2991122B2 - Communication buffer control system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication buffer control system, and more particularly to a communication buffer control system for transmitting and receiving information between a main transmission communication device and an operating system, which employs a redundant configuration for a control / monitoring unit. It is.

[0002]

2. Description of the Related Art A transmission apparatus sequentially notifies a host operating system of various information on operation and services in the apparatus required for controlling, monitoring, and further maintaining a communication service. ing. This type of notification information to the operating system includes, in addition to failure information and switching information to be notified when an event occurs, performance information for notifying a failure state and an operation state at regular time intervals.

[0003] Further, in the transmission device, a redundant configuration is adopted in each part in the device in order to ensure service safety and maintainability. In particular, in a device used for a dedicated line service, there is a high demand for avoiding service stoppage and for quick service restoration, so that the control / monitoring unit also has a redundant redundant configuration.

In this control / monitoring unit, since the main signal service is not directly affected and a firmware (F / W) is mounted, the standby system is in a standby state or a cold standby state, and a switching factor of the active system is generated. At this time, the system is switched to the standby system, and after the F / W starts up, it operates as the active system.

The communication buffer control method in such a transmission device is used for the purpose of notifying operation / service information in the device to a higher-level operating system.

FIG. 4 is a block diagram showing an example of such a conventional communication buffer control system. The first control / monitoring board 101a includes a first CPU 1a connected via a first CPU bus 12a, a first memory 2a for storing a transmission message as a communication buffer, and a first operating system network 11a. And a first communication driver 3a for performing the above communication control.

[0007] The second control / monitoring panel 101b is similarly connected to a second CPU 1b connected by a second CPU bus 12b.
b, a second memory 2b, and a second communication driver 3b. The operation signal 21 is transmitted to the first control / monitoring panel 1
01a, the first CPU 1a and the second control / monitoring panel 10
1b is exchanged with the second CPU 101b.

Next, the operation will be described. First control
When the monitoring panel 101a is an active system, the first CPU 1a
Notifies the second CPU 1b that the first CPU is mounted on the control / monitoring board 101a of the active system, which is the active system, by the operation signal 21. Second CPU 1b
Receives the operation signal 21 and recognizes that the first control / monitoring panel is the operating system and the second control / monitoring panel is the standby system.

When information to be notified to the operating system is collected and transmitted from the device, the first CPU 1
a, a message is recorded in a first memory 2a used as a communication buffer, and a storage address of a transmission message recorded in the first memory is designated to a first communication driver 3a via a first CPU bus 12a. Issue a message transmission request.

The first communication driver 3a receives the message transmission request, reads the transmission message from the specified address from the first memory 2a, and transmits the message to the first operating system network 11a.

When the first control / monitoring board 101a is an active system, the second control / monitoring board 101b does not perform a message transmission operation and does not access the second memory 2b from the second CPU 1b. .

[0012]

A first problem of the conventional communication buffer control method is that operation / service information in the device required by the operating system may be lost.

The reason is that when information exceeding the communication capacity between the operating systems exceeds the upper limit of the communication buffer, the communication buffer overflows, so that communication becomes impossible and information is lost. The amount of such information increases in proportion to the number of lines accommodated, and increases in proportion to the improvement in control / monitoring accuracy. In particular, in an ATM (asynchronous transfer mode) device, an SDH (Synchronous Transfer Mode) is used.
The number of monitoring targets is much larger than that of a transmission device of the No. Digital Hierarchy), and the ABR
(Available Bit Rate) or UPC
(Usage Parameter Control)
Since a large number of monitoring parameters are required to realize the / shaper function and the like, the amount of information to be notified increases dramatically, and the possibility of overflowing the communication buffer increases.

A second problem is that it is impossible to use the function of the control / monitoring panel of the standby system as the operating system in the conventional control / monitoring panel on which the F / W is mounted.

[0015] The reason is that, in a transmission device having a redundant configuration, the standby system is always subject to maintenance, and it is defined that removal and insertion can always be performed. Affects operations.

An object of the present invention is to provide a communication buffer control system capable of preventing a loss of operation / service information of an operating system in a transmission device.

[0017]

According to the present invention, there is provided a first communication control system having a processor and a communication buffer for temporarily storing information to be transmitted from the processor to a higher order;
A second communication control system having a processor and a communication buffer for temporarily storing information to be transmitted from the processor to the higher order, wherein one of the first and second communication control systems is in a standby state when the other is operating. A communication buffer control system in a transmission communication device having a redundant configuration, wherein each of the first and second communication control systems permits access from a working processor to a communication buffer of a standby system. A communication buffer control system characterized by including control means is obtained.

Each of the access control means includes:
When the own system is the active system, it is characterized in that access from the standby processor to the communication buffer of the own system is prohibited, and each of the access control means is configured such that the own system is the standby system. In this case, access from the standby processor to the communication buffer of the standby system is prohibited.

Further, each of the access control means, when the access address from the processor of the own system exceeds the maximum address of the communication buffer of the own system, converts the address to the address of the communication buffer of the other system while converting the address of the other system. It is characterized by having address conversion means for accessing the communication buffer.

The active processor can access the memory space of the standby communication buffer, effectively doubling the capacity of the active buffer memory to prevent the loss of communication information. .

[0021]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, and the same parts as those in FIG. 4 are denoted by the same reference numerals. The communication buffer control system shown in FIG. 1 is a first system which performs connection control of a CPU bus and a memory bus of a control / monitoring board of its own system and a memory access bus of another control / monitoring board in addition to the conventional system.
Bus control means 4a and second bus control means 4b, and address conversion means 5a and 5b for converting an extended address into an address area of the first memory 2a and the second memory 2b.

The first address conversion means 5a is connected to the second bus control means 4b by a first memory access bus 13a, and the second address conversion means 5b
Is connected to the first bus control means 4a by the memory access bus 13b.

Next, the operation will be described with reference to the flow chart of FIG. 2, assuming that the first control / monitoring panel 101a is an active system. The first CPU 1a detects the operation signal 21 (Step 201), and determines whether or not the second CPU 1b is an operation system (Step 202). First CPU 1a
Does not receive the operation signal 21, the second CPU
1b determines that it is not the active system, the first CPU 1a that has been processing first becomes the active system, outputs the operation signal 21 (step 203), and secures the area of the communication buffer (step 204).

At this time, the first CPU 1a which has become the operation system
Figure 3 shows the address area as a communication buffer secured by
It is shown in (A). That is, the addresses from “xxxx” to “yyyy−1” are areas of the first memory 2a mounted on the first control / monitoring panel 101, and “yy”
The area from “yy” to “zzz” is an area of the second memory 2b mounted on the second control / monitoring panel 101b to be secured as an extended communication buffer area.

After securing the communication buffer area in step 204, the first CPU 1a outputs a first bus control signal 22a to the first bus control means 4a, and outputs the first bus control signal 22a.
is connected to the memory bus 14a, and the memory access bus 13b is disconnected (step 205). First
CPU 1a performs a regular process after the bus control (step 206).

In the second CPU 1b, step 2
02, if the operation signal has been received, the first C
PU1a recognizes that it is the active system, and as shown in the memory map of FIG. 3B, the address “xxxx” to “zzz”
All communication buffer areas up to z ″ are released (step 211).

After releasing the communication buffer area, the second CPU 1
b is the second bus control means 4b according to the bus control signal 22b.
Connect the first memory access bus 13a from the first address conversion means 5a to the second memory bus 14b connected to the second memory 2b, and disconnect the second CPU bus 12b ( Step 212). Second CPU 1
b enters a standby state after the bus control (step 213).

Next, the normal processing of the first CPU 1a will be described. When transmitting operation / service information to the operating system, the first CPU 1a uses the transmission message as a communication buffer via the first CPU bus 12a, the first CPU bus control means 4a, and the first memory bus 14a. A message transmission request specifying a transmission message storage address is issued to the first communication driver 3a via the first CPU bus 12a.

When the operation / service information in the apparatus for notifying the operating system exceeds the capacity of the first memory 2a which is a communication buffer, the first CPU 1a returns to the state shown in FIG. The extended address of the communication buffer, that is, the second memory 2b is accessed. Therefore, the first address conversion means 5a converts the extension address into an address of the second memory 2b (an address exceeding "yyyy-1", an address in "yyyy" to "zzzz"), and Output to the memory access bus 13a.

Since the first memory access bus 13a and the second memory access bus 14b are connected to each other, the second bus control means 4b converts the extension address into an area converted to the address of the second memory 2b. The transmission message is recorded, and the first CP is transmitted to the first communication driver 3a.
A message transmission request specifying a storage address of a transmission message is issued via the U bus 12a.

When receiving the message transmission request, the first communication driver 3a specifies the address where the transmission message is stored, and performs the reading process. If the transmission message is stored in the first memory 2a, the first C
Data is read from the memory 2a via the PU bus 12a, the first bus control means 4a, and the first memory bus 14a. Also, the second
Is stored in the first CPU bus 12a, the first address conversion means 5a, the first memory access bus 13a, the second bus control means 4b, and the second memory bus 14b. Read out the transmission message from the memory 2b.

After reading the transmission message, the message is transmitted to the first operating system interface 11a.

As for each address of the first and second memories 2a and 2b, the address of the memory 2a is changed to "xxx".
If "x" to "yyy-1" and the addresses of the memory 2b are "yyy" to "zzz", the address conversion means 5a and 5b in FIG. 1 are unnecessary (address conversion is unnecessary).
And direct access to each other's memory address space is possible.

[0035]

As described above, according to the present invention, it is possible to access the standby memory from the active CPU and use the accessible memory area as a communication buffer. Thereby, even when transmitting operation / service information in a large number of devices in which the communication buffer memory of the own system overflows, it is possible to notify the operating system of up to twice the amount of information without discarding the information. This has the effect.

The F / W mounted on the control / monitoring panel, which is a transmission communication device, requires only knowledge of operation and spare,
It becomes possible to access the memory of the control / monitoring panel of the standby system regardless of the physical mounting position.

Further, since the memory of the standby system is secured as an extension area of the active system, even if the memory becomes abnormal due to the removal or failure of the control / monitoring panel of the standby system, the memory for the standby communication buffer is stored. Only the access becomes difficult, and there is no direct effect on the basic operation of the device, and there is no particular effect on the operation and service.

Further, as the capacity of the communication buffer increases, the amount of information to be notified to the operating system increases, thereby improving the operation and service.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a communication buffer control system according to the present invention.

FIG. 2 is a flowchart showing an operation of a CPU in FIG. 1;

FIG. 3 is a schematic diagram of a memory map in FIG. 1;

FIG. 4 is a block diagram showing an embodiment of a conventional communication buffer control method.

[Explanation of symbols]

101a first control / monitoring panel 101b second control / monitoring panel 1a first CPU 1b second CPU 2a first memory 2b second memory 3a first communication driver 3b second communication driver 4a No. 1 bus control means 4b Second bus control means 5a First address conversion means 5b Second address conversion means 11a First operating system interface 11b Second operating system interface 12a First CPU bus 12b Second CPU bus 13a First memory access bus 13b Second memory access bus 14a First memory bus 14b Second memory bus 21 Operation signal 22a First bus control signal 22b Second bus control signal

Claims (3)

(57) [Claims] 1. A processor and a higher-order processor
Has a communication buffer to temporarily store information to be sent to
A first communication control system; a processor;
Communication having a communication buffer for temporarily storing information
A control system, and when the one of the first and second communication control systems is operating,
In a redundantly configured transmission communication device where the
A communication buffer control system, wherein each of the first and second communication control systems receives an access from a working processor to a standby communication buffer.
A communication backpack with access control means for permitting access
A communication buffer , wherein each of said access control means is configured to prohibit access from a standby processor to a communication buffer of the own system when the own system is an active system. Control system. 2. The system according to claim 1, wherein each of said access control means prohibits a standby processor from accessing a communication buffer of the standby system when the own system is a standby system. communication buffer control system. 3. The access control means, when an access address from a processor of the own system exceeds a maximum address of a communication buffer of the own system, converts the address into a communication buffer of the other system while converting the address of the other system. 3. The communication buffer control system according to claim 1, further comprising address conversion means for accessing the communication buffer.