JP2990087B2 - Digital signal waveform shaping circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a digital signal waveform shaping circuit, and more particularly to a digital signal waveform shaping circuit for a circuit that operates using digital signals.

[0002]

2. Description of the Related Art The waveform of a digital signal is distorted due to the influence of an induced noise in a circuit or a reflected wave generated due to a mismatch between a terminating resistor and a signal line impedance. This distortion usually occurs around a threshold of a rising edge of a waveform. In this case, a pulse is generated digitally immediately before the normal waveform, and a circuit using the rising edge of the digital signal may malfunction.

Conventionally, in this type of digital signal waveform shaping circuit, a digital signal is input to a filter (composed of an integrating circuit and a Schmitt inverter) to shape a pulse, and a one-shot multivibrator is used to reduce the waveform masking time. The pulse was shaped by producing.

[0004]

In the digital signal waveform shaping circuit using the above-mentioned prior art, an integrating circuit (generally configured using a capacitor and a resistor as lumped constants) is provided with an allowable tolerance of the capacitance value of a used component. However, it is not possible to realize a highly accurate waveform masking time due to an allowable error of the resistance value. Further, there are disadvantages that the waveform is delayed and required data cannot be obtained.

Also, since the one-shot multivibrator uses a capacitor and a resistor similarly to the integration circuit, the waveform masking time varies depending on the tolerance and temperature coefficient inherent to the parts, so that a highly accurate waveform masking time can be obtained. There are no drawbacks.

[Object of the Invention] An object of the present invention is to provide a circuit using a digital signal waveform, even if a pulse is generated immediately before the digital signal waveform due to induced noise or reflected waves.
An object of the present invention is to provide a digital signal waveform shaping circuit capable of shaping a digital signal waveform without errors and delays.

[0007]

A digital signal waveform shaping circuit according to the present invention converts a digital signal (hereinafter, referred to as a digital signal) having a plurality of pulses unnecessary at rising edges due to the influence of induced noise and reflected waves. If entered,
A flip-flop circuit (hereinafter, referred to as an FF circuit) that latches a first rising edge of the pulse to output a positive signal and a negative signal, and a counter that counts an arbitrary time using the negative signal output from the FF circuit as an input When,
An EX-NOR gate to which an output signal from the counter and a negative signal from the FF circuit are input;
It has an OR gate that receives an output signal of the OR gate and the digital signal, and a clock oscillator that supplies a clock signal to the FF circuit and the counter.

The FF circuit has fine rising edge capture means capable of receiving the clock signal as input and latching a pulse of the digital signal at a rising edge thereof.

In the FF circuit, when the potential of the pulse of the digital signal once becomes a high level (potential higher than a threshold), the counter starts counting,
The time until the waveform potential of the digital signal stabilizes at a high level (hereinafter referred to as a waveform masking time) is counted. Until the counting is completed, the waveform potential of the digital signal is at a low level (lower than a threshold). The input has a function to keep the high level even when it changes to.

Further, the counter starts counting the waveform masking time by inputting a negative signal output from the FF circuit, and the counter operates before the digital signal having the pulse falls. It has.

Further, the counter has an output port Qn
A function of controlling the waveform masking time by selecting (n = 1 to 12) is provided.

[Operation] Of the plurality of pulses generated immediately before the rising edge of the input signal, the first pulse is latched by the FF circuit, and once latched, the counter continues counting for a certain period of time. The counter operates so as to always keep the high level even when the input signal due to the pulse changes during the counting, so that the pulse is not picked up, and the falling is equivalent to the falling of the input signal.

With such a circuit configuration, even when there are a plurality of rising pulses, it is possible to shape them.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION

[First Embodiment] An embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 shows a digital signal waveform shaping circuit according to the present invention. In the figure, a digital signal 1 having a pulse input to an input terminal 13 (hereinafter, referred to as a digital signal 1) is input to one end of an OR gate 7. When the digital signal 1 is at a high level (the waveform potential is higher than the threshold) and the counter 9 is counting for an arbitrary time, the signal 2 fed back from the EX-NOR gate 10 is at a high level. The signal 2 output from the EX-NOR gate 10 at the end of the counting becomes low level (the waveform potential is lower than the threshold) and is input to the OR gate 7, respectively. The digital signal 3 output from the OR gate 7 is connected to a D terminal of a flip-flop circuit 8 (hereinafter, referred to as an FF circuit 8).

The FF circuit 8 inputs the digital signal 3 using a high-speed clock from the clock oscillator 11, that is, a clock signal 12 having a rising width smaller than that of the digital signal 3, thereby obtaining the latch signal 4 and the latch signal 4. 5 is output.

Further, when the potential of the pulse of the input digital signal 3 becomes high level (higher than the threshold) once, the counter 9 starts counting, and the waveform potential of the digital signal 3 becomes high level. The input of the digital signal 3 is maintained at a high level even if the potential of the waveform of the digital signal 3 changes to a low level (lower than a threshold) until the end of counting until the time until the waveform is stabilized (waveform masking time). Can be.

As an embodiment of the FF circuit 8, the μPD 7
It can be easily realized by a flip-flop circuit represented by 4HC74 (manufactured by NEC Corporation).

In the counter 9, the input latch signal 5
Is not counted when the output port Qn (n
= 1 to 12 can be controlled by keeping the waveform masking time fixed at the low level and the latch signal 5
Starts counting when it is at a low level, and outputs a high-level count signal 6 from an output port Qn after an arbitrary time.

As an embodiment of the counter 9, μPD7
It can be easily realized by a counter represented by 4HC4040 (manufactured by NEC Corporation).

When the latch signal 5 of the input signal is at the high level, the EX-NOR gate 10 does not start the counter 9 for inputting the same signal.
Remains at the low level, and as a result, the signal 2 is also fed back to the OR gate 7 at the low level. However, when the latch signal 5 is at the low level (when the digital signal 1 has attained the high level at least once) and the counter 9 that inputs the same signal is counting, during the time set by the output port Qn of the counter 9 ( During the waveform masking time), since the output of the counter 9 is at a low level, the signal 2 is kept at a high level during that time and is fed back to the OR gate 7. On the other hand, the signal 2 after the counter 9 finishes counting (completion of the waveform masking time) changes to low level,
Since the signal is fed back to the gate 7, the waveform of the latch signal 4 follows the logic level of the digital signal 1.

The latch signal 4 is output from the output terminal 14 as a waveform after shaping the digital signal 1.

FIG. 2 is a timing chart of the digital signal waveform shaping circuit. When the rising waveform of the digital signal 1 is distorted due to a reflected wave or the like due to propagation in the circuit, it is assumed that two unnecessary pulses are generated immediately after the rising edge of the normal waveform.

If the digital signal 1 is directly input to the FF circuit 8, it is latched by the clock signal 12 having a finer rising width than the digital signal 1, and is synchronized with the clock signal 12 so that the FF circuit 8 is supposed to have the same structure as shown in FIG. Output Q of circuit 8
The waveform becomes the latch signal 10 as (positive) and the latch signal 11 as Q (negative).

However, the FF circuit 8 to which the first rising pulse of the digital signal 1 is inputted sets the latch signal 5 to low level, and inputs the same to the reset terminal of the counter 9 to count the counter 9 (during the waveform masking time). ), A waveform of the count signal 6 is created. While the latch signal 5 is at the low level and the count signal 6 is at the low level, the signal 2 fed back is the EX-NOR gate 10
The input terminal 1
Even if the second pulse of the digital signal 1 (when the input is changed) is input, the masking is performed, and as a result, the output Q (positive) of the FF circuit 8 is a signal obtained by shaping the digital signal 1 It is output as a latch signal 4, and Q (negative) is output as a latch signal 5.

Therefore, while the count signal 6 is counting (during the waveform masking time), even if the digital signal 1 changes, the signal once latched is not changed and continues to be output.

When the counter 9 finishes counting, that is, when the waveform masking time of the signal 2 has passed and the signal has become low level, the digital signal 1 which is the original input signal remains at F
Since the digital signal 1 is latched by the F circuit 8, the high level of the normal waveform of the digital signal 1 is maintained as it is, and then the latch signal 4 falls at the same time as the digital signal 1 falls. Thus, a shaped waveform according to the normal waveform can be obtained at the output terminal 14 as the output signal of the latch signal 4.

In the above embodiment, when the pulse width is narrower than the normal waveform due to noise such as click and impulse mixed in the initial stage of the pulse having a constant pulse width, such noise is removed from the rising edge of the first pulse. A waveform with the deleted pulse width can be obtained. In this case, an accurate pulse waveform can be obtained because it does not include a factor causing an error using a conventional resistor or capacitor.

The waveform masking time is determined by the counter 9
Can be set arbitrarily by the counter value of the above, but the waveform can be accurately shaped by arbitrarily setting it according to the environment in which the waveform shaping circuit for the digital signal is set.

[Second Embodiment] When a digital signal is routed for a long time, a pulse is generated just before the rising edge of the digital signal due to the reflected wave of the digital signal unless matching is achieved by the terminating resistor. In some cases, a digital circuit malfunctions such that an edge is recognized, but two rising edges are erroneously recognized and the digital signal is used to operate.

A waveform shaping circuit that prevents such a malfunction will be described with reference to FIG. The digital signal 21 is input to the monostable multivibrator 20 and the OR gate 30. In the monostable multivibrator 20,
Triggered by the first rising edge, the digital signal 21
Generates a positive pulse having a sufficient time width to rise, and inputs the pulse to the OR gate 30. The OR gate 30 combines the directly input digital signal 21 and the positive pulse signal 22 from the monostable multivibrator 20 to generate 1
Generates two rising edges.

The digital signal waveform shaping circuit 15 receives a digital signal 21 (including a reflected wave of the digital signal itself) and outputs a pulse signal 22 to the monostable multivibrator 20 and the digital signal 21 (reflection of the digital signal itself). And an OR gate 30 which inputs a pulse signal 22 and outputs a digital signal 23.
The monostable multivibrator 20 receives a digital signal 21 having two triggers as shown in FIG. 4 and is triggered at the first rising edge. The monostable multivibrator 20 is a positive pulse having a time width at which the digital signal sufficiently rises, that is, the pulse signal 22 in FIG. (Positive pulse) is output.

The OR gate 30, which inputs the digital signal 21 and the pulse signal 22, outputs the digital signal 23 of FIG. 4 as a waveform obtained by combining the two signals.

With the above configuration, even if the rising waveform of the digital signal is distorted by the reflected wave due to the propagation in the circuit, the waveform is shaped into a normal rising waveform, and a malfunction of a circuit that operates using the digital signal can be prevented.

As described above, in the present embodiment, the waveform can be easily shaped. However, as described above, in the monostable multivibrator 20, the constant pulse width is set by the values of the internal capacitors and resistors. The first embodiment is an example that is more resistant to environmental changes because it may vary depending on environmental conditions such as temperature and humidity.

[0035]

As described above, according to the present invention, the use of the flip-flop circuit or the counter which operates by receiving the high-speed clock causes the influence of the tolerances of the conventional capacitors and resistors. Thus, there is an effect that the waveform masking time can be set with high accuracy, that is, the waveform shaping with high accuracy can be realized.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a digital signal waveform shaping circuit according to the present invention.

FIG. 2 is a timing chart of a digital signal waveform shaping circuit according to the present invention.

FIG. 3 is a digital signal waveform shaping circuit diagram according to the present invention.

FIG. 4 is a timing chart of a digital signal waveform shaping circuit according to the present invention.

[Explanation of symbols]

 Reference Signs List 1 digital signal 2 signal 3 signal 4 latch signal 5 latch signal 6 count signal 7 OR gate 8 flip-flop circuit (μPD74HC74) 9 counter 9 (μPD74HC4040) 10 EX-NOR gate 11 clock oscillator 12 clock signal 13 input terminal 14 output terminal 15 Waveform shaping circuit 20 Monotable multivibrator 30 OR gate

Claims (5)

(57) [Claims] A digital signal having a plurality of pulses (hereinafter, referred to as a digital signal) is input, and one of the pulses is input.
A flip-flop circuit (hereinafter, referred to as an FF circuit) that latches a second rising edge and outputs a positive signal and a negative signal, a counter that counts a predetermined time using the negative signal output from the FF circuit as an input, An EX-NOR gate that receives an output signal from a counter and a negative signal from the FF circuit, an OR gate that receives an output signal of the EX-NOR gate and the digital signal, and an FF circuit and the counter. A digital signal waveform shaping circuit, comprising: a clock oscillator that supplies a clock signal. 2. The digital circuit according to claim 1, wherein the FF circuit receives the clock signal and has a fine rising edge capable of latching a pulse of the digital signal at a rising edge thereof. Signal waveform shaping circuit. 3. The FF circuit, when the potential of the pulse of the digital signal once becomes a high level (potential higher than a threshold), the counter starts counting, and the waveform potential of the digital signal is stabilized at a high level. Until that time, the input keeps a high level even if the potential of the waveform of the digital signal changes to a low level (lower than a threshold) until the counting ends. 2. The digital signal waveform shaping circuit according to claim 1, wherein: 4. The counter starts counting the waveform masking time by inputting a negative signal output from the FF circuit, and ends counting before the digital signal falls. The digital signal waveform shaping circuit according to claim 3. 5. The counter has an output port Qn (n =
4. The digital signal waveform shaping circuit according to claim 3, wherein the waveform masking time can be controlled by selecting one of 1) to 12).