JP2989927B2 - Vector arithmetic unit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vector operation device, and in particular, replaces a vector division instruction for a plurality of dividend elements and a plurality of divisor elements with a product of a dividend element and an approximate reciprocal of the divisor element, and uses a release method every time. The present invention relates to a vector operation device that executes by making a multi-digit partial quotient.

[0002]

2. Description of the Related Art Heretofore, a division method (for example, disclosed in Japanese Patent Application Laid-Open Publication No. H11-157572) which replaces the division with a product of a dividend and an approximate reciprocal of a divisor and creates a partial quotient of many digits each time by using a release method is disclosed. Japanese Patent Application Laid-Open No. 57-041737) discloses a vector arithmetic device which converts a mantissa of a divisor element into a binary normal form, generates an approximate reciprocal of each divisor element from predetermined upper bits of the divisor element, and executes a vector division instruction. Was. The execution of the vector division instruction by such a device has been realized using a circuit as shown in FIG. 2, for example. The example shown here relates to floating-point division.

In FIG. 2, a control circuit 1 is a circuit for controlling the entire vector operation device. Divisor register 3
Is a register for storing the divisor element, and the divisor check circuit 4 is a circuit for determining whether or not the mantissa part of the divisor element stored in the divisor register 3 is in binary normal form.

Next, a binary normalized shift count generation circuit 5 receives the output of the divisor register 3 and generates a left shift count necessary for converting the mantissa part of the divisor element into a binary normal form. The binary normalized shift count register 7 is a register that stores the output of the binary normalized shift count generation circuit 5. Further, the binary normalization shifter 6 shifts the output of the divisor register 3 to the left in accordance with the output of the binary normalization shift count generation circuit 5 to make it into a binary normal form.

Further, the divisor selector 2 is a selector for selecting the divisor given first or the output of the binary normalization shifter 6 when generating the approximate reciprocal. An approximate reciprocal of the mantissa of the divisor element stored in the divisor register 15 is generated from the bit.

The division circuit 9 determines whether or not the following relationship is established between the dividend element and the divisor element: | mantissa of the dividend element | <| mantissa of the divisor element | If not, the mantissa of the dividend element is right-shifted so as to satisfy the expression (1) to correct the exponent. A similar left shift is performed on the mantissa of the element to correct it. Further, the calculation is performed using the dividend element obtained by these corrections and the approximate reciprocal of the divisor element which is the output of the approximate reciprocal generation circuit 8. The vector division instruction is executed as follows using the circuit of FIG.

Step 1 The divisor element is stored in the divisor register 3 via the divisor selector 2. Step 2 The divisor check circuit 4 determines whether the mantissa of the output of the divisor register 3 is in binary normal form, and notifies the control circuit 1. Step 3 A shift count is generated by the binary normalized shift count generation circuit 5 from the output of the divisor register 3 and stored in the binary normalized shift count register 7. Step 4 If the divisor check circuit 4 determines that the mantissa of the output of the divisor register 3 is in binary normal form, step 6 is executed. If it is determined that it is not in the binary normal form, step 5 is executed. Step 5 The mantissa of the divisor element, which is the output of the divisor register 3, is calculated as 2 from the output of the binary normalized shift count generation circuit 5.
The result is stored in the divisor register 3 via the divisor selector 2 and the step 6 is executed. Step 6 The approximate reciprocal of the mantissa of the divisor element is generated using the approximate reciprocal generation circuit 8 from the upper predetermined bits of the mantissa of the divisor element which is the output of the divisor register 3. Step 7 The division circuit 9 compares the absolute values of the mantissa of the dividend element and the mantissa of the divisor element. If the absolute value of the mantissa of the dividend element is larger, the right-hand operation is performed until the mantissa of the dividend element becomes smaller. shift. Thereafter, if step 5 is executed, the same amount of left shift is performed on the mantissa of the dividend element using the output of the binary normalized shift count register 7. Step 8 The mantissa part of the dividend element and the approximate reciprocal generation circuit 8 corrected by the execution of step 7 in the division circuit 9
And the approximate reciprocal of the mantissa of the divisor element, which is the output of.

According to the above-described conventional vector operation device, when the divisor element is not in the binary normal form at the time of executing the vector division instruction, the divisor element is once converted into the binary normal form, and then the divisor element is further processed. An operation of generating an approximate reciprocal from the upper predetermined bits is executed for each element. However, in an actual program, the divisor element is often a constant (the inter-element distance is zero). For example,
The program shown in FIG. 3 is for a case where the same division is repeated ten times, and the divisor element C is a constant.

In such a case, the approximate reciprocal of the divisor element is 1
If it is created once, it can be used every time thereafter, but since the approximate reciprocal is generated for each divisor element, there is a disadvantage that a large amount of wasteful execution time is consumed.

[0010]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional disadvantages, and an object of the present invention is to improve the performance of a vector division instruction when a divisor element is a constant by adding a small amount of hardware. It is.

[0011]

A vector operation device according to the present invention is a vector operation device which receives a plurality of divisor elements and a divisor element as inputs and sequentially divides the divisor element by the plurality of divisor elements, wherein the approximate reciprocal of the divisor element is provided. And a register for holding the generated approximate reciprocal, and when the inter-element distance of each of the plurality of divisor elements is zero, the approximate reciprocal held in the register is transmitted. There and having a selector for sending an approximate reciprocal generated by the generating circuit when not zero, and a divide circuit for performing an operation with approximate reciprocal sent from the selector by said dividend element.

[0012]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of an embodiment of a vector operation device according to the present invention, and portions equivalent to those in FIG. 2 are denoted by the same reference numerals. In the figure, the arithmetic unit of the present embodiment has a divisor-element distance determination circuit 1 in the configuration of FIG.
0, an approximate reciprocal register 11 and an approximate reciprocal selector 12 are added.

The divisor-distance-element distance determination circuit 10 is a circuit that determines the inter-element distance of the mantissa of the divisor element from the instruction word and detects whether the mantissa of the divisor element is a constant. The approximate reciprocal register 11 is a register for holding the output of the approximate reciprocal generation circuit 8. The approximate reciprocal selector 12
This is a selector that selectively sends out the output of the approximate reciprocal generation circuit 8 and the output of the approximate reciprocal register 11.

In the apparatus of this embodiment, by adding the above hardware, when the divisor is a constant, that is, when the distance between the elements is zero, only one approximation reciprocal is created, and thereafter, the generation of the approximation reciprocal becomes unnecessary. I have. That is, the execution of the vector division instruction is performed as follows using the arithmetic unit shown in FIG.

(1) First, the inter-divisor element distance determination circuit 10 determines whether or not the inter-element distance of the mantissa part of the divisor element is zero based on the instruction word, and notifies the control circuit 1.

(2) In the case of the first element Step 1 The divisor register 3 stores the mantissa of the divisor element via the divisor selector 2. Step 2 The divisor check circuit 4 determines whether the mantissa of the output of the divisor register 3 is in binary normal form, and notifies the control circuit 1. Step 3 A shift count is generated by the binary normalized shift count generation circuit 5 from the output of the divisor register 3 and stored in the binary normalized shift count register 7. Step 4 If the divisor check circuit 4 determines that the mantissa of the output of the divisor register 3 is in binary normal form, step 6 is executed. If it is determined that it is not in the binary normal form, step 5 is executed. Step 5 The mantissa of the divisor element, which is the output of the divisor register 3, is calculated as 2 from the output of the binary normalized shift count generation circuit 5.
The result is stored in the divisor register 3 again via the divisor selector 2 and the step 6 is executed. Step 6 The approximate reciprocal of the mantissa of the divisor element is generated using the approximate reciprocal generation circuit 8 from the upper predetermined bits of the mantissa of the divisor element, which is the output of the divisor register 3.
1 is stored. Step 7 The division circuit 9 compares the absolute value of the mantissa of the dividend element and the absolute value of the mantissa of the divisor element. shift. Thereafter, when step 5 is executed, the mantissa of the dividend element is also set to 2
The same amount of left shift is performed using the output of the hexadecimal normalized shift count register 7. Step 8 The mantissa part of the dividend element and the approximate reciprocal selector 1 corrected by the execution of step 7 in the division circuit 9
An operation is performed on the output of 2 with the approximate reciprocal of the mantissa part of the divisor element.

(3) In the case of the second and subsequent elements Step 1 If it is determined that the inter-element distance of the mantissa part of the divisor element is not zero by executing the above-mentioned (1), the above-mentioned (2) Execute in the same way as for the first element. If it is determined that the inter-element distance is zero, step 2 and subsequent steps are executed. Step 2 The division circuit 9 compares the absolute value of the mantissa of the dividend element and the absolute value of the mantissa of the divisor element. If the absolute value of the mantissa of the dividend element is larger, the right side is operated until the mantissa of the dividend element becomes smaller. shift. Also, if the mantissa of the divisor element is converted to the binary normal form by executing step 5 of the above (2) on the first element, the mantissa of the second and subsequent dividend elements is also set to 2 The same amount of left shift is performed using the output of the hexadecimal normalized shift count register 7. Step 3 Divide the mantissa of the dividend element corrected by the execution of the step 1 and the approximate reciprocal of the mantissa of the divisor element stored in the approximate reciprocal register 11 by the execution of the step 6 of (2) via the approximate reciprocal selector 12. 9 and execute the operation.

As described above, it can be understood that the execution of the vector division instruction by the arithmetic unit of this embodiment can shorten the instruction execution time and improve the performance when the mantissa of the divisor element is a constant.

[0020]

As described above, according to the present invention, when the divisor element is a constant, the operation is performed by using the approximate reciprocal held in the register, so that the operation can be performed only by adding a small amount of hardware. There is an effect that performance can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an arithmetic unit according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a conventional arithmetic device.

FIG. 3 is an example of a program in which a divisor element is a constant.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 control circuit 2 divisor selector 3 divisor register 4 divisor check circuit 5 binary normalized shift count generation circuit 6 binary normalized shifter 7 binary normalized shift count register 8 approximate reciprocal generation circuit 9 division circuit 10 judgment of distance between divisor elements Circuit 11 Approximate reciprocal register 12 Approximate reciprocal selector

Claims (1)

(57) [Claims] 1. A vector operation device which receives a plurality of divisor elements and a divisor element as inputs and sequentially divides the divisor element by the plurality of divisor elements, and a generation circuit that generates an approximate reciprocal of the divisor element. A register that holds the generated approximate reciprocal, and sends the approximate reciprocal held in the register when the inter-element distance of each of the plurality of divisor elements is zero, and the generation circuit when the inter-element distance is not zero. a selector for sending the generated approximated reciprocal, vector operation unit, characterized in that it comprises a divider circuit for performing an operation with approximate reciprocal sent from the selector by said dividend element.