JP2988144B2 - ECL level output buffer circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit comprising a CMOS circuit, and more particularly to an ECL level output buffer circuit.

[0002]

2. Description of the Related Art In a conventional ECL level output buffer,
To obtain an output level that matches the existing ECL level,
Although the CMOS level is level-shifted and output,
Since the basic configuration is different between the OSFET and the bipolar transistor, it is difficult to obtain an accurate ECL level due to temperature characteristics and the like, and it is not suitable for high-speed operation at an ECL level with a narrow signal amplitude.

[0003] This temperature characteristic will be described. MOSF
When the drain current is _ID when the ET is in the conductive state, _ID = β / 2 · (V _GS −V _T ) ² . Here, V _{GS is} a potential between the gate and the source of the MOSFET, and V _T is a threshold potential of the MOSFET. Here, the relationship is expressed as β = μ · C _OX · (W / L). C _OX : MOSFET gate oxide film capacity, L: MOSFET gate length, W:
This is the gate width of the MOSFET. Μ is the carrier mobility, which has a negative temperature characteristic. That is, in the MOSFET structure, the output level has a negative temperature characteristic.

On the other hand, in the case of a bi-port transistor, when the potential difference between the emitter and the collector is V _CC when grounded by an emitter follower which is a general ECL output buffer circuit configuration, the output voltage V ₀ becomes has the relationship shown by _{V 0 = V CC -R C I} E · β / (1 + β). R _C : collector resistance,
I _E : emitter current, β: current amplification factor. I _B is dependent on the base resistance, also of the bipolar transistor β,
R _C all have positive temperature characteristics. As a result, the output buffer composed of MOSFETs has negative temperature characteristics, and the output buffer composed of bipolar transistors has temperature characteristics opposite to positive.

[0005]

When the output stage is of the open drain type in the MOSFET circuit, the drain current _ID of the FET used for the open drain is given by _ID = β / 2 · (V _GS −V _T ) 2, and β is also proportional to a coefficient of carrier mobility μ, which generally has a negative temperature characteristic. V _GS : source
Gate-to-gate potential difference, V _T : threshold voltage. That is,
The drain current _{ID of the} FET has a negative temperature characteristic. The output voltage of the open drain is also proportional to the drain current, so that the output voltage also shows a negative temperature characteristic. This is contrary to the fact that a bipolar transistor that generally constitutes an ECL level circuit has a positive temperature characteristic of the base-emitter voltage V _BE , and a strict ECL level transmission system requires a CMOS output buffer. It means that it doesn't fit.

For a signal having a small amplitude such as an ECL level, an accurate output level is required in consideration of noise and a voltage drop in a transmission system. Further, a differential amplifier is a typical example on the receiving side. A fundamental characteristic of the differential amplifier is that a large difference in delay time occurs when the amplitude of an input signal decreases. Conversely, when the amplitude increases, the time required for the bipolar transistor itself to become conductive or non-conductive becomes longer.
In other words, high-speed operation at the ECL level requires an accurate level including temperature characteristics, but has a problem that it is difficult to obtain a completely compatible level. SUMMARY OF THE INVENTION An object of the present invention is to provide an ECL output buffer circuit capable of obtaining a high-precision output level that matches an ECL level.

[0007]

According to the present invention, there is provided a first constant voltage power supply capable of obtaining a high level potential of an ECL level;
A second constant-voltage power supply capable of obtaining an L-level low-level potential; switch means interposed between the first and second constant-voltage power supplies and the power supply terminal ; And a buffer for selectively operating according to the first and second input terminals.
The output voltage of the constant voltage power supply or the second constant voltage power supply
Comparing means for inputting to another input terminal via gate means.
The first constant voltage power supply provided by the switch means.
Alternatively, when the second constant voltage power supply is selected,
The gate means is turned on and according to the result of comparison by the comparing means.
The first constant voltage power supply or the second constant voltage power supply
Is changed.

[0008]

Next, the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram of a first embodiment of the present invention. In FIG. 1, the ECL buffer 1 has an input terminal 11 and an inverted input terminal 12, and has a forward output terminal 13 and a reverse output terminal 14. The constant voltage power supply circuit 2 can output the same potential as the high level of the ready-made ECL level.
Can output the same potential as the low level of the ready-made ECL level. Each of the constant voltage power supply circuits 2 and 3 has the same output terminal 15. The forward output terminal 13 of the ECL buffer 1 is connected to the gate of the switching gate 4, and the reverse output terminal 1
4 is connected to the gate of the switching gate 5. The source / drain of the switching gate 4 is connected between the high-potential-side power supply terminal 16 and the constant-voltage power supply 2, and the source / drain of the switching gate 5 is connected to the high-potential-side power supply terminal 16
And the constant voltage power supply 3. The low potential side power supply terminal 17 is commonly connected to the ECL buffer 1, the constant voltage power supplies 2 and 3, respectively.

Next, the operation will be described. The ECL buffer 1 controls the switching gate 5 at the inverted output 14 and the forward output 1 according to the signals at the input terminal 11 and the inverted input terminal 12.
At 3, the switching gate 4 is operated. This allows
The two switching gates 4 and 5 are operated complementarily, so that the high-level constant voltage power supply 2 and the low-level constant voltage power supply 3 of the ECL level do not operate at the same time, and are output from the output terminal 15. Either the high level or the low level of the ECL level can be output by control by the input signal.

FIG. 2 is a block diagram showing a second embodiment of the present invention, and the same parts as those in FIG. 1 are denoted by the same reference numerals. In this embodiment, a reference ECL level input terminal 18 is provided, a voltage comparator 6 for comparing with a reference ECL level input to this terminal 18 is provided, and its output is used as a power supply for the constant voltage power supplies 2 and 3. Further, a switching gate 7 controlled by the output of the forward output terminal 13 of the ECL buffer 1 is provided.
And the other input terminal of the voltage comparator 6.

According to this circuit, the voltage comparator 6
Is a ready-made ECL level input from the input terminal 18,
The output output from the output terminal 15 is input via the switching gate 7, and these are compared. Then, when the output level falls below the ready-made ECL level reference, the output level from the voltage comparator 6 rises, and conversely, when the output level rises above the reference, the output level falls. This makes it possible to change the voltage of the power supply to be supplied to the constant voltage power supplies 2 and 3 and to keep the output level constant at all times while matching with the ready-made ECL level. Therefore, even if the output accuracy of the constant voltage power supply cannot be increased, there is an advantage that the ready-made ECL level can be precisely maintained.

[0012]

According to the embodiments described above , the present invention is the second embodiment.
By adopting the second embodiment, the first constant voltage power supply for obtaining the ECL level high level potential and the second constant voltage power supply for obtaining the low level potential are selectively operated by the switch means, respectively. Since the output level is configured to be output from these constant voltage power supplies, it is always possible to use a ready-made ECL.
This has the effect that an extremely accurate output level that matches the level can be obtained. The comparison means is based on the standard
The voltage is compared with the outputs of the first and second constant voltage power supplies, and
To the first and second constant voltage power supplies according to the comparison result of
In order to change the power supply voltage, a reference voltage, for example,
Keep the output level constant while measuring consistency with the ECL level
It is possible to keep the time constant.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a first embodiment of an ECL level buffer circuit according to the present invention.

FIG. 2 is a circuit diagram of a second embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Buffer 2 ECL level high level constant voltage power supply 3 ECL level low level constant voltage power supply 4,5 Switching gate 11 Input terminal 12 Inverting input terminal 15 Output terminal 16 High potential side power supply terminal 17 Low potential type power supply terminal

Claims (1)

(57) [Claims] A first constant-voltage power supply for obtaining an ECL-level high-level potential; a second constant-voltage power supply for obtaining an ECL-level low-level potential; a first and a second constant-voltage power supply; Switch means interposed between the constant voltage power supply and the power supply terminal , a buffer for selectively operating these switch means in accordance with an input signal, and a buffer connected to one input terminal.
A reference voltage, and the first constant voltage power supply or the
The output voltage of the constant voltage power supply 2 is input to another input via the gate means.
Comparing means for inputting to the input end, wherein the switch means
The first constant voltage power supply or the second constant voltage
When the power supply is selected, the gate means conducts and the
The first constant-voltage power supply is also switched according to the comparison result of the comparison means.
An ECL level output buffer circuit, wherein the voltage of the second constant voltage power supply is changed .