JP2987144B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device,
In particular, the present invention relates to a large-capacity semiconductor memory device composed of fine elements.

[0002]

2. Description of the Related Art In recent years, the capacity of DRAM has been increasing four times in three years. Due to this increase in storage capacity, the storage capacity of DRAM is currently 16M at the market level.
Bits are about to peak in supply, and 64 Mbits are appearing on the market.
At the research and development level, 256 Mbits to 1G
The stage has come to the point where bit DRAMs are developed.

[0003]

Even if the DRAM has a large capacity, a test for determining whether or not the DRAM is good is important.

When testing a large-capacity DRAM,
The following problems occur.

Shortening of test mode time When the DRAM has a large storage capacity, the test mode time increases as the storage capacity increases. Therefore, it is required to reduce the test mode time.

Improvement of Test Accuracy As a DRAM test, for example, a parallel test has been devised (see “92.9 Hitachi IC Memory Data Book P.6”).
39 Built-in 16-bit parallel test function "and" Parallel test technology suitable for ultra-large capacity memory "Matsumura et al. ICD87-7
5pp.41-46 "and" A45ns64Mb DRAM wit
ha Merged Match-line Test Architecture Shige
ru, Mori., et al., 1991 IEEE ISSCC pp.
110-111 ").

In the parallel test, for example, the same data is written to a plurality of memory cells connected to the same word line of a DRAM, and whether or not all values output from a plurality of bit lines corresponding to the plurality of memory cells are the same. To test. An EXOR circuit is conceivable as a circuit for performing the test, and is obtained by passing values output from a plurality of bit lines through the EXOR circuit. Therefore, even if "1" is written to a plurality of memory cells connected to the same word line, if all "0" are output, the DRAM is determined to be non-defective.

The above-described parallel test can be used as a screening test, but cannot be said to be a highly accurate test.

The present invention has been made in consideration of the above problems, and has as its object to reduce the test mode time of a semiconductor memory device and further improve the test accuracy.

[0010]

A semiconductor memory device according to the present invention comprises a memory block having a plurality of memory cells and a test pattern generating circuit for generating at least one test pattern for testing the memory block. A semiconductor memory device provided on a chip, wherein a width of a first bus line connecting the memory block and the test pattern generation circuit is equal to a width of a second bus line connecting the outside of the semiconductor memory device and the memory block. Greater than the width, thereby achieving the above objectives.

The present invention is a method for writing a test pattern generated by a test pattern generation circuit on a one-chip to a memory block when a test is performed on the memory block on the one-chip. Is larger than the width of the second bus line. Therefore, using the first bus line is a method of writing a test pattern input from outside of one chip into a memory block, that is, using the second bus line to write the test pattern. The test pattern can be written to the memory block faster than writing.

The test pattern generation circuit has a storage unit for storing a plurality of test patterns, and one of the plurality of test patterns is output according to an address signal received by the test pattern generation circuit. Is also good.

A plurality of test patterns are recorded in the storage section, and the test pattern generation circuit can output different test patterns according to the address signal. Therefore, many tests can be performed on the memory block.

The semiconductor memory device may include a comparator for comparing a test pattern read from the memory block with a test pattern generated by the test pattern generation circuit.

The test pattern generated by the test pattern generation circuit is written to the memory block, and thereafter, the test pattern stored in the memory block is read. The comparator compares the test pattern read from the memory block with the test pattern generated by the test pattern generation circuit. Therefore, it is accurately detected whether or not a plurality of memory cells in the memory block are normal.

A switch may be provided for outputting the test pattern generated by the test pattern generation circuit to the memory block or the comparator.

The semiconductor memory device has a plurality of terminals for inputting / outputting data to / from the memory block, and the test pattern generation circuit generates a plurality of terminals in accordance with the address signals input through the plurality of terminals. A test pattern may be generated.

A plurality of terminals are used for inputting / outputting data to / from the memory block, and further used for receiving an address signal required for the test pattern generation circuit to generate a test pattern. For this reason, the number of terminals of the semiconductor memory device can be reduced as compared with a case where a terminal for inputting and outputting data and a terminal for receiving an address signal are separately provided.

The semiconductor memory device includes a plurality of terminals for inputting / outputting data to / from the memory block, and at least one of the plurality of terminals includes a test pattern read from the memory block by the comparator. And a result obtained by comparing the test pattern with the test pattern generated by the test pattern generation circuit.

A plurality of terminals are used for inputting / outputting data to / from the memory block, and at least one of the plurality of terminals is used for outputting a result compared by the comparator. For this reason, the number of terminals can be reduced in the semiconductor memory device as compared with a device having separate terminals for inputting and outputting data and terminals for outputting the result of comparison by the comparator.

[0021]

Embodiments of the present invention will be described below with reference to the accompanying drawings. (Embodiment 1) FIG. 1 is a block diagram showing a semiconductor memory device 100 according to a first embodiment of the present invention.

The semiconductor memory device 100 shown in FIG. 1 has a memory block MB having a plurality of memory cells and a test pattern generation circuit PAM for generating at least one test pattern for testing the memory block MB on one chip. And

The test pattern generation circuit PAM is connected to a memory block MB via a first bus line FBL, and the memory block MB is connected to the outside of the semiconductor memory device 100 via a second bus line SBL. The bus width of the first bus line FBL is wider than the bus width of the second bus line SBL. For example, the bus width of first bus line FBL is 64 bits, and the bus width of second bus line SBL is 8 bits.

The test pattern generated by the test pattern generation circuit PAM is transmitted through the first bus line FBL.
The data is written to the memory block MB. For this reason, the semiconductor memory device 100 writes the test pattern to the memory block MB at a higher speed than when the test pattern is written to the memory block MB using the second bus line SBL having a bus width narrower than the first bus line. be able to.

Test pattern generation circuit PAM generates at least one test pattern for testing memory block MB based on a signal input from outside semiconductor memory device 100, for example, an address signal.

For example, test pattern generation circuit PAM
Has a storage unit (not shown) for storing a plurality of test patterns, and performs at least one test according to a signal (address signal) input from outside the semiconductor memory device 100 via the input line IL. A pattern may be output. A plurality of test patterns are recorded in the storage unit, and the test pattern generation circuit PAM can output different test patterns according to the address signal.

Alternatively, a test pattern generation circuit PAM
Has a pseudo-random number generator (not shown) and has an input line I
At least one test pattern may be generated based on a signal input from outside the semiconductor memory device 100 via L. Since the pseudo random number generator generates a plurality of test patterns, different tests can be performed on the memory block MB.

As described above, the test pattern generation circuit PAM can perform many tests on the memory block MB. Therefore, the accuracy of the test is improved. Note that the line width of the input line IL may be 1 bit or more.

(Embodiment 2) FIG. 2 is a block diagram showing a semiconductor memory device 200 according to a second embodiment.

The semiconductor memory device 200 includes, on one chip, a memory array MA, a test pattern generation circuit PAM for generating at least one test pattern for testing a memory block, and a test pattern read from the memory array MA. And a comparison circuit COMP for comparing the test pattern with the test pattern generated by the test pattern generation circuit PAM.

The test pattern generated by the test pattern generation circuit PAM is stored in the memory array M.
In order to compare the test pattern written in A and read from the memory array MA with the test pattern generated by the test pattern generation circuit PAM (the test pattern written in the memory array MA), the plurality of memories in the memory array MA are compared. It is correctly detected whether the cell is normal.

The semiconductor memory device 200 includes a switching circuit PS
W, and the switching circuit PSW can output the test pattern generated by the test pattern generation circuit PAM to the memory array MA or the comparison circuit COMP.

Hereinafter, the detailed configuration of the semiconductor memory device 200 will be described.

The semiconductor memory device 200 has a memory array M
Address input circuit A for inputting an address signal to A
DB, a data input / output circuit I / O for inputting / outputting data to / from the memory array MA, a timing generation circuit TG, an address input circuit RADB for inputting an address signal to the test pattern generation circuit PAM, and a timing generation circuit RTG. Have.

The timing generation circuit TG includes a row address strobe signal / RAS, a column address strobe signal / CAS, a test enable signal TE, a write enable signal / WE, and an output enable signal / RAS.
Receive OE. In response to these signals, the timing generation circuit TG controls a control signal TGMA for controlling the timing at which the memory array MA inputs and outputs data, a control signal TGIO for controlling the data input / output circuit I / O, and an address input circuit ADB. Control signal TGAD for controlling writing and reading of data and a control signal T for controlling writing or reading of data.
Generate at least one of the RWs.

The timing generation circuit RTG receives a row address strobe signal / RAS, a column address strobe signal / CAS, a test enable signal TE, and a write enable signal / WE. The timing generation circuit RTG controls a control signal TGPAM for controlling the timing at which the test pattern generation circuit PAM generates a test pattern, a control signal TGRA for controlling the address input circuit RADB, and a comparison circuit COMP according to the signals. To generate at least one of a control signal TGCP, a control signal TGMI, and a control signal TGCPI.

The memory array MA has an internal address bus I
It is connected to the address input circuit ADB via AD. The address input circuit ADB has address terminals A00 to A
10, and the memory array MA receives an address signal input from address terminals A00 to A10.

The memory array MA has an internal data bus MD
Through the data input / output circuit I / O.
The data input / output circuit I / O has a data input / output terminal I / O0.
, And between the data input / output circuit I / O and the outside of the one-chip semiconductor memory device 200.
Data can be input and output. Further, the memory array MA is connected to a comparison circuit COMP via a test pattern output bus TMO.

The pattern generation circuit PAM is connected to an address input circuit RADB via an internal address bus IRAD. The address input circuit RADB has address terminals RA00 to RA07, and the pattern generation circuit PAM receives an address signal input from the address terminals RA00 to RA07. Pattern generation circuit PA
M generates at least one test pattern according to the address signal. The generated test pattern is output to the switching circuit PSW via the internal bus TPD.

The switching circuit PSW is connected to the memory array MA via the internal bus TMI,
Is connected to the comparison circuit COMP via the. The switching circuit PSW receives the control signal TGMI or TGCPI, and according to the control signal TGMI or TGCPI,
The test pattern generated by the pattern generation circuit PAM is
The data is sent to the memory array MA or the comparison circuit COMP.

The comparison circuit COMP compares the test pattern read from the memory array MA with the test pattern generated by the test pattern generation circuit PAM. The comparison result is output from the output terminal TO.

The area TB on one chip is called a test circuit block, and the area MB on the same chip is called a memory block. As the memory block MB, a memory block equivalent to a general semiconductor memory device is used.
The memory block MB includes a memory array MA, an address input circuit ADB, a data input / output circuit I / O, a timing generation circuit TG, and the like. The test circuit block TB includes a test pattern generation circuit PAM, a comparison circuit COMP, and the like.

The operation of semiconductor memory device 200 will be described below.

In the test mode, the test pattern generated by the test pattern generation circuit PAM in the test circuit block TB stores the test pattern in the address indicated by the address signal input through the address terminals A00 to A10 of the address input circuit ADB. Memory array M of block MB
A is written.

Each of the plurality of test patterns is stored in the test pattern generation circuit PAM in correspondence with an address, and an address signal is externally input via the address terminals RA00 to RA07 of the address input circuit RADB. Then, a test pattern corresponding to the address signal is generated.

The switching circuit PSW preferably transfers the generated test pattern to the memory array MA, and then transfers the test pattern to the comparison circuit COMP.

The written test pattern is read from the memory array MA, and the same test pattern as the test pattern written in the memory array MA is generated by the test pattern generation circuit PAM. In addition,
When the switching circuit PSW stores the test pattern, the test pattern generation circuit PAM does not need to generate the same test pattern again.

The test pattern from the memory array MA and the test pattern from the test pattern generation circuit PAM are compared by the comparison circuit COMP, and if the test patterns match, the comparison circuit COMP indicates that the semiconductor storage device 200 is a non-defective product. Output a signal indicating that
A signal indicating that semiconductor memory device 200 is defective is output from output terminal TO.

As described above, in the semiconductor memory device 200, it is possible to input 8-bit data from the data input / output terminals I / O0 to I / O7 to the memory array MA at one time.

It is assumed that these data input / output terminals I / O0
Even though it is possible to input an 8-bit test pattern at a time from .about.I / O7, the number of memory cells that can be tested at one time is eight.

Even if an 8-bit address signal is input from address terminals RA00 to RA07 of address input circuit RADB, test pattern generation circuit PAM is
For example, a 64-bit test pattern can be generated according to an 8-bit address signal. In other words, the number of bits of the test pattern generated by the test pattern generation circuit PAM is larger than the number of bits of data that the memory array MA receives from the data input / output terminal.

Since a 64-bit test pattern is generated, the number of memory cells that can be tested at one time is 64.

The test pattern generation circuit PAM
Since test patterns are selectively generated according to an external address signal, test patterns can be generated in an arbitrary order. For example, when an 8-bit address signal is input, test pattern generation circuit PAM
Is capable of generating a test pattern of 2 ^8.
For this reason, in the semiconductor memory device 200, since there are many types of test patterns and the degree of freedom in the order in which the test patterns are generated increases, a detailed test can be performed.

A specific example of the test pattern generation circuit PAM will be described below with reference to FIGS.

FIG. 3 is a diagram showing a configuration example of the test pattern generation circuit PAM.

Test pattern generation circuit PAM shown in FIG.
Are the word lines WL000 to WL2 arranged in a matrix.
55 having a memory section WL and a row decoder circuit RRDE
C, sense amplifier / output circuits RSA00 to RSA63,
And test pattern output terminals TPD00 to TPD6
3 and so on.

As described above, the test circuit block TB
Since an 8-bit address signal is input from address terminals RA00 to RA07 of test pattern generation circuit P,
The AM can generate 2 ⁸ = 256 types of test patterns. The test pattern generation circuit PAM is 256
It has 256 word lines to generate different types of test patterns.

A memory cell for 64 bits is provided for each word line, and the pattern generation circuit PAM can output a 64-bit test pattern at a time in parallel.

Address terminal R of test circuit block TB
When an 8-bit address signal is input from A00 to RA07, this address signal is applied to the row decoder circuit RRDE.
Input to C. Row decoder circuit RRDEC selects and activates a word line corresponding to the address signal in response to control signal TGPAM from timing generation circuit RTG. Outputs data stored in a memory cell connected to the selected word line. Data output from a memory cell connected to the selected word line is amplified by sense amplifier / output circuits RSA00 to RSA63. Thereafter, the amplified data is output to the switching circuit PSW via the internal bus TPD (output terminals TPD00 to TPD63).

The memory unit WL may be any type of memory, but is preferably a ROM type that can hold data even after the power is turned off.
L is assumed to be a mask ROM type.

When there is a request to rewrite the test pattern stored in the memory unit WL, an EEPROM, an SRAM or the like may be applied as the memory unit WL. In such a case, the EEPROM requires a booster circuit and complicates the data storage process. In the SRAM, when the power is turned off, data cannot be held. EEPROM or S as the memory unit WL
These considerations should be taken into account when applying RAM.

Hereinafter, EEPRO will be used as the memory section WL.
A test pattern generation circuit PAM in a case where M, SRAM, or the like is applied will be described with reference to FIG.

FIG. 4 is a diagram showing a configuration example of a test pattern generation circuit PAM capable of rewriting a test pattern.

Test pattern generation circuit PAM shown in FIG.
Are 64 in the test pattern generation circuit PAM shown in FIG.
It is provided with a bit shift register circuit SR and a write unit WR having a write switch SW. The writing unit WR is located on the same one chip as the semiconductor storage device 200.

The shift register circuit SR stores a 64-bit test pattern serially input in synchronization with the control clock signal CLK. The 64-bit test pattern input serially is input from the input terminal IN.

Thereafter, the write switch SW turns on the shift register circuit SR in response to the write control signal CNT.
Are output in parallel to the memory unit WL. At this time, the row decoder circuit RRDE
C receives an address signal from address terminals RA00-RA07, and responds to a control signal TGPAM from timing generation circuit RTG to select and activate a word line of memory portion WL corresponding to the address signal. The memory cells connected to this word line store the 64-bit test pattern from the shift register circuit SR.

One of 256 word lines is sequentially designated by an 8-bit address input to the row decoder circuit RRDEC, and each time a word line is designated,
The 64-bit test pattern is stored in the shift register circuit SR.
Is entered from By such a method, the memory unit W
L can store 256 types of test patterns.

As described above, the test pattern generation circuit PA
If the test pattern in M can be easily rewritten, the test pattern can be diversified and a highly accurate test can be performed.

When the above-described shift register circuit SR is used, the test pattern is input serially and the input test pattern is output in parallel, so that only one terminal is required for inputting the test pattern. I'm done. When the shift register circuit SR is used, the configuration of the external terminals of the semiconductor memory device 200 does not become complicated.

Note that as long as the test pattern can be serially input to the shift register circuit SR, the test pattern may be written to the shift register circuit SR by any procedure.

Such a test pattern write operation may be performed at any time. When exposing the test mode to the user, the semiconductor memory device 20 having the writing unit WR
A test pattern may be written when a system using a zero chip is initialized. This is because the test on the user side is generally performed when the system is initialized.

FIG. 5 shows the memory section W shown in FIG. 3 or FIG.
FIG. 9 is a diagram showing an example of 256 test patterns stored in L.

The memory section WL shown in FIG. 3 or FIG.
Since it has 56 × 64 memory cells and 256 word lines, 256 × 64 values can be stored. 64 memory cells are connected to one word line.
A bit test pattern is stored.

One circle shown in FIG. 5 corresponds to one memory cell, white circles indicate “L” level, and black circles indicate “H” level. For example, the levels of the memory cells connected to word line WL000 are all “L”, and the levels of the memory cells connected to word line WL065 are all “H”.

The word line WL000 is activated to set “L”
When the test pattern of the level is output from the test pattern generation circuit PAM, and the test pattern is output to the memory array MA via the switching circuit PSW, the address of the memory array MA specified by the address input circuit ADB is changed. If the states are sequentially changed, the states of all the memory cells in the memory array MA can be rewritten to the “L” level.

Similarly, word line WL065 is activated, a test pattern at "H" level is output from test pattern generation circuit PAM, and the test pattern is output to memory array MA via switching circuit PSW. In this state, if the address of the memory array MA specified by the address input circuit ADB is sequentially changed, the state of all the memory cells in the memory array MA can be rewritten to the “H” level.

Such batch erasing and batch writing may be used other than in the test mode.

If 256 test patterns are not enough, the number of word lines may be increased. When increasing the number of word lines, it is necessary to increase the number of bits of the address signal and the number of address terminals.

The configuration of the memory array MA will be described below with reference to FIGS.
This will be described with reference to FIG.

FIG. 6 is a diagram showing a configuration example of the memory array MA.

The memory array MA shown in FIG. 6 includes a memory section MCA, a row decoder circuit RDEC, a column decoder circuit CDEC, a column switch circuit CSW, and data lines DL00 to DL63. In this embodiment,
Although a DRAM is used as the memory unit MCA, a rewritable memory such as SR
AM and EEPROM may be used.

The row decoder circuit RDEC and the column decoder circuit CDEC receive a part of the address signal, and indicate a memory cell of the memory array MA according to the part of the address signal.

The column switch circuit CSW is connected to an internal data bus MD, an internal bus TMI, and a test pattern output bus TMO. Further, the column switch circuit CSW includes a control signal TR for controlling writing or reading of data when testing the memory array MA.
W, receives the timing signal TGMA. Further, the column switch circuit CSW receives a part of the address signal.

FIG. 7 is a diagram showing a part of the memory section MCA of the memory array MA shown in FIG.

The memory section MCA shown in FIG. 7 includes a plurality of memory blocks BLK0, BLK1, a plurality of sense amplifiers S
A, a plurality of read amplifiers RA, a plurality of switches SW, a plurality of data line pairs DL, / DL, a plurality of bit line pairs BL,
/ BL, a plurality of memory cells (not shown), and a plurality of word lines (not shown). A pair of bit lines BL amplified by the selected sense amplifier circuit SA,
The potential difference between / BL is output as one bit.

In memory block BLK0, a plurality of sense amplifiers SA and a plurality of bit line pairs BL and / BL are
For example, it is divided into 64 groups G1 to G64.
One word line (not shown) is activated by the row decoder circuit RDEC shown in FIG. The data of the memory cell connected to the activated word line is read out to the plurality of bit line pairs BL and / BL. The column decoder circuit CDEC shown in FIG. 6 activates one of the plurality of sense amplifiers SA in each of the groups G1 to G64. Note that the column decoder circuit CDEC also determines which switch SW is to be activated based on the address signal. Data passed through the activated sense amplifier SA is transmitted to the activated switch SW and read amplifier RA.
Is output to the column switch circuit CSW via the

FIG. 8 is a diagram showing details of the column switch circuit CSW shown in FIGS. 6 and 7.

The column switch circuit CSW has column switch blocks CSWB0 to CSWB7. The column switch block CSWB has a plurality of switches, for example, a plurality of N-type MOS transistors.

The column switch circuit CSW is connected to the data line D
Data output via L00 to DL63 is output to internal data bus MD or test pattern output bus TMO.

When data output via data lines DL00-DL63 is output to internal data bus MD,
Data output via data lines DL00 to DL63 is thinned out by column switch circuit CSW. That is, the column switch circuit CSW thins out the data output via the data lines DL00 to DL63 based on the address signal. In order to output data to the internal data bus MD, each of the column switch blocks CSWB0 to CSWB according to the address signals IA _n , IA _{n + 1} , IA _{n + 2.}
One of the seven switches S1 is selected. In this case, all the switches S2 and S3 of each of the column switch blocks CSWB0 to CSWB7 are turned off by the timing signal TGMA.

For example, column switch block CSW
In B0, the switch S1 connected to the data line DL00
Is selected, the data output via the data line DL00 is sent to the internal bus MD0.

The column switch circuit CSW is connected to the data line D
When data output through L00 to DL63 is output to the test pattern output bus TMO, all data is output to the test pattern output bus TMO via the stitch S3 of the column switch blocks CSWB0 to CSWB7. In this case, the control signal TRW instructing to read the test pattern and the timing signal TGM
By A, each column switch block CSWB0-C
All the switches S3 of SWB7 are turned on, and each of the column switch blocks CSWB0 to CSWB is controlled by a control signal TRW instructing to read a test pattern.
All switches S2 of B7 are turned off.

Further, column switch circuit CSW outputs data output from internal data bus MD or internal bus TMI to memory portion MCA via a part / all of data lines DL00-DL63.

When data output from internal data bus MD is output to memory section MCA via a part of data lines DL00 to DL63, each column switch block C
One of the switches S1 of SWB0 to CSWB7
One is selected according to the address signals IA _n , IA _{n + 1} , and IA _{n + 2} . In this case, all the switches S2 and S3 of each of the column switch blocks CSWB0 to CSWB7.
Is turned off in response to the timing signal TGMA.

For example, column switch block CSW
In B0, the switch S1 connected to the data line DL00
Is selected, the data output from the internal bus MD0 is sent to the memory unit MCA via the data line DL00.

Data output from internal bus TMI is supplied to memory unit MC via all data lines DL00-DL63.
A, each column switch block CSW
All of the plurality of switches S2 of B0 to CSWB7 are selected. In this case, each of the column switch blocks CSWB0 to CSWB is controlled by a control signal TRW instructing to write a test pattern and a timing signal TGMA.
All switches S2 of B7 are turned on, and all switches S3 of each of the column switch blocks CSWB0 to CSWB7 are turned off by a control signal TRW instructing to write a test pattern.

For example, a column switch block CSW
In B0, the switch S2 connected to the data lines DL00 to DL07 is selected, and the internal buses TMI00 to TMI0 are selected.
7 output data lines DL00-DL0.
7 to the memory unit MCA.

The configuration of the comparison circuit COMP will be described below with reference to FIG.

FIG. 9 is a diagram showing the comparison circuit COMP. The comparison circuit COMP includes 64 exclusive OR circuits E
An X-NOR and one AND circuit AND with 65 inputs are provided.

Each exclusive OR circuit EX-NOR has a 64-bit test pattern read from the memory array MA and a 64-bit test pattern transmitted from the test pattern generation circuit PAM via the output switching circuit PSW. A test pattern is input. Both test patterns are
If even one bit does not match, an “L” level signal is output from the AND circuit AND to the output terminal TO. If both test patterns match for all bits, an “H” level signal is output. The signal is output from the circuit AND to the output terminal TO.

The AND circuit AND is connected to the comparison circuit CO
It is opened and closed in response to the control signal TGCP of the MP. Control signal TGCP is generated by timing generation circuit RTG.

Hereinafter, the semiconductor memory device 200 shown in FIG.
An example of the test mode timing will be described.

FIG. 10 shows the semiconductor memory device 20 shown in FIG.
FIG. 9 is a diagram showing a timing chart of a test mode of 0.

In the test mode, a cycle (write) in which a test pattern is written to the memory array MA, data stored in the memory array MA are read, and the read data is tested by the test pattern generation circuit PAM. This is performed in two cycles of a cycle (comparison) to be compared with the pattern.

In the test mode, the test enable signal TE
It is started in synchronization with the rise of. The present invention is not limited to this, and any signal may be used as long as the semiconductor memory device 200 is in the test mode, and the rising edge of the signal may not be used.

In the test mode, a test pattern is written to memory array MA. Timing generation circuit T
G is the falling of the row address strobe signal / RAS, raises the control signal TGAD, the address input circuit ADB is the rise of the control signal TGAD, fetches the address signal A ₁ to A _n. Address input circuit AD
B converts the address signals A _{1 to An} into the internal address signal IAD.
It may be converted to _{1 ~IAD n.} Address input circuit ADB
Are the address signals A _{1 to An} or the internal address signal IA.
D starts accessing the memory cells of the memory array MA based on _{1 ~IAD n.}

An address signal designating the address of memory array MA is taken in synchronization with control signal TGAD generated by timing generation circuit TG. In the timing chart shown in FIG. 10, the timing generation circuit TG
Is generated in response to a row address strobe signal / RAS, but the control signal TGAD may be generated in response to a column address strobe signal / CAS.

In the test mode, the address of the memory array MA is
Of the test pattern generation circuit PAM.
In order to capture the address indicating the test pattern,
The timing generation circuit TGR has a row address strobe.
The control signal TGRA rises at the fall of the signal / RAS.
increase. Thus, the test pattern address signal R
A₁~ RA_mIs taken into the address input circuit RADB.
You. Address input circuit RADB is provided with address signal RA.₁
~ RA_mTo the internal address signal IRAD₁~ IRAD_mStrange
It may be replaced. Address signal RA₁~ RA_mOr internal
Dress signal IRAD ₁~ IRAD_mTess indicated by
Pattern is read from the test pattern generation circuit PAM
Is done.

Output switching circuit PSW outputs control signal TGMI.
Is at "H" level, the test pattern generation circuit PA
The test pattern from M is transferred to the memory array MA via the internal bus TMI. The memory array MA receives the previous address signals A _{1 to An} or the internal address signals IAD ₁ to IAD ₁ to An.
A memory cell indicated by the IAD _n, and stores the test pattern.

Test pattern write control signal TGM
I indicates that when the test enable signal TE is at the “H” level and the test mode is set, the row address strobe signal / RAS and the write enable signal / WE
Is generated by the timing generation circuit TGR.

The timing generation circuit TG controls the control signal TG at the fall of the row address strobe signal / RAS.
Launch AD. The address input circuit ADB responds to the rise of the control signal TGAD, and outputs the address signals A _{1 to An.}
Take in. The address input circuit ADB may convert the address signals A _{1 to An} into internal address signals IAD _{1 to} IAD _n .

The memory cells of the memory array MA are accessed based on the address signals A _{1 to An} or the internal address signals IAD _{1 to} IAD _n , and the test pattern stored in the memory array MA is read. The test pattern is transferred to the comparison circuit COMP.

On the other hand, timing generation circuit TGR raises control signal TGRA at the fall of row address strobe signal / RAS.

Address input circuit RADB provides control signal T
Address signals RA _{1 to} RA _m in response to the rise of GRA
Take in to. Address input circuit RADB converts address signals RA ₁ -RA _m to internal address signals IRAD ₁ -IRAD.
It may be converted to AD _m . A test pattern indicated by address signals RA _{1 to} RA _m or internal address signals IRAD _{1 to} IRAD _m is used as a test pattern generation circuit PAM.
And is sent to the output switching circuit PSW.

The output switching circuit PSW outputs the control signal TGCP
When I is at “H” level, the test pattern generation circuit P
The test pattern from the AM is transferred to the comparison circuit COMP.

The control signal TGCPI for controlling the timing for comparing the test patterns is the test enable signal T
E is at “H” level and the write enable signal / WE
Is at "H" level, it is generated by the timing generation circuit TGR in response to the fall of the row address strobe signal / RAS.

Since the control signal TGCPI and the above-described control signal TGMI both write and compare test patterns in the test mode, they can be generated by any other method as long as they are performed. No problem.

In response to control signal TGCP, comparison circuit COMP compares a test pattern read from memory array MA with a test pattern output from test pattern generation circuit PAM via output switching circuit PSW. If the two test patterns match, an "H" level signal is output to the output terminal TO. If the two test patterns do not match, an "L" level signal is output to the output terminal TO.
Output to When the level of the output terminal TO is “H”, the semiconductor memory device 200 passes the test, and when the level of the output terminal TO is “L”, the semiconductor memory device 20
0 fails the test.

The semiconductor memory device 200 according to the present embodiment is a one-chip, in which a test pattern is generated, and the generated test pattern is stored in the memory array MA. The test pattern generated by the test pattern generation circuit PAM is compared with the test pattern read from the memory array MA. Therefore, it is accurately detected whether or not a plurality of memory cells of the memory array MA are normal.

A plurality of test patterns corresponding to a plurality of address signals are recorded in the test pattern generation circuit PAM.
Can output different test patterns depending on the address signal. Therefore, many tests can be performed on the memory block.

Embodiment 3 Hereinafter, a semiconductor memory device 300 according to a third embodiment will be described with reference to FIGS. In the semiconductor memory device 300,
The same components as those of the semiconductor memory device 200 of the second embodiment are denoted by the same reference numerals, and the description is basically omitted.

FIG. 11 is a block diagram showing a semiconductor memory device 300 according to the third embodiment.

In the semiconductor memory device 300 of the third embodiment, the test pattern generation circuit P of the semiconductor memory device 200
The address terminals RA00 to RA07 for AM are omitted, and instead, the input / output terminals I / O0 for memory array MA are used.
To I / O7 are shared by the memory array MA and the test pattern generation circuit PAM. Therefore, the configuration of the input / output circuit I / OT of the semiconductor storage device 300 is different from the configuration of the data input / output circuit I / O of the semiconductor storage device 200.

Data input / output terminals I / O0 to I / O7 of semiconductor memory device 200 are not used in the test mode. Therefore, it may be used to input an address signal to the test pattern generation circuit PAM in the test mode. As a result, in the semiconductor memory device 300, an address signal can be input to the test pattern generation circuit PAM without providing the address terminals RA00 to RA07.

FIG. 12 shows the input / output circuit I / O shown in FIG.
FIG.

The input / output circuit I / OT includes an input / output block B
0 to B7. Each of the input / output blocks B0 to B7 includes an input buffer circuit Ib and an output buffer circuit Ib.
o, an inverter circuit INV, and N-type MOS transistors MN1 and MN2.

The input / output circuit I / OT has an input / output control signal T
Controlled by GIO and / or test enable signal TE. During normal operation (other than the test mode), the input / output circuit I / OT operates as a data input / output circuit,
Data is exchanged with the memory array MA via the internal data bus MD. In the test mode, the input / output circuit I /
The OT outputs the received data, that is, the address signal to the address input circuit RADB via the internal bus RAD.

The output buffer Io is controlled by a control signal TGIO. When data is output to memory array MA and when an address signal is output to test pattern generation circuit PAM, output buffer Io
Increases the impedance on the output side of the output buffer Io in response to the control signal TGIO. Therefore, data and address signals do not flow back to the input / output terminals I / O0 to I / O7.

In normal operation, test enable signal T
Since E is at the “L” level, the transistor MN1 is turned on, and in response to the control signal TGIO, for example, data from the memory array MA is transferred to the input / output terminal I / O0. In addition, data is transferred in response to test enable signal TE and control signal TGIO, and vice versa.

In the test mode, test enable signal TE is at "H" level, so that transistor MN2 is turned on, and, for example, an address signal from input terminal I / O0 is transferred to address input circuit RADB.

Note that the circuit configuration and control signal may take any form as long as the above-described operation can be realized.

In the above example, the memory array MA
Alternatively, the input / output terminals I / O0 to I / O7 for the memory array MA are shared by the memory array MA and the test pattern generation circuit PAM because the test pattern generation circuit PAM receives data or address signals. Some of the address terminals A00 to A10 for MA may be shared by the memory array MA and the test pattern generation circuit PAM.

Note that an address signal to be received by the test pattern generation circuit PAM may be input using all of the address terminals A00 to A10 for the memory array MA. In this case, the number of bits of the address for accessing the test pattern generation circuit PAM increases, so that it is possible to further increase the types of test patterns without providing a new terminal.

By sharing the terminal used in the test mode with the terminal used in the normal operation, a new terminal for inputting an address signal to the test pattern generation circuit RAM from outside the one chip is not required.

(Embodiment 4) Hereinafter, a semiconductor memory device 400 according to a fourth embodiment will be described with reference to FIGS. The fourth embodiment aims to reduce the number of terminals of a semiconductor memory device, as in the third embodiment.

In the semiconductor memory device 400, the same components as those of the semiconductor memory device 200 of the second embodiment are denoted by the same reference numerals, and the description is basically omitted.

FIG. 13 is a block diagram showing a semiconductor memory device 400 according to the fourth embodiment.

In the semiconductor memory device 400, the output terminal TO (output terminal of the test result) as in the semiconductor memory device 200
Instead of being provided independently, a terminal of semiconductor memory device 400, for example, input / output terminal I /
One of O0 to I / O7 is shared as output terminal TO.

FIG. 14 shows the semiconductor memory device 4 shown in FIG.
FIG. 2 is a diagram showing an input / output circuit I / OU at 00.

The input / output circuit I / OU includes an input / output block B
B0 to BB7 are provided. For example, it is assumed that the input / output terminal I / O0 of the input / output block BB0 is used as the output terminal TO.

The input / output block BB0 includes an input buffer circuit Ib, an output buffer circuit Io, and an inverter circuit IN
V and N-type MOS transistors MN1 and MN2. Each of the input / output blocks BB1 to BB7 includes an input buffer circuit Ib, an output buffer circuit Io, an inverter circuit INV, and an N-type MOS transistor MN1.

The input / output block BB0, like the input / output block B0 shown in FIG.
Thus, the normal operation and the operation in the test mode are switched.

In the input / output block BB0, when the output buffer Io outputs data to the memory array MA, the output side impedance is increased in response to the control signal TGIO.

In normal operation, test enable signal T
Since E is at the “L” level, the transistor MN1 is turned on, and in response to the control signal TGIO, for example, data from the memory array MA is transferred to the input / output terminal I / O0. Data is transferred in response to the control signal TGIO and vice versa.

In the test mode, since the test enable signal TE is at the “H” level, the transistor MN2 is turned on, and the signal from the comparison circuit COMP is transferred to the input / output terminal I / O0.

This embodiment may be combined with the third embodiment.

By sharing the terminal used in the test mode with the terminal used in the normal operation, there is no need for a new output terminal TO for outputting a signal indicating the result of the test from the comparison circuit COMP.

[0148]

According to the semiconductor memory device of the present invention, the width of the first bus line connecting the memory block and the test pattern generation circuit is larger than the width of the second bus line connecting the outside of the semiconductor memory device and the memory block. . For this reason, in the semiconductor memory device of the present invention, using the first bus line is a method of writing a test pattern input from outside of one chip into the memory block, that is, using the second bus line to write the test pattern. The test pattern can be written to the memory block faster than writing.

Another semiconductor memory device of the present invention has a comparator. The test pattern generated by the test pattern generation circuit is written to the memory block, and thereafter, the test pattern stored in the memory block is read. The comparator compares the test pattern read from the memory block with the test pattern generated by the test pattern generation circuit. Therefore, it is accurately detected whether or not a plurality of memory cells in the memory block are normal.

[Brief description of the drawings]

FIG. 1 is a semiconductor memory device 100 according to a first embodiment;
FIG.

FIG. 2 shows a semiconductor memory device 200 according to a second embodiment;
FIG.

FIG. 3 is a diagram illustrating a configuration example of a test pattern generation circuit PAM.

FIG. 4 is a diagram showing a configuration example of a test pattern generation circuit PAM capable of rewriting a test pattern.

FIG. 5 is a diagram showing an example of 256 test patterns stored in the memory unit WL shown in FIG. 3 or FIG.

FIG. 6 is a diagram illustrating a configuration example of a memory array MA.

FIG. 7 shows a memory section MCA of the memory array MA shown in FIG.
It is a figure which shows a part of.

FIG. 8 shows a column switch circuit CS shown in FIGS. 6 and 7;
FIG. 4 is a diagram showing details of W.

FIG. 9 is a diagram illustrating a comparison circuit COMP.

10 is a diagram showing a timing chart of a test mode of the semiconductor memory device 200 shown in FIG.

FIG. 11 shows a semiconductor memory device 30 according to a third embodiment.
FIG.

12 is a diagram showing an input / output circuit I / OT shown in FIG.

FIG. 13 shows a semiconductor memory device 40 according to a fourth embodiment.
FIG.

14 is a diagram showing an input / output circuit I / OU in the semiconductor memory device 400 shown in FIG.

[Explanation of symbols]

MA memory array ADB address input circuit I / O data input / output circuit TG timing generation circuit PAM test pattern generation circuit RADB address input circuit PSW output switching circuit RTG timing generation circuit COMP comparison circuit / RAS row address strobe signal / CAS column address strobe signal TE test enable signal / WE write enable signal / OE output enable signal A00-A10 Address signal terminal RA00-RA07 Address signal terminal I / O0-I / O7 Data input / output terminal TGIO, TGMA, TGAD, TGRA, TGPA
M, TGMI, TGCPI, TGCP, CMPI Control signal IAD Internal address bus IRAD Internal address bus of pattern generation circuit PAM TMI test pattern input bus TMO test pattern output bus TO output terminal MB memory block TB test circuit block TPD test pattern generation circuit Output MD0-MD7 Data bus

Continuation of the front page (51) Int.Cl. ⁶ identification code FI G11C 11/34 371A (58) Investigated field (Int.Cl. ⁶ , DB name) G11C 29/00 G11C 11/401 G01R 31/28 G01R 31 / 3183

Claims (6)

(57) [Claims] 1. A semiconductor memory device comprising: a memory block having a plurality of memory cells; and a test pattern generation circuit for generating at least one test pattern for testing the memory block on a single chip, A semiconductor memory device wherein a width of a first bus line connecting the memory block and the test pattern generation circuit is larger than a width of a second bus line connecting the outside of the semiconductor memory device and the memory block. 2. The test pattern generation circuit has a storage unit for storing a plurality of test patterns, and one of the plurality of test patterns is output according to an address signal received by the test pattern generation circuit. The semiconductor memory device according to claim 1, wherein: 3. The semiconductor memory device according to claim 1, further comprising a comparator for comparing a test pattern read from the memory block with a test pattern generated by the test pattern generation circuit. Semiconductor storage device. 4. The semiconductor memory device according to claim 3, further comprising a changeover switch capable of outputting a test pattern generated by said test pattern generation circuit to said memory block or said comparator. 5. The semiconductor memory device includes a plurality of terminals for inputting / outputting data to / from the memory block, and the test pattern generation circuit responds to the address signal input through the plurality of terminals. 2. The semiconductor memory device according to claim 1, wherein a plurality of test patterns are generated. 6. The semiconductor memory device includes a plurality of terminals for inputting / outputting data to / from the memory block, and at least one of the plurality of terminals is read by the comparator from the memory block. 4. The semiconductor memory device according to claim 3, wherein a result of comparing a test pattern with a test pattern generated by the test pattern generation circuit is output.