JP2985993B2 - Multiplication circuit - Google Patents

Multiplication circuit

Info

Publication number
JP2985993B2
JP2985993B2 JP4280792A JP28079292A JP2985993B2 JP 2985993 B2 JP2985993 B2 JP 2985993B2 JP 4280792 A JP4280792 A JP 4280792A JP 28079292 A JP28079292 A JP 28079292A JP 2985993 B2 JP2985993 B2 JP 2985993B2
Authority
JP
Japan
Prior art keywords
input
voltage
timer
output
time
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP4280792A
Other languages
Japanese (ja)
Other versions
JPH06111036A (en
Inventor
国梁 寿
維康 楊
ウィワット・ウォンワラウィパット
直 高取
山本　　誠
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TAKATORI IKUEIKAI KK
Consejo Superior de Investigaciones Cientificas CSIC
Original Assignee
TAKATORI IKUEIKAI KK
Consejo Superior de Investigaciones Cientificas CSIC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by TAKATORI IKUEIKAI KK, Consejo Superior de Investigaciones Cientificas CSIC filed Critical TAKATORI IKUEIKAI KK
Priority to JP4280792A priority Critical patent/JP2985993B2/en
Priority to US07/964,157 priority patent/US5343419A/en
Priority to KR1019930018186A priority patent/KR940008266A/en
Publication of JPH06111036A publication Critical patent/JPH06111036A/en
Application granted granted Critical
Publication of JP2985993B2 publication Critical patent/JP2985993B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【産業上の利用分野】この発明は乗算回路に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplication circuit.

【０００２】[0002]

【従来技術】従来、デジタル型の乗算回路は大規模とな
り、またアナログ型の乗算回路はその計算精度が低かっ
た。2. Description of the Related Art Conventionally, digital multiplication circuits have become large-scale, and analog multiplication circuits have low calculation accuracy.

【０００３】[0003]

【発明が解決しようとする課題】この発明はこのような
従来の問題点を解消すべく創案されたもので、小規模か
つ高精度の乗算が可能な乗算回路を提供することを目的
とする。SUMMARY OF THE INVENTION The present invention has been made to solve such a conventional problem, and an object of the present invention is to provide a multiplication circuit capable of performing small-scale and high-precision multiplication.

【０００４】[0004]

【課題を解決する手段】この発明に係る乗算回路は、時
間の指数関数で出力が変化するとともに、基準電圧と入
力電圧との比に対応した時間だけこの指数関数的変化を
生じさせる第１、第２タイマを用いて第１、第２入力電
圧に基づくカウントを行い、両タイマの総動作時間を第
３タイマで算出して乗算結果を出力するものである。According to a first aspect of the present invention, there is provided a multiplying circuit in which an output changes in an exponential function of time and an exponential change occurs for a time corresponding to a ratio between a reference voltage and an input voltage. The second timer counts based on the first and second input voltages, calculates the total operation time of both timers with the third timer, and outputs the multiplication result.

【０００５】[0005]

【実施例】次にこの発明に係る乗算回路の１実施例を図
面に基づいて説明する。図１において、乗算回路は第１
〜第３のタイマＴ1〜Ｔ3を有し、タイマＴ1には入力電
圧ｘが、タイマＴ2には入力電圧ｙが入力されている。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of the multiplying circuit according to the present invention will be described with reference to the drawings. In FIG. 1, the multiplication circuit is the first
Have to third timer T 1 through T 3, the timer T 1 input voltage x is in the timer T 2 input voltage y is inputted.

【０００６】タイマＴ1は直列のコンデサＣ1、Ｃ2の中
間を高抵抗Ｒ1を介して接地してなり、コンデサＣ1側に
ステップ状の開始トリガＳＴが入力され、一方Ｃ2側
に、コンデンサＣ3を介して入力電圧ｘが接続されてい
る。そしてＣ2、Ｃ3の中間にインバータＩＮＶ1が接続
され、ＩＮＶ1は入力電圧が閾値よりも小のときに最大
値を、また閾値を越えたときに０Ｖを出力する。いまｘ
が入力された状態で開始トリガＳＴが入力されると、Ｃ
1両端の電位差が次第に増加し、Ｃ1、Ｃ2間の電圧は次
第に低下して、ＩＮＶ1への入力電圧は減少する。[0006] timer T 1 becomes grounded intermediate series Condesa C 1, C 2 through the high resistance R 1, the input step-like start trigger ST to Condesa C 1 side, whereas the C 2 side , input voltage x via a capacitor C 3 is connected. The inverter INV 1 is connected to an intermediate of C 2, C 3, INV 1 is a maximum value when the smaller than the input voltage threshold, and also outputs 0V when exceeding the threshold. Now x
When the start trigger ST is input in a state where is input, C
1 The potential difference between both ends gradually increases, the voltage between C 1 and C 2 gradually decreases, and the input voltage to INV 1 decreases.

【０００７】このときのＣ1、Ｃ2間電圧Ｖ1の変化は図
２に示すとおりであり、 Ｖ1＝Ｖst×ｅｘｐ｛−ｔ1／（Ｒ1Ｃ1）｝ ｔ1 ：時間 Ｖst：開始トリガの最大電圧 と表現される。この充電によってＩＮＶ1の入力は低下
し、Ｖ1＝ｘとなったときに、その出力は０Ｖになる。
Ｔ2はＴ1と同様に構成され、その構成要素を「’」を
付して示すと、ＩＮＶ1の出力はＴ2のコンデンサＣ1’
に入力され、ＩＮＶ1の出力が０ＶになるとＣ1’、
Ｃ2’間の電圧が低下し始め、Ｖ1’＝ｙとなったときに
ＩＮＶ1’の出力電圧が０Ｖになる。The change in the voltage V 1 between C 1 and C 2 at this time is as shown in FIG. 2, where V 1 = V st × exp {−t 1 / (R 1 C 1 )} t 1 : time V st : Expressed as the maximum voltage of the start trigger. This charging lowers the input of INV 1 , and when V 1 = x, the output goes to 0V.
T 2 are the same configuration as the T 1, the components '''and shown as being denoted by the output of the INV 1 capacitor C 1 of T 2'
When the output of INV 1 becomes 0 V, C 1 ′,
The voltage between C 2 ′ starts to drop and when V 1 ′ = y, the output voltage of INV 1 ′ becomes 0V.

【０００８】一方、ＩＮＶ1’の出力および開始トリガ
ＳＴ（基準電圧）は第３タイマＴ3に入力され、Ｔ3にお
いてＴ1、Ｔ2の総充電時間（総作動時間）が算出され
る。Ｔ3は、ＩＮＶ1’の出力がゲートに入力されたｐＭ
ＯＳ（以下Ｔｒという）を有し、このＴｒのドレイン
に、コンデンサＣ4、抵抗Ｒ2を順次介して、開始トリガ
ＳＴが入力されている。Ｔｒのソースは接地され、ゲー
ト電圧すなわちＩＮＶ1’の出力電圧が充分高い値のと
きｐＭＯＳは導通し、Ｃ4には一端にＳＴが他端にグラ
ンドが接続される。このとき、Ｃ4は充電される。そし
てＴｒのゲート電圧が０Ｖになると、ｐＭＯＳは遮断さ
れ、以後Ｃ4の電荷が保持される。すなわち、Ｔ3は
Ｔ1、Ｔ2の充電時間の合計の時間だけＳＴによる充電が
行われる。On the other hand, the output and start trigger ST of INV 1 '(a reference voltage) is input to the third timer T 3, the T 3 T 1, T total charge time of 2 (total operating time) is calculated. T 3, the output of INV 1 'is input to the gate pM
It has an OS (hereinafter referred to as Tr), and a start trigger ST is input to the drain of the Tr via a capacitor C 4 and a resistor R 2 sequentially. Tr source is grounded, pMOS is rendered conductive when a sufficient high value output voltage is the gate voltage, ie INV 1 ', the ground is connected the ST to the other at one end to C 4. In this case, C 4 is charged. When the gate voltage of the Tr becomes 0V, pMOS is blocked, the charge of the subsequent C 4 is held. That, T 3 is charged by time only ST of the total charge time of T 1, T 2 is performed.

【０００９】Ｔ3の充電特性は Ｖ3＝Ｖst×ｅｘｐ｛−ｔ3／（Ｒ2Ｃ4）｝ ｔ ：時間 Ｖst：開始トリガの最大電圧 であり、Ｒ1＝Ｒ1’＝Ｒ2、Ｃ1＝Ｃ1’＝Ｃ4とすると、 （ｘ／Ｖst）×（ｙ／Ｖst）＝（ｚ／Ｖst） ｅｘｐ｛−ｔ1／（Ｒ1Ｃ1）｝×ｅｘｐ｛−ｔ2／
（Ｒ1’Ｃ2’｝＝ｅｘｐ｛−ｔ3／（Ｒ2Ｃ4）｝ であり、Ｔ3の出力電圧ｚ（Ｃ4、Ｒ2間の電圧）は入力
電圧ｘ、ｙの積になる。The charging characteristic of T 3 is as follows: V 3 = V st × exp ｛−t 3 / (R 2 C 4 )｝ t: time V st : maximum voltage of the start trigger, and R 1 = R 1 ′ = R 2 , assuming that C 1 = C 1 ′ = C 4 , (x / V st ) × (y / V st ) = (z / V st ) exp {−t 1 / (R 1 C 1 )} × exp} −t 2 /
(R 1 'C 2 '｝ = exp ｛-t 3 / (R 2 C 4 )｝), and the output voltage z of T 3 (the voltage between C 4 and R 2 ) is the product of the input voltages x and y. Become.

【００１０】ここにＲＣ回路の充電特性は、一般のアナ
ログ型乗算回路に比較して精度が高く、またデジタル型
乗算器に比較して著しく構成が単純である。なお、ｚの
補数出力（１−ｚ）を得るためには、図３に示すよう
に、ｐＭＯＳ（以下Ｔｒ’という）のソースをＣ4’を
介して接地し、ＳＴをＲ2’を介してＴｒ’のドレイン
に入力し、Ｔｒ’とＣ4’との間の電圧を出力電圧とす
る。Here, the charging characteristic of the RC circuit is higher in accuracy than a general analog type multiplier circuit, and the configuration is significantly simpler than that of a digital type multiplier. In order to obtain the complement output (1-z) of z, as shown in FIG. 3, the source of the pMOS (hereinafter Tr ') is grounded via C 4 ', and ST is connected via R 2 '. Input to the drain of Tr ′, and the voltage between Tr ′ and C 4 ′ is set as the output voltage.

【００１１】[0011]

【発明の効果】前述のとおり、この発明に係る乗算回路
は、時間の指数関数で出力が変化するとともに、基準電
圧と入力電圧との比に対応した時間だけこの指数関数的
変化を生じさせる第１、第２タイマを用いて第１、第２
入力電圧に基づくカウントを行い、両タイマの総動作時
間を第３タイマで算出して乗算結果を出力するので、回
路が小規模であるとともに、計算精度が良好であるとい
う優れた効果を有する。As described above, in the multiplier circuit according to the present invention, the output changes in an exponential function of time, and the exponential change occurs for a time corresponding to the ratio between the reference voltage and the input voltage. 1st, 2nd using the 2nd timer
Since the counting based on the input voltage is performed, the total operation time of both timers is calculated by the third timer, and the multiplication result is output, there is an excellent effect that the circuit is small and the calculation accuracy is good.

【図面の簡単な説明】[Brief description of the drawings]

【図１】この発明に係る乗算回路の１実施例を示す回路
図である。FIG. 1 is a circuit diagram showing one embodiment of a multiplication circuit according to the present invention.

【図２】同実施例における各タイマの特性を示すグラフ
である。FIG. 2 is a graph showing characteristics of each timer in the embodiment.

【図３】第１実施例の第３タイマの変形例を示す回路図
である。FIG. 3 is a circuit diagram showing a modified example of the third timer of the first embodiment.

【符号の説明】[Explanation of symbols]

Ｔ1 第１タイマ Ｔ2 第２タイマ Ｔ3 第３タイマ Ｃ1，Ｃ2，Ｃ3，Ｃ1’，Ｃ2’，Ｃ3’，Ｃ4，Ｃ4’
コンデンサ Ｒ1，Ｒ1’ 高抵抗 Ｒ2 抵抗 ＳＴ 開始トリガ ｘ，ｙ 入力電圧 ＩＮＶ1，ＩＮＶ1’ インバータ Ｔｒ，Ｔｒ’ ｐＭＯＳ ｚ 出力電圧 Ｖ1，Ｖ1’，Ｖ3 電圧 ＶCC 電源T 1 The first timer T 2 second timer T 3 third timer C 1, C 2, C 3 , C 1 ', C 2', C 3 ', C 4, C4'
Capacitor R 1, R 1 'high resistance R 2 resistor ST start trigger x, y input voltage INV 1, INV 1' inverter Tr, Tr 'pMOS z output voltage V 1, V 1', V 3 voltage V CC supply

フロントページの続き (72)発明者 ウィワット・ウォンワラウィパット 東京都世田谷区北沢３−５−18 株式会 社鷹山内 (72)発明者 高取 直 東京都世田谷区北沢３−５−18 株式会 社鷹山内 (72)発明者 山本 誠 東京都世田谷区北沢３−５−18 株式会 社鷹山内 (56)参考文献 特公 昭52−26858（ＪＰ，Ｂ２) (58)調査した分野(Int.Cl.6，ＤＢ名) G06G 7/16 G06F 7/556 G06F 7/62 Continued on the front page (72) Inventor Wewatt Wonwarawipat 3-5-18 Kitazawa, Setagaya-ku, Tokyo Co., Ltd. (72) Inventor Nao Takatori 3-5-18 Kitazawa, Setagaya-ku, Tokyo Co., Ltd. Takayamauchi (72) Inventor Makoto Yamamoto 3-5-18 Kitazawa, Setagaya-ku, Tokyo Takayamauchi Co., Ltd. (56) References JP-B-52-26858 (JP, B2) (58) Fields surveyed (Int.Cl) . 6, DB name) G06G 7/16 G06F 7/556 G06F 7/62

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】 時間に対して指数関数的に出力電圧が増
加する特性を有するとともに基準電圧と入力電圧との差
に対応した時間だけ作動する第１、第２タイマと、電圧
信号を終了トリガとして、時間に対して指数関数的出力
電圧が増加する特性を有する第３タイマとを備え、第１
タイマには第１入力電圧が入力されるとともに、ステッ
プ状の開始トリガが基準電圧として入力され、その出力
電圧が基準電圧として第２タイマに入力され、第２タイ
マには第２入力電圧が入力されるともにその出力が終了
トリガとして第３タイマに入力され、第３タイマには前
記開始トリガが入力信号として入力されていることを特
徴とする乗算回路。1. A first and a second timer having a characteristic that an output voltage increases exponentially with respect to time and operating only for a time corresponding to a difference between a reference voltage and an input voltage, and a trigger for terminating a voltage signal. And a third timer having a characteristic that an exponential output voltage increases with time.
The first input voltage is input to the timer, a step-like start trigger is input as a reference voltage, the output voltage is input to the second timer as the reference voltage, and the second input voltage is input to the second timer. A multiplying circuit, wherein the output is input to a third timer as an end trigger, and the start trigger is input to the third timer as an input signal.
JP4280792A 1992-09-25 1992-09-25 Multiplication circuit Expired - Lifetime JP2985993B2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP4280792A JP2985993B2 (en) 1992-09-25 1992-09-25 Multiplication circuit
US07/964,157 US5343419A (en) 1992-09-25 1992-10-21 Analog calculation circuit using timers
KR1019930018186A KR940008266A (en) 1992-09-25 1993-09-09 A multiplication circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4280792A JP2985993B2 (en) 1992-09-25 1992-09-25 Multiplication circuit

Publications (2)

Publication Number Publication Date
JPH06111036A JPH06111036A (en) 1994-04-22
JP2985993B2 true JP2985993B2 (en) 1999-12-06

Family

ID=17630030

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4280792A Expired - Lifetime JP2985993B2 (en) 1992-09-25 1992-09-25 Multiplication circuit

Country Status (2)

Country Link
JP (1) JP2985993B2 (en)
KR (1) KR940008266A (en)

Also Published As

Publication number Publication date
KR940008266A (en) 1994-04-29
JPH06111036A (en) 1994-04-22

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