JP2985278B2 - Component placement design support method - Google Patents
Component placement design support methodInfo
- Publication number
- JP2985278B2 JP2985278B2 JP2291528A JP29152890A JP2985278B2 JP 2985278 B2 JP2985278 B2 JP 2985278B2 JP 2291528 A JP2291528 A JP 2291528A JP 29152890 A JP29152890 A JP 29152890A JP 2985278 B2 JP2985278 B2 JP 2985278B2
- Authority
- JP
- Japan
- Prior art keywords
- component
- signal line
- components
- main axis
- designating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は部品配置設計支援方式に関し、特に電子機器
のプリント配線板の部品配置設計支援に関する。Description: TECHNICAL FIELD The present invention relates to a component layout design support system, and more particularly to a component layout design support for a printed wiring board of an electronic device.
従来の部品配置設計支援方式は、部品間の仮想配線長
を短くするように配置するか、部品間においたカットラ
インを横切る配線の数が少なくなるように配置してい
た。In the conventional component placement design support system, the components are arranged so as to shorten the virtual wiring length between the components, or to reduce the number of wires crossing the cut line between the components.
上述した従来の部品配置設計支援方式は、配線処理で
分岐配線を許した場合に、主軸線に対する各ロードピン
の分岐線長が一定にならない欠点と、配線処理を行った
時、配線長が指定線長以内になるかどうか保証されない
欠点がある。The conventional component placement design support method described above has the disadvantage that the branch line length of each load pin with respect to the main axis is not constant when the branch wiring is permitted in the wiring process, and that the wiring length is equal to the designated line length when performing the wiring process. There are drawbacks that are not guaranteed to be within long.
本発明の部品配置設計支援方式は、プリント配線板の
部品配置設計支援方式において、前記プリント配線板に
搭載される部品及び部品間信号線等の論理接続情報を格
納した論理接続情報記憶手段と；前記信号線及びその主
軸線長，分岐線長を指定する信号線指定手段と；前記信
号線指定手段を介して指定された信号線に接続する部品
を前記論理接続情報記憶手段を参照して求め、この指定
された信号線に接続する部品のなかからソースピンを持
つ部品と最終ロードピンを持つ部品とを選択し配置可能
領域に配置指定し、この２つの部品の前記ソースピン及
び前記最終ロードピン間を主軸線として前記信号線指定
手段を介して指定された主軸線長以内で配線指定し、前
記主軸線の両隣に前記信号線指定手段を介して指定され
た分岐線長だけ離れた仮線を設定し、前記指定された信
号線に接続する未配置の部品をそのロードピンが前記仮
線上に載る様に配置指定し、これらの部品の配置情報を
出力する部品配置処理手段とを有している。The component placement design support method according to the present invention is the component placement design support method for a printed wiring board, wherein logical connection information storage means for storing logical connection information such as components mounted on the printed wiring board and signal lines between components; A signal line designating means for designating the signal line and its main axis length and branch line length; and a part to be connected to the signal line designated via the signal line designating means is obtained by referring to the logical connection information storage means. A component having a source pin and a component having a final load pin are selected from the components connected to the designated signal line, and the components are designated in the allocable area, and the components between the source pin and the final load pin of the two components are designated. Is designated as a main axis within a main axis length specified through the signal line specifying means, and separated by a branch line length specified through the signal line specifying means on both sides of the main axis. Component placement processing means for setting provisional lines, designating placement of unplaced components connected to the designated signal lines so that their load pins are placed on the provisional lines, and outputting placement information of these components. doing.
次に、本発明について図面を参照して説明する。 Next, the present invention will be described with reference to the drawings.
第１図は本発明の一実施例のブロック図である。本実
施例の部品配置設計支援方式は、論理接続情報ファイル
10からの論理接続情報を格納する論理接続情報記憶部１
と、クロック信号等のクリティカルな信号線を指定する
信号線指定部３と、主軸線の長さを指定する主軸線指定
部４と、分岐線の長さを指定する分岐線指定部５と、ク
リティカルな信号線に接続する部品名を記憶する信号線
接続部品名記憶部６と、クリティカルな信号線に接続す
る部品数をカウントする信号線接続部品数カウンタ７
と、配置処理済の部品数をカウントする処理済部品数カ
ウンタ８と、配線可能領域内の部品配置状況を格納する
配線領域マップ記憶部９と、上記各部を制御して指定さ
れたクリティカルな信号線に対する部品配置を行い部品
配置情報を部品配置情報ファイル11に出力し部品配置不
能時のエラー情報をエラーファイル12に出力する部品配
置処理部２とを有している。FIG. 1 is a block diagram of one embodiment of the present invention. The component placement design support method of this embodiment is based on a logical connection information file.
Logical connection information storage unit 1 for storing logical connection information from 10
A signal line designating unit 3 for designating a critical signal line such as a clock signal, a main axis designating unit 4 for designating the length of the main axis, a branch line designating unit 5 for designating the length of the branch line, A signal line connection component name storage unit 6 for storing names of components connected to critical signal lines, and a signal line connection component number counter 7 for counting the number of components connected to critical signal lines.
And a processed part number counter 8 for counting the number of arranged parts, a wiring area map storage unit 9 for storing a part arrangement state in the wirable area, and a critical signal designated by controlling the above parts. And a component placement processing unit 2 that performs component placement on the line, outputs component placement information to the component placement information file 11, and outputs error information when component placement is impossible to the error file 12.
次に、動作を説明する。第２図（ａ），（ｂ）にフロ
ーチャートを、第３図に部品の配置例を示す。Next, the operation will be described. 2 (a) and 2 (b) show a flowchart, and FIG. 3 shows an example of component arrangement.
部品配置処理部２の制御により以下の処理を行う。信
号線指定部３により分岐線長を一定にしたいクロック信
号等の信号線αを指定する（ステップS1）。論理接続情
報記憶部１の論理接続情報から信号線αに接続する部品
を抽出し、それぞれをaiとし、信号線接続部品名記憶部
６に格納する（ステップS2）。部品aiの中から信号線α
のソースピンを持つ部品Ｐと信号線αの最終ロードピン
を持つ部品Ｑを選択する（ステップS3）。部品aiの全個
数をカウント値ｊとして信号線接続部品数カウンタ７へ
設定しておく（ステップS4）。配線領域マップ記憶部９
の情報に基づいて部品Ｐと部品Ｑとを配線可能領域内に
配置する（ステップS5）。信号線接続部品数カウンタ７
のカウント値ｊから部品P,Qの２個分を差し引いておく
（ステップS6）。部品Ｐのソースピンと部品Ｑの最終ロ
ードピンを主軸線指定部４により理論上の遅延計算に基
づき指定された線長以内で配線し、このパターンを主軸
線Ｌとする（ステップS7）。主軸線Ｌの両隣に分岐線指
定部５により指定された分岐線長ｍだけ離れた所に配置
のための仮線N1とN2とを設定する（ステップS8）。The following processing is performed under the control of the component placement processing unit 2. The signal line designation unit 3 designates a signal line α for a clock signal or the like whose branch line length is to be made constant (step S1). The components to be connected to the signal line α are extracted from the logical connection information in the logical connection information storage unit 1 and each is set as ai and stored in the signal line connection component name storage unit 6 (step S2). Signal line α from part ai
The component P having the source pin and the component Q having the final load pin of the signal line α are selected (step S3). The total number of the components ai is set in the signal line connection component number counter 7 as the count value j (step S4). Wiring area map storage 9
Based on this information, the components P and Q are arranged in the wirable area (step S5). Signal line connection parts counter 7
The two components P and Q are subtracted from the count value j (step S6). The source pin of the component P and the final load pin of the component Q are wired within the line length specified by the main axis specifying unit 4 based on theoretical delay calculation, and this pattern is set as the main axis L (step S7). Setting the temporary line N 1 and N 2 for placement away only the specified branch line length m by the branch line specifying section 5 on both sides of the main axis L (step S8).
次に、信号線接続部品名記憶部６に格納されている残
りのすべての部品aiについて配置処理を行う。まず、処
理済部品数カウンタ８のカウント値ｉを“0"に設定し
（ステップS9）、配置処理が行なわれるたびにそのカウ
ント値ｉに“1"を加算する（ステップS10）。仮線N1上
で部品Ｐから任意の距離ｄ離れた点を点O1とする（ステ
ップS11）。分岐線により信号線αに継がる部品aiのロ
ードピンが点O1上に載るように部品aiを配置する（ステ
ップS12）。ステップS12の処理で部品aiが他の部品と重
なるならば（ステップS13のYES）、点O1を仮線N1上を微
小距離Δｄ離れた位置に移動させ（ステップS14）、点O
1が仮線N1の終点（部品Ｑ）に行きつくまでステップS12
〜ステップS14の処理を繰返す。点O1が仮線N1の終点に
行きついたら（ステップS15のYES）、仮線N2上の部品Ｐ
より距離ｄだけ離れた点をO2とし（ステップS16）、上
記と同様に、点O2上に部品aiを配置し（ステップS1
7）、他の部品と重なるならば（ステップS18のYES）、
点O2を仮線N2の終点に行きつくまで微小距離Δｄずつ移
動させながら（ステップS19）、ステップS17〜ステップ
S19の処理を繰り返す。Next, an arrangement process is performed on all the remaining components ai stored in the signal line connection component name storage unit 6. First, the count value i of the processed component number counter 8 is set to "0" (step S9), and "1" is added to the count value i each time the arrangement processing is performed (step S10). The point away any distance d from the component P on phantom N 1 and the point O 1 (step S11). Load pin of Tsugaru component ai to the signal line α by a branch line to place components ai to rest on the point O 1 (step S12). If component ai overlaps with other components in the process of step S12 (YES in step S13), and moves the point O 1 on Karisen N 1 at a position away a small distance [Delta] d (step S14), and the point O
1 step to end up in the end point of the phantom N 1 (component Q) S12
Step S14 is repeated. When the point O 1 reaches the end point of the provisional line N 1 (YES in step S15), the part P on the provisional line N 2
A point distant by more distance d and O 2 (step S16), and in the same manner as described above, to place the components ai on the point O 2 (step S1
7) If it overlaps with another part (YES in step S18),
While moving the point O 2 by the minute distance Δd until reaching the end point of the provisional line N 2 (Step S19), Steps S17 to S17
The processing of S19 is repeated.
点O2が仮線N2の終点に行きついたら（ステップS20のY
ES）、部品aiは配置不能としてエラー情報を出力しエラ
ーファイル12に書込む（ステップ21）。When the point O 2 reaches the end point of the provisional line N 2 (Y in step S20)
ES), the component ai outputs error information as being unplaceable and writes it to the error file 12 (step 21).
ステップS13またはステップS18で他の部品と重ならな
かった部品aiに対して、部品配置情報を取出し部品配置
情報ファイル11に書込む（ステップS22）。処理済部品
数カウンタ８のカウント値ｉが信号線接続部品数カウン
タ７のカウント値ｊの値未満の間、ステップS10〜ステ
ップS22の処理を繰返す（ステップS23）。For the component ai that does not overlap with another component in step S13 or step S18, the component placement information is extracted and written in the component placement information file 11 (step S22). While the count value i of the processed component number counter 8 is less than the count value j of the signal line connected component number counter 7, the processes of steps S10 to S22 are repeated (step S23).
以上説明したように本発明は、信号線名を指定し、接
続する部品の中よりソースピンと最終ロードピンを持つ
部品を配置可能領域中に置き、そのソースピンと最終ロ
ードピンを指定線長で結線した主軸線を設けその主軸線
の両隣の指定分岐線長だけ離れた所に仮線を設けて残り
の部品のロードピンが先の仮線上に載るように部品を配
置することによって、配線長が指定線長以内でかつ主軸
線に対して分岐線長がほぼ一定になるような部品配置情
報を得られる効果がある。As described above, according to the present invention, a main shaft in which a signal line name is specified, a component having a source pin and a final load pin is placed in a placeable area from among components to be connected, and the source pin and the final load pin are connected by a specified line length. By providing a temporary line at a position separated by the specified branch line length on both sides of the main axis and arranging the parts so that the load pins of the remaining parts are placed on the previous temporary line, the wiring length becomes the specified line length Within this range, there is an effect that component arrangement information can be obtained such that the branch line length becomes substantially constant with respect to the main axis.
【図面の簡単な説明】 第１図は本発明の一実施例のブロック図、第２図は本発
明のフローチャート、第３図は本発明による部品の配置
例を示す図である。 １……論理接続情報記憶部、２……部品配置処理部、３
……信号線指定部、４……主軸線指定部、５……分岐線
指定部、６……信号線接続部品名記憶部、７……信号線
接続部品数カウンタ、８……処理済部品数カウンタ、９
……配線領域マップ記憶部、10……論理接続情報ファイ
ル、11……部品配置情報ファイル、12……エラーファイ
ル。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of one embodiment of the present invention, FIG. 2 is a flowchart of the present invention, and FIG. 3 is a diagram showing an example of the arrangement of components according to the present invention. 1 ... logical connection information storage unit, 2 ... component placement processing unit, 3
... Signal line designation part, 4... Spindle line designation part, 5... Branch line designation part, 6... Signal line connection part name storage part, 7... Signal line connection part number counter, 8. Number counter, 9
... Wiring area map storage unit, 10... Logical connection information file, 11... Component placement information file, 12.
Claims (1)
おいて、前記プリント配線板に搭載される部品及び部品
間信号線等の論理接続情報を格納した論理接続情報記憶
手段と；前記信号線及びその主軸線長，分岐線長を指定
する信号線指定手段と；前記信号線指定手段を介して指
定された信号線に接続する部品を前記論理接続情報記憶
手段を参照して求め、この指定された信号線に接続する
部品のなかからソースピンを持つ部品と最終ロードピン
を持つ部品とを選択し配置可能領域に配置指定し、この
２つの部品の前記ソースピン及び前記最終ロードピン間
を主軸線として前記信号線指定手段を介して指定された
主軸線長以内で配線指定し、前記主軸線の両隣に前記信
号線指定手段を介して指定された分岐線長だけ離れた仮
線を設定し、前記指定された信号線に接続する未配置の
部品をそのロードピンが前記仮線上に載る様に配置指定
し、これらの部品の配置情報を出力する部品配置処理手
段とを有することを特徴とする部品配置設計支援方式。In a component layout design support system for a printed wiring board, logical connection information storage means for storing logical connection information of components mounted on the printed wiring board and signal lines between components, etc .; A signal line designating means for designating a main axis length and a branch line length; and a part to be connected to the signal line designated via the signal line designating means is obtained by referring to the logical connection information storage means, and the designated A component having a source pin and a component having a final load pin are selected from the components connected to the signal line, and are arranged and designated in the allocable area. The space between the source pin and the final load pin of the two components is defined as a main axis. Specify wiring within the main axis length specified via the signal line specifying means, and set a temporary line separated by the branch line length specified via the signal line specifying means on both sides of the main axis, and Component placement means for designating placement of unplaced components connected to the specified signal lines such that their load pins are placed on the provisional lines, and outputting placement information of these components. Design support method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2291528A JP2985278B2 (en) | 1990-10-29 | 1990-10-29 | Component placement design support method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2291528A JP2985278B2 (en) | 1990-10-29 | 1990-10-29 | Component placement design support method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04165471A JPH04165471A (en) | 1992-06-11 |
| JP2985278B2 true JP2985278B2 (en) | 1999-11-29 |
Family
ID=17770072
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2291528A Expired - Fee Related JP2985278B2 (en) | 1990-10-29 | 1990-10-29 | Component placement design support method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2985278B2 (en) |
-
1990
- 1990-10-29 JP JP2291528A patent/JP2985278B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH04165471A (en) | 1992-06-11 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |