JP2985212B2 - Edge detection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The edge detection circuit of the present invention will be described in detail according to the following items.

A. Industrial application fields B. Summary of the invention C. Prior art [Fig. 5] D. Problems to be solved by the invention [Fig. 6] E. Means for solving the problems F. Examples [Fig. 1 to 4] a. Circuit configuration [FIGS. 1 to 3] a-1. Complementary circuit [FIG. 2] a-2. Pulse width limiting circuit [FIG. 3] b. Figure] c. Function G. Effect of the Invention (A. Field of Industrial Application) The present invention relates to a novel edge detection circuit. For more information,
It is an object of the present invention to provide a novel edge detection circuit for stabilizing a binarized signal corresponding to an edge portion of an input signal.

(B. Summary of the Invention) An edge detection circuit according to the present invention includes a high-pass filter for extracting a high-frequency component of an input signal, a double-wave rectifier for performing double-wave rectification on a signal from the high-pass filter, and outputting the double-wave rectifier. Comparing the signal level output by the means with a reference value to determine whether or not the signal is an edge of the input signal, and obtaining a binary signal corresponding to the determination result; By synthesizing the delay signal of the binarized signal and the delayed signal, 2
By providing complementary means for generating a signal having a substantially continuous level as a digitized signal, the level change of the binarized signal corresponding to the edge portion is prevented from frequently occurring.

(C. Prior Art) [FIG. 5] In a VTR (Video Tape Recorder), a circuit for detecting an edge portion of a signal is used. For example, an edge detection circuit for an edge noise reducer related to a Y (luminance) signal, , An edge detection circuit for an edge enhancer related to a reproduced C (chroma) signal, an edge detection circuit used for switching a bandpass filter for C signal separation in Y / C separation, and the like.

FIG. 5 (A) shows an example a of such an edge detection circuit.

The input signal is sent to a high-pass filter (high-pass filter or band-pass filter) c via a signal input terminal b and then to a comparator e via a dual-wave rectifier circuit d.

Then, the comparator e compares the level of the envelope waveform extracted by the dual-wave rectifier circuit d with a predetermined reference value (this is referred to as “V _ref ”), and the result of the comparison is output as a pulse signal to the output terminal f. From.

The signal input to the edge detection circuit a has its high-frequency component extracted by the high-pass filter c and then the envelope is detected. The signal level is compared with the reference value in the comparator e, and the comparison result is binarized. (Hereinafter referred to as an “edge pulse”) from the output terminal f.

FIG. 5 (B) schematically shows the signal waveform of each part when the S / N (signal to noise) ratio of the input signal is high, where “A” is a ramp-shaped input signal, and “B” is both. The output “C” of the wave rectifier circuit d indicates the edge pulse output from the comparator e.

(D. Problems to be Solved by the Invention) [FIG. 6] In the above-described edge detection circuit a, when the S / N ratio of the input signal is low, the generation of the edge detection pulse becomes unstable. There is a problem that it becomes.

FIG. 6 schematically shows this situation, and the meanings of A to C in the figure are as described above with reference to FIG. 5 (B).

For example, when a reproduced Y (luminance) signal in a VTR is taken as the input signal A, a component of the crosstalk picked up by the magnetic head that is difficult to remove due to the azimuth effect appears as edge noise in the outline portion, and thus the change in the input signal is smooth. Instead of high-frequency noise components.

Then, a phenomenon occurs such or is less than V _ref or exceeds the signal level is the reference value V _ref in the edge portion as shown in an envelope waveform B, the level of the edge pulse is H (high) a level interval frequently Will be done.

(E. Means for Solving the Problems) In order to solve the above-described problems, the edge detection circuit of the present invention employs a high-pass filter for extracting a high-frequency component of an input signal, and a signal from the high-pass filter for both waves. A dual-wave rectifier for rectifying and outputting the signal, and comparing the signal level output from the dual-wave rectifier with a reference value to determine whether or not the input signal is an edge portion, and forming a binary signal corresponding to the determination result. A comparison means for obtaining the signal and a complementing means for generating a signal having a substantially continuous level as a binary signal indicating an edge portion by combining the binary signal and a delay signal of the binary signal are provided. Things.

Therefore, according to the edge detection circuit of the present invention, a single signal level period corresponding to an edge portion can be obtained by the complementing means, so that the inconvenience that the level change of the edge detection pulse occurs indiscriminately is solved. .

(F. Embodiment) [FIGS. 1 to 4] Hereinafter, the details of the edge detection circuit of the present invention will be described with reference to the illustrated embodiment. The illustrated embodiment illustrates the present invention.
An example in which the present invention is applied to an edge detection circuit used for an edge noise reducer which forms a part of a reproduction Y signal processing system in a VTR is shown.

That is, in the edge noise reducer, when the edge detection circuit detects an edge portion related to the reproduced Y signal, the comb filter is deeply applied to enhance the noise removal effect and improve the S / N ratio.

(A. Circuit Configuration) [FIGS. 1 to 3] In the drawings, reference numeral 1 denotes an edge detection circuit.

 Reference numeral 2 denotes a signal input terminal to which a reproduced Y signal is input.

Reference numeral 3 denotes a high-pass filter, which is provided to extract a high-frequency component of the Y signal from the signal input terminal 2, and uses a high-pass filter or a band-pass filter.

Reference numeral 4 denotes a dual-wave rectifier circuit, which is provided after the high-pass filter 3 and is provided to extract an envelope waveform of an output signal of the high-pass filter 3.

Reference numeral 5 denotes a comparator. The output signal of the dual-wave rectifier circuit 4 is input to a positive input terminal of the comparator, and a predetermined reference voltage (referred to as “V _ref ”) is supplied to a negative input terminal by a constant voltage source 6. Have been added.

(A-1. Complementary Circuit) [FIG. 2] Reference numeral 7 denotes a complementary circuit, which is provided after the comparator 5. This complementary circuit 7 is used when the edge pulse output from the comparator 5 is disturbed due to the influence of edge noise or the like at the edge portion of the Y signal, and the state frequently changes between high and low (that is, H level or L level).
This is a circuit for complementing an L level section for a predetermined time or less occurring between a certain H level section and the next H level section by regarding it as an H level and filling in the gap between the two.

As an example of the complementing circuit 7, there is a configuration example 8 as shown in FIG. 2 (A), for example.

This circuit 8, 2 · t _u min of L when the unit time was t _u
The configuration is such that level sections can be complemented.

That is, 3 to the OR circuit 9 inputs a signal g _A from the comparator 5, and the delayed signal g _B delayed by t _u for the input signal g _A by the delay circuit 10, a delay signal g _B by the delay circuit 11
A delayed signal g _C delayed even more t _u is adapted to be input.

Reference numeral 12 denotes a 3-input AND circuit, and the output signal g _{D of the} OR circuit 9
When the signal g _D and the delayed signal g _E which delay time t _u by passing through the delay circuit 13, yet t _u from the delay signal g _E by the delay circuit 14
Delayed delay signal g _F is input.

Then, the output signal g _G of the AND circuit 12 becomes the final output of the complementing circuit 8.

FIG. 2 (B) is a time chart schematically showing an example of a signal situation in each section.

Now, when the L level period of 2 · t _u and is between the H-level section with the input signal g _A (t _u) and the next H level period (t _u), the signal g _B, g _C is T _{u for} the input signal g _A ,
And delayed by 2 · t _u, therefore the sum signal g _D obtained by the OR circuit 9 becomes a signal having a H-level section of 6 · t _u.

And each t _u, 2 · t _u delayed signal g _E with respect to the signal g _D, a g _F, 3 one signal g _D by the AND circuit 12,
The product signal g _G of g _E and g _F is the time signal 2 _G from the rise of the signal g _A.
t _u delay, and will be output as a signal having the H level section over 4 · t _u.

(A-2. Pulse width limiting circuit) [FIG. 3] Reference numeral 15 denotes a pulse width limiting circuit provided at the subsequent stage of the complementing circuit 7 for removing unnecessary portions at the rising edge pulse from the complementing circuit 7. Things.

That is, edge noise as shown schematically in FIG. 3 (C) is to appear in the second half of the rise of the Y signal, the width of the edge pulse is narrow as w _1, less the effect of the comb filter , comb filter even before the rise of too wide when Y signal as w ₂ it takes deep reversed.

Therefore, in order to eliminate this inconvenience, the comparator 5
The threshold _Vref is set to be low so that the width of the edge pulse output from the complementing circuit 7 is widened, and the pulse width limiting circuit 15 removes an unnecessary portion h at the rising portion of the edge pulse. Are used as edge pulses.

As an example of the pulse width limiting circuit 15, as shown in FIG. 3A, a delay circuit 16 and a two-input AND circuit 17 are provided. A signal delayed by a predetermined time (referred to as “η”) by the output signal passing through the delay circuit 16 is input.

FIG. 3 (B) is a time chart schematically showing the signal waveforms of the respective parts, where “g _G ” is the output signal of the complementing circuit 7, “g _H ” is the delay signal obtained by the delay circuit 16,
“G _I ” indicates an output signal of the AND circuit 17.

As can be seen, the output signal g _I of the AND circuit 17 is the signal g
Rising from the rise of _G with a delay time eta, the fall is a pulse waveform synchronized with the falling edge of the signal g _G.

Then, so that the signal g _I is used as the final edge pulse.

(B. Operation) [FIG. 4] The operation of the edge detection circuit 1 described above is performed as follows. FIG. 4 shows the S / N of the reproduced Y signal.
FIG. 4 schematically shows signal waveforms at various parts of the circuit when the ratio is low, in which “A” is a reproduced Y signal, “B” is an output signal of the dual-wave rectifier circuit 4, and “C” is an output signal of the comparator 5. , "D" indicate the output signal of the complementing circuit 7, and "E" indicates the final edge pulse output from the pulse width limiting circuit 15. It should be noted that the signal waveform is shown in the figure while ignoring the time delay required for signal processing.

As shown in waveform A, the reproduced Y signal includes a noise component from the rising portion to the latter half of the rising portion.

The high-frequency component of the reproduced Y signal is extracted by the high-pass filter 3 and then converted into an absolute value by the dual-wave rectifier circuit 4 (see waveform B).

Thereafter, the double-wave rectified output is equal to the threshold V _{ref of the} comparator 5.
In this case, the output waveform C
Is obtained as a waveform in which H and L level changes are frequently repeated.

The complementing circuit 7 detects the L of the output waveform C for a predetermined time or less.
The level section is set to the H level, and an adjacent H level section is connected so as to be corrected to a pulse signal having only a single H level section, and this is set as an output signal D.

Then, the unnecessary portion h at the rising edge is removed by the pulse width limiting circuit 15, and the final edge pulse E is obtained.

(C. Operation) In the edge detection circuit 1, when the length of the L level section in the output signal of the comparator 5 is shorter than a predetermined time, the complement circuit replaces the signal level in the level section with the H level. 7, an edge pulse having a single H level section corresponding to the edge of the input signal can be obtained.

(G. Effect of the Invention) As is clear from the above description, the edge detection circuit of the present invention performs high-frequency filtering of a high-frequency component of an input signal and dual-wave rectification of the signal from the high-frequency filtering. A dual-wave rectifier for outputting, and a signal level output from the dual-wave rectifier for comparing with a reference value to determine whether or not the input signal is an edge portion, and to obtain a binary signal corresponding to the determination result. Comparing means and a complementing means for generating a substantially continuous level signal as a binarized signal indicating an edge portion by synthesizing the binarized signal and a delay signal of the binarized signal. Features.

Therefore, according to the present invention, since a single signal level period corresponding to an edge portion can be obtained by the complementing means, the inconvenience that the level change of the edge detection pulse occurs indiscriminately is solved.

[Brief description of the drawings]

1 to 4 show an embodiment of an edge detection circuit according to the present invention. FIG. 1 shows a circuit block diagram, FIG. 2 shows an example of a complementary circuit, and FIG. FIG. 3 (B) is a time chart, FIG. 3 is an example of a pulse width limiting circuit, (A) is a circuit block diagram, (B) is a time chart, and (C) is a pulse width limiting circuit. FIG. 4 is a waveform diagram schematically showing signal waveforms of various parts in the edge detection circuit, and FIG. 5 is a diagram showing an example of a conventional edge detection circuit. FIG. 6A is a circuit block diagram, FIG. 6B is a waveform diagram schematically showing signal waveforms at various parts, and FIG. 6 is a schematic waveform diagram for explaining a problem. DESCRIPTION OF SYMBOLS 1... Edge detection circuit 3... High-pass filter 4... Double-wave rectification circuit 5... Comparison means 7 and 8.

Claims (1)

(57) [Claims] A high-pass filter for extracting a high-frequency component of an input signal; a double-wave rectifier for performing dual-wave rectification on a signal from the high-pass filter; and a signal level output from the dual-wave rectifier. Comparing means for judging whether or not the input signal is an edge portion by comparing with a reference value and obtaining a binarized signal corresponding to the judgment result; and the binarized signal, and a delay of the binarized signal. An edge detecting circuit comprising: a signal generating unit that generates a signal having a substantially continuous level as a binarized signal indicating an edge by synthesizing the signal with the signal.