JP2984591B2 - Timer counter counting method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a counting method for a timer counter, and more particularly to a counting method for a timer counter incorporated in a microcomputer.

[0002]

2. Description of the Related Art Conventionally, as a method of detecting the passage of an arbitrary time in microcomputer software, first, a timer counter built in the microcomputer counts the time, and an interrupt signal is generated when a specified time is counted. Thus, there is a method of detecting the elapse of a designated time.

FIGS. 4 (a) and 4 (b) are a flowchart of a main module process and a flowchart of a timer interrupt process, respectively, in a conventional process for counting an arbitrary time by the built-in timer counter. As shown in FIG. 4A, this processing flow is such that when the processing 2 is executed every 10 ms, the built-in timer counter is set to 10 m in the main module.
The time of s is set, the built-in timer is activated, and then the interruption of the timer counter is permitted. Thereafter, as shown in FIG. 4B, when an interrupt signal of the built-in timer counter is generated, the process 2 is executed in the timer interrupt module.

As a second method of detecting the passage of time, a flag internally set by a microcomputer is monitored by a main process when the timer counter has counted a designated time without using the above-mentioned interrupt signal. There is also a method of detecting the elapse of a designated time by waiting for the set time to be set to 1.

FIG. 5 is a flow chart of a main module process in the counting process of an arbitrary time by such a built-in timer counter. As shown in FIG. 5, this processing flow is a flow in the case where the processing 2 is executed every 10 ms, similar to the processing flow of FIG. 4 described above, but is performed without using a timer interrupt. First, the main module sets an internal timer counter to 10 ms,
Start the built-in timer. Then, if the timer counter is 10
After counting ms, a flag that is set internally is monitored, and if this flag is kept cleared to 0, processing 2
, And if set to 1, the process 2 is executed. In this method, no interrupt processing is required.

The method shown in FIG. 5 has no problem when applied to a small system. However, recently, a microcomputer system has become large-scale and requires a plurality of types of timer counters for a plurality of uses. It is becoming.

[0007] However, since the microcomputer usually has about one to three timer counters, the method of allocating one built-in timer counter to one use as described above makes the number of timer counters insufficient. Therefore, it is common to use a software timer that creates a reference time by one built-in timer counter, divides this reference time by software, and counts a plurality of types of times.

In this method, a counter is allocated to a RAM, and the RAM counter is counted up or down every reference time (for example, 10 ms). Allocate one RAM for one application (5
0 uses 50 RAMs), a value corresponding to the time to be counted (reference time is 10 ms, 4
When counting 0 ms, the basic processing is to set 4) as a software timer and count all software timers with a timer interrupt generated every reference time. Here, as described above, when the reference time is set to 10 ms and a short time of 2.55 seconds (= 10 ms × 255) or less is counted as an example, the maximum count value is 2
55 is sufficient, and the RAM area only needs to be 8 bits long. If it is 16 bits long, it takes about 10 minutes at maximum (about 1 minute).
0 ms × 65535).

FIGS. 6 (a) to 6 (c) show a main module processing flow chart and a processing module 2 for performing an arbitrary time counting process using a conventional software timer.
FIG. 3 is a flowchart of the processing of FIG. As shown in FIG. 6A, in this processing flow, in the processing module 2 called from the main module, the processing 2 and the processing 3 are performed after a predetermined time counted by the software timer has elapsed. This processing module 2 is activated only under certain conditions, as shown in FIG.
Also, as shown in FIG. 6C, all the software timers count in a module of a built-in timer interrupt generated every 10 ms.

First, in the main module shown in FIG. 6A, the built-in timer is set to 10 ms, the built-in timer is started, and then the interrupt is enabled. Then, based on the count result of the software timer, the starting condition of the processing module 2 that performs the predetermined processing is determined. If the starting condition is observed, the 250 ms timer (250 ms = 10 m4 × 25 is used from the RAM). Counter is set to 25) and 1 minute timer (1 minute = 10 ms × 60)
(From 00 to 6000).

On the other hand, with a reference timer interrupt generated every 10 ms, the built-in timer interrupt module shown in FIG. 6C counts down the RAM of the 250 ms timer and the RAM of the 1 minute timer. In the processing module 2 shown in FIG. 6B, if the counter of the RAM of the 250 ms timer is 0, it means that 250 ms has elapsed.
Processing 2 shown in FIG. 6B is performed. Similarly, if the counter of the RAM of the one-minute timer is 0, it means that one minute has elapsed, and the process 3 shown in FIG. 6B is performed.

In this example, an example is shown in which only two software timers are used. However, no matter how many software timers are used, as in the processing examples of FIGS. The software timer is counted by the built-in timer interrupt module.

Next, an example in which the software timer is specifically used in an air conditioner system will be described. In the software of the air conditioner system, about 50 timers for several seconds to several tens of minutes are required for the thermostat control of the room temperature, the high pressure control of the refrigerant, and the start / stop control of the compressor.

FIGS. 7 (a) to 7 (c) show a main module processing flow diagram, a room temperature control module processing flow diagram, and a built-in timer interrupt module processing flow, respectively, in a case where the counting of an arbitrary time by a conventional software timer is applied to an air conditioner system. FIG. As shown in FIG. 7 (a), when using such a software timer for room temperature control, the main module activates a built-in timer and permits an interrupt, then determines whether to start the compressor, and activates the compressor. Then, 2 minutes (2 minutes = 10 ms × 12000 to 12000) are set in the software timer, and the room temperature control module is started.

Next, as shown in FIG. 7 (b), the room temperature control module monitors the expiration of the two-minute timer, and if the two-minute timer has expired, turns on the room temperature thermo and returns. I do. On the other hand, as shown in FIG. 7C, the two-minute timer counts down every 10 ms by the reference time interrupt module of the built-in timer, and finally returns to the main module.

However, when the above-mentioned software timer is used like a one-shot timer (measures a predetermined time only once from a certain time), when the counting is completed (in the case of a down counter, the counter is reset to 0). In some cases, the counting operation is stopped, or under certain conditions, the counting operation is temporarily suspended. In such a case, information for determining whether or not the counting operation may be performed is required for each software timer. Further, when software timers having various bit lengths are present, the method of determining the time-up on the module side (the processing module 2 in the example of FIG. 6 described above) differs from one another.

For example, an instruction for judging whether the counter is 0 is different between an 8-bit software timer and a 16-bit software timer, and the module for judging time-up (processing module 2 in the example of FIG. 6) May be complicated.

Then, for each software timer,
If you add information indicating whether the time is up,
The processing on the module side for determining the time-up is only to check the flag, so that it is common regardless of the bit length of the software timer. In order to generate this time-up information, it is necessary to determine whether or not the counter is 0 on the interrupt processing side (internal timer interrupt module in the example of FIG. 6) of the reference timer that counts the software timer. Since the determination process is also required when creating the information of the counting operation stop when the above-mentioned counter becomes 0, it can be shared.

In view of the above, an example has been proposed in which the counting method of the software timer shown in FIG. 6 is further developed. That is, as the configuration of the software timer, not only the counter portion, but also a software timer having time-up information of the software timer and count permission / prohibition information is realized.

Next, the configuration and operation of such a software timer will be described with reference to FIGS.

FIG. 8 is a diagram showing a timer area configuration of one conventional software timer. As shown in FIG.
Each software timer 10a includes a counter 11a having a plurality of bits, a count enable flag 13a having a 1-bit configuration, and a time-up flag 12a having a 1-bit configuration.
And is formed with. This software timer 10a
Is used as a time-up flag 12a for each software timer to indicate whether or not the timer has timed out, and to indicate permission / inhibition of the count operation of the software timer 10a,
Similarly, one bit of the RAM is used as the count permission flag 13a. Then, the counter 11a is allocated to the RAM at a rate of one for one application similarly to the software timer described above.

One such software timer 10
Referring to FIG. 9A and FIG. 10, a description will be given of a counting method for counting a time of 40 ms by using a specific 8-bit microcomputer as an example. Note that the processing step numbers in FIGS. 9 and 10 correspond to each other.

FIG. 9 is an explanatory diagram of the counting operation using the software timer in FIG. 8, and FIG.
10D is a main processing flowchart for explaining the counting operation of FIG. 9, a software timer initialization processing flowchart of the processing module 3, a built-in timer interrupt processing flowchart, and a processing flowchart of the processing module 3.

First, as shown in FIG.
3a and 12a represent the counter 11a and the flags 13a and 12a of the software timer 10a in FIG. 8, respectively, and show the processing steps S11, S13 to S16, S18,
S19 represents the processing steps in FIGS. 10 (b) and 10 (c).

10 (a) to 10 (d), the main processing shown in FIG. 10 (a) is executed when the starting condition of the processing module 3 shown in FIG. 10 (d) is satisfied.
A software timer initialization processing flow of the processing module 3 shown in FIG. This processing module 3
In the software timer initialization process, the count value 4
(40 ms = 10 ms × 4) is set in the counter, and FIG.
The count permission flag 13a is set, and the processing step S11 of FIG. 9, that is, the step S11 of FIG.
The counter is enabled as shown in (1). In addition, when a software timer is used in addition, it is usual that the initial setting is performed at a necessary place.

On the other hand, in the internal timer interrupt processing generated every 10 ms shown in FIG. 10C, the count permission flag 13a shown in FIG.
(If the counting operation is permitted), the counter 11a of the software timer 10a is counted down as in S13 of FIGS. 9 and 10.

Next, in order to determine the time-up of the software timer, it is checked whether or not the counter 11a has become 0 as shown in S17 of FIG. 10C. If this counter is not 0, it means that the timer has not yet timed up. Therefore, in the processing of the next 10 ms built-in timer interrupt in FIG.
4, and the counter 11a counts down again as in S14 of FIG. 10C. Thereafter, as shown in step S20 of FIG. 10C, if there are a plurality of software timers,
The same processing as steps S12 to S17 in FIG. 10C is performed.

As described above, the check of the count permission flag 13a and the subtraction of the counter 11a are performed in step S of FIG.
As shown in steps S13 to S16 and steps S12 to S17 in FIG. 10C, the process is repeated until the counter 11a becomes 0. When the counter 11a reaches 0, the counter shown in FIGS.
As shown in S18 of (c), the time-up flag 12
is set, and the count permission flag 13a is cleared and the count is disabled, as shown in step S19 of FIGS. 9 and 10 (c). When there are a plurality of software timers, as shown in step S20 of FIG. 10C, the processes of steps S12 to S19 of FIG.

Further, in the processing module 3 of FIG. 10D called from the main processing in FIG. 10A, the time-up flag 1 of the corresponding software timer 10a is set.
2a is checked, and when the flag 12a is set, it means that 40 ms has elapsed, as shown in step S21 of FIG. 10D, so that the time-up flag shown in step S22 of FIG. 10D is cleared. And the processing 4 in step S23. Conversely, if the time-up flag is not set, it means that 40 ms has not elapsed,
The clearing of the time-up flag and the processing 4 are not performed.

[0030]

In the conventional software timer counting method described above, at least five instructions per software timer in the internal timer interrupt processing at time-up [Steps S12 to S12 in FIG. S
In the case of processing 19, assuming that one processing is one instruction]
Therefore, the greater the number of software timers, the greater the number of instructions to be executed, and the longer the interrupt processing time of the built-in timer.

In this counting method, the time during which another interrupt process of the same system that occurs during the software timer counting process is suspended is considerably long. That is, the processing time spent when one software timer times out is, as described above, 5 instructions = about 10 instructions.
μs (when one instruction is 2 μs). Assuming that 30 software timers have timed out due to the built-in timer interrupt currently being performed, 10 μs × 30 = 3
The processing of 00 μs takes time.

For example, in a fan motor control of an indoor unit and an outdoor unit of an air conditioner, in the case of a system in which a phase signal from a motor is fetched by an interrupt process, an interrupt process of the phase signal generated immediately after the start of the count process of the software timer is accepted for 300 μs. This results in a delay, which greatly affects the rotation control of the motor. In this case, the phase signal is used to change the rotation speed of the motor smoothly or to maintain a constant speed by recognizing the current phase shift from the previous motor rotation phase, This is an input signal to the microcomputer when determining the voltage (the rotation speed of the motor). Normally, the time difference between the phase signal and the previous signal is calculated by measuring the time between the signals using a built-in timer.

As described above, the air conditioner system requires about 50 software timers. In addition, the number of software timers that are timed up by one built-in timer interrupt varies depending on the timing. If half of the 30 software timers have timed out at a certain timing, the software , The detection of the phase signal is delayed by a maximum of 300 μs. In addition, the phase signal from the fan motor of the air conditioner is 1 ms
In some cases, the phase signal is input at about a period, and the deviation of the phase signal detection of 300 μs corresponds to about 30% of one period. Therefore, even if the motor is to be rotated at a constant speed, the next rotation speed will be 1.3 times faster, and the accuracy of the rotation speed control will be greatly reduced. That is, the fact that the detection of the phase signal is delayed is because the rotation speed of the motor is recognized as being lower than the actual speed, so that software processing is performed to rotate the motor at a speed higher than the really necessary speed.

Therefore, the feedback control such as the speed control of the fan motor of the air conditioner (the rotation speed of the motor is controlled by the output such as the current and voltage on the control side, and the signal that the motor rotates and returns to the control side) In the feedback control that determines the next output to the motor on the control side, if errors occur continuously in the speed detection (phase signal detection in the example of an air conditioner), motor control becomes impossible, and in the worst case, The motor continues to rotate at a speed higher than its maximum rating, that is, a current that exceeds the maximum rating or a voltage continues to be applied to the motor. In such a case, the operation of the motor is not guaranteed,
There is a disadvantage that the motor is sometimes destroyed and the air conditioner stops functioning.

Further, in the above-described conventional method of counting a timer counter such as a software timer, the number of times that the software timer has
Although it is assumed that the number is zero, if the number becomes 35, 40, or 45, it goes without saying that the above-mentioned situation becomes worse.

An object of the present invention is to simplify the processing when the time of the counter is up, to increase the idle time of the CPU so that there is a margin in the processing time of the entire system, and to reduce the program size of the timer counting processing. It is an object of the present invention to provide a counting method of a timer counter.

[0037]

According to the counting method of the timer counter of the present invention, an interrupt is generated at a predetermined cycle, and the value of the timer counter area provided on the storage area is counted up or down by the interrupt. In counting the time, when a predetermined value is counted, a flag is set in a flag area provided on the storage area. Are provided in a continuous storage area, and the bit data of the flag area is provided in an upper bit area of the bit data of the timer counter area, and the flag and the bit data of the timer counter are counted as a continuous timer counter area at the time of counting. Up or counsel Configured to down processing.

In the counting method of the timer counter according to the present invention, one bit of the flag area is provided as a time-up flag in an upper bit of the counter area.

Further, in the counting method of the timer counter according to the present invention, one bit of the flag area is provided as a count permission flag in an upper bit of the counter area.

In short, the present invention solves the conventional problem that the number of instructions to be executed increases as the number of software timers increases, and the interrupt processing time of the built-in timer increases. This specifies how the counter, time-up flag, and count permission flag are allocated to the RAM. The time-up flag and the count permission flag are controlled by the overflow or underflow of the counter, and the upper bits of the counter area are used to specify these times. An up flag and a count permission flag are assigned.

[0041]

Next, an embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a configuration diagram of a timer area of a software timer for explaining an embodiment of the present invention.
As shown in FIG. 1, this embodiment shows a software timer 10 used for an 8-bit microcomputer, and one byte of RAM is provided for each software timer.
Is assigned. That is, the 6-bit counter 11 is assigned to bits 0 to 5, the time-up flag 12 indicating that the timer has expired is assigned to bit 6, and the count enable flag 13 indicating whether the count of the software timer 10 is enabled / disabled is assigned to bit 7. It is a thing. In the present embodiment, such a software timer 1
When 0 is used and the reference time is 10 ms, 40 ms
FIG. 6 shows a counting method for counting the time.

FIG. 2 is an explanatory diagram of the counting operation using the software timer in FIG. 1, and FIGS. 3 (a) to 3 (d)
3 is a main processing flow diagram for explaining the counting operation of FIG. 1; a software timer initialization processing flow diagram of the processing module 1; a built-in timer interrupt processing flow diagram; and a processing flow diagram of the processing module 1. FIG. 2 corresponds to FIG. 9 of the conventional example described above, and FIG.
(A) to (d) correspond to FIGS. 10 (a) to (d).

First, in the main processing of FIG.
When the activation condition of the processing module 1 in FIG. 3D is satisfied, the software timer initialization processing of the processing module 1 shown in FIG. 3B is called. In the software timer initial setting processing of the processing module 1, a value obtained by subtracting -1 from a value (40 ms = 10 ms × 4) corresponding to the time to be counted, that is, 3, is set in the counter 11, and the counter shown in FIGS. As shown in processing step S1, the count permission flag 13 is set (to a count permission state). If other software timers are used, their initial settings are made at necessary places.
Here, the reason why the value corresponding to the time to be counted is decremented by one is that the time-up is determined by the counter 11a in FIG. This is to determine the time-up by utilizing the overflow of the counter 11.

Next, in the interrupt processing of the built-in timer shown in FIG.
If it is set (if the count operation is permitted) as in the processing step S2 of (c), the processing step S2 of FIG.
As described in 3, the counter of the software timer 10 is set to -1
I do. In the above-described conventional counting method, it is checked whether or not the time has elapsed (whether or not the counter has become 0). However, in the present embodiment, this check is not performed.

Thereafter, the processing step S7 of FIG.
As shown in (1), when there are a plurality of software timers 10, the same processing as the processing steps S2 to S7 is continuously performed on the software timer.

Subsequently, as shown in the processing step S4 in FIG. 2 and FIG. 3C, the counter 11 counts down again by the next built-in timer interrupt. This subtraction is shown in FIG.
As shown in processing steps S3 to S6 in FIG.
As shown in the processing step S6 in FIG. 2, the value of the counter 11 overflows, and the count permission flag 13 is actually cleared and the time-up flag 12 is set. Similarly, as shown in processing step S7 of FIG. 3C, when there are a plurality of software timers, the number of processing timers of FIG.
Repeat steps 2 to S6.

Further, as in step S8 shown in FIG. 3D, in the processing module 1 called from the main processing, the time-up flag 12 of the corresponding software timer 10 is checked, and if the flag 12 is set. , 40 ms have passed, and FIG.
As shown in steps S9 and S10 of (d), the time-up flag is cleared and processing 1 is performed. Conversely, if the time-up flag 12 is not set, the clearing of the time-up flag 12 and the processing 1 are not performed because 40 ms has not elapsed.

In the counting method of the software timer according to the present embodiment, as shown in the processing step S6 of FIG. Even if the permission flag 13 is not cleared, the count is prohibited (cleared) when the time is up.

In the above description of the counting method of the software timer, the case of the 8-bit microcomputer has been described as an example. However, the number of bits of the microcomputer CPU is 4 bits, 16 bits, 32 bits, and the like. Needless to say, the same method can be applied even in the case of the above.

In an application example using the counting method of the software timer, there is no difference from the method described in the prior art described above. That is, this corresponds to the main module of FIG. 6 (a) and FIG.
That is, a software timer can be realized by a processing algorithm similar to that of the processing module 2. In addition, as a specific example, even when applied to an air conditioner system, a software timer can be applied with a processing algorithm similar to that of FIG. 7 described in the related art.

Further, in the present embodiment, the counter 11
When the time-up flag 12 is assigned to the bit immediately above and the count enable flag 13 is assigned to the bit immediately above the time-up flag 12, but the way of assigning the time-up flag 12 and the count enable flag 13 is reversed. However, the side that refers to this flag [for example, FIG.
3 (d), the logic (1/0) of the time-up flag 12 and the count permission flag 13
Is interpreted in reverse, and the software timer can be controlled in exactly the same procedure as in FIGS. 2 and 3 in the present embodiment.

Further, in this embodiment, an example has been described in which the counter areas 11 to 13 are down-counted. However, even in the case of up-counting, the software timer can be controlled in the same procedure as the processing flow of FIG. . In this case, the two's complement of the value to be counted in the counter areas 11 to 13 (the value obtained by inverting the bit to be counted and adding +1)
Should be initialized. For example, if you want to count 1, FFH (hexadecimal F
If F) is set, the value of the counter areas 11 to 13 becomes 00H when counting is performed once, and the value of step S6 in FIG.
As shown in the figure, the logic of the time-up flag 12 (1 /
0) is in the opposite state. In this case, the side that refers to this flag [for example, the processing module 1 in FIG.
The logic (1/0) of the time-up flag 12 may be interpreted in reverse and used. At this time, the value of the counter 11 in step S6 in FIG.
Since the value of the counter 11 in step S6 at time-up is not used, there is no problem at all.

As described above, as long as the time-up flag 12 and the count permission flag 13 are arranged in the upper bits of the counter 11, the arrangement order of the time-up flag 12 and the count permission flag 13 in this embodiment is not limited. And the case where it is arranged upside down.
The street is conceivable. As for the counting method of the counter areas 11 to 13, two kinds of realization are possible, that is, the case of counting down as in this embodiment and the case of counting up.

[0055]

As described above, the counting method of the timer counter according to the present invention, when counting a predetermined value, sets a plurality of flags in the flag area provided on the storage area. The flag area and the timer counter area are provided in a continuous storage area, and the bit data of these flag areas are provided in the upper bit area of the bit data of the timer counter area. Since the count-up or count-down process can be performed as the timer counter area, the time-up judgment that was performed each time the counter of the conventional software timer is decremented, the setting of the time-up flag that was performed at the time of time-up, and the setting of the count enable flag are performed. No need to clear Come, there is an effect that the processing at the time of time-up can be less than or equal to half of the conventional. In other words, five instructions can be reduced to two instructions, and the processing time can be reduced to half or less. In short, according to the present invention, it is possible to reduce the delay of acceptance of interrupt processing other than the software timer, which has been a problem in the conventional example, to less than half.

For example, in a fan motor control system for an indoor unit and an outdoor unit of an air conditioner as specific examples,
The delay time for accepting the interrupt processing of the phase signal generated immediately after the start of the timer interrupt processing for counting the software timer can be reduced to 150 μs or less in the present invention, compared to 300 μs in the related art. Accuracy can be improved by several steps. This means that the period of the motor phase signal input (motor rotation period)
Is 1 ms, in the conventional method, the ratio of the shift (delay) of the phase signal detection timing by software to the actual phase signal input cycle is about 30% (about 300 μs ÷).
1 ms), but 15% or less (≒
(150 μs ÷ 1 ms). Therefore, the accuracy of the rotation speed control of the motor is improved about 1.2 times.

Further, in the counting method of the present invention, as the number of timers increases, the ratio of the count processing time of the software timer to the processing time of the entire system can be reduced. The effect is that the time can be increased. That is, the processing time of the entire system can be spared, and the time can be allocated to other processing.

Further, as described above, the present invention can reduce the number of instructions to less than half of the conventional one, so that the program size of the software timer counting process can be reduced to less than half of the conventional one.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a timer area of a software timer for describing an embodiment of the present invention.

FIG. 2 is an explanatory diagram of a counting operation using a software timer in FIG. 1;

3 is a flowchart showing a main process for explaining a counting operation in FIG. 1, a software timer initialization process of the processing module 1, an internal timer interrupt process, and a process of the processing module 1. FIG.

FIG. 4 is a flowchart of a main module process and a timer interrupt process in a count process of an arbitrary time by a conventional built-in timer counter.

FIG. 5 is a flowchart of a main module process in a count process of an arbitrary time by a conventional built-in timer counter.

FIG. 6 is a flowchart showing a main module process, a process of a processing module 2, and a built-in timer interrupt module process when performing a count process of an arbitrary time using a conventional software timer.

FIG. 7 is a flowchart showing a main module process, a room temperature control module process, and a built-in timer interrupt module process when an arbitrary time count by a conventional software timer is applied to an air conditioner system.

FIG. 8 is a configuration diagram of a timer area of one conventional software timer.

9 is an explanatory diagram of a counting operation using a software timer in FIG.

10 is a flowchart showing a main process, a software timer initialization process of the processing module 3, an internal timer interrupt process, and a process of the processing module 3 for explaining the counting operation of FIG.

[Explanation of symbols]

 10 Software timer 11 Counter 12 Time-up flag 13 Count enable flag

Claims (3)

(57) [Claims] An interrupt is generated at a predetermined cycle, and when the time is counted by counting up or down a value of a timer counter area provided in a storage area by the interrupt, a predetermined predetermined time is counted. In a timer counter counting method of setting a flag in a flag area provided on the storage area when counting the value, the flag area and the timer counter area are provided in a continuous storage area, and a bit of the flag area is set. Timer counter counting, characterized in that data is provided in an upper bit area of the bit data of the timer counter area, and when counting, the flag and the bit data of the timer counter are counted up or down as a continuous timer counter area. Method. 2. The timer counter counting method according to claim 1, wherein one bit of the flag area is provided as a time-up flag in an upper bit of the counter area. 3. The counting method of a timer counter according to claim 1, wherein one bit of the flag area is provided as a count permission flag in an upper bit of the counter area.