JP2979623B2 - Level shift circuit - Google Patents

Description

The present invention relates to a level shift circuit.

[Conventional technology]

The conventional level shift circuit has an inverter output stage composed of a P-channel MOS transistor 37 and an N-channel MOS transistor 40, as shown in FIG. MOS
Transistors 35 and 36 and N-channel MOS transistor 3
8 and 39, and an inverter 34.

The gates of the N-channel MOS transistors 38 and 39 are supplied with a low-voltage level signal 104 supplied from the inside via the terminal 57 and a complementary signal via the inverter 34, respectively. In this circuit, two N channels
By controlling the MOS transistors 38 and 39, the gate potentials of the opposing P-channel MOS transistors 35 and 36 are changed to obtain a high voltage level signal. Therefore, for the P-channel MOS transistors 35 and 36,
As the N-channel MOS transistors 38 and 39, elements having a considerably high driving force are used. Such a circuit is generally called a complementary level shift circuit.

Conventionally, as in the second conventional example shown in FIG. 5, a level shift circuit for converting a low voltage level signal 106 into a high voltage level signal 107 by a comparator circuit having a bias circuit is also used. . In this circuit,
One of a bias circuit 43 including P-channel MOS transistors 41 and 42, a constant current source of N-channel MOS transistors 49 and 50, and a comparator circuit including a current mirror circuit including P-channel MOS transistors 44 and 45. as the input is an input low voltage level signal 106 from the interior, the other input of the predetermined reference voltage V _r from the terminal 58 is inputted. In this case, the voltage level V of the low voltage level signal 106 input via the terminal 60
_A high voltage level is obtained when _b is lower than the reference voltage _Vr .

FIGS. 6 (a), (b) and (c) show:
FIG. 11 is a diagram showing output signal waveforms for a low voltage level signal in the above two conventional examples. FIG. 6 (a) shows the low voltage level signals 104/106 in each conventional example, and FIGS. 6 (b) and (c) show the high voltage level outputs in the second and first conventional examples, respectively. The waveforms of the signals 107 and 105 are shown.

[Problems to be solved by the invention]

In the above-described conventional level shift circuit, in the case of the first conventional example shown in FIG. 4, when the driving capability of the P-channel MOS transistor forming the level shift portion is increased, the gate of the P-channel MOS transistor is increased. It is necessary to further increase the driving capability of the N-channel MOS transistor whose drain is connected to
In the case of this circuit configuration, the configuration of the N-channel MOS transistor has a drawback that a considerably large area is required, and has the following drawbacks.

In the case of the second conventional example shown in FIG.
Since the S transistor is used in the saturation region, the amplification factor for the low voltage level signal 106 is high. Therefore, it is not necessary to increase the size of each MOS transistor, especially the N-channel MOS transistor. There is.

As is apparent from FIGS. 6 (b) and 6 (c) showing the output signal waveforms corresponding to the low voltage level signal input, the case of the first conventional example of FIG. 4 (FIG. 6 (c)) 5), the output signal 105 changes slowly with respect to the input, so that there is a disadvantage that a large through current flows transiently through the output circuit. In the case of the second conventional example shown in FIG. 5 (see FIG. 6 (b)). ) Has a disadvantage that the output signal 107 changes rapidly with respect to the input, but the current flowing constantly is large.

[Means for solving the problem]

The level shift circuit of the present invention is a level shift circuit including: a level shift unit that converts an internal low voltage level signal into a high voltage level signal; and an external output unit that outputs the high voltage level signal to the outside. In a time zone before and after the level signal changes, a timing generation circuit that outputs a predetermined control signal, a plurality of switches that are controlled to a closed circuit or an open circuit in response to the control signal, and the plurality of switches. When the output of the high output level signal is changed in response to the change of the low voltage level signal in accordance with the closed or open state of the switch, the high output level signal is configured as a comparator circuit having a fast response speed. And a level shift unit configured as a complementary level shift circuit during the output value holding period of the level signal.

〔Example〕

Next, the present invention will be described with reference to the drawings. First
FIG. 2 is a circuit diagram of the first embodiment of the present invention. As shown in FIG. 1, this embodiment includes an inverter 1, a reference voltage generation circuit 2, switches 3 to 9, a PMOS transistor
10 to 12, NMOS transistors 13 to 16, and a timing generation circuit 17.

In FIG. 1, in synchronization with the change of the low voltage level signal 101, a predetermined control signal for each switch is generated in the timing generation circuit 17 and transmitted to each switch at the corresponding timing. When the control signal is at the L level, the switches 4, 6, 7 and 9 are controlled to be open and the switches 3, 5 and 8 are controlled to be closed. In this embodiment, the comparator circuit is the same as the conventional one, and the response to the input of the low voltage level signal is fast.

Therefore, the control signal output from the timing generation circuit 17 is set to the L level in an appropriate time zone before and after the low voltage level signal changes. When the control signal is at the H level, the switches 4, 6, 7, and 9 are closed, and the switches 3, 5, and 8 are open. Through the operation of this switch, this circuit configuration is equivalent to the above-described complementary level shift circuit, and the response speed to the input is slow, but no steady current flows.

Therefore, when an output signal is changed in response to a change in an input signal, a comparator circuit having a high response speed is formed, and a complementary level shift circuit is formed during an output value holding period.

In the configuration of the present invention, since the complementary level shift circuit is used only during the output value holding period, it is necessary to increase the driving capability of the N-channel MOS transistors with respect to the P-channel MOS transistors 10 and 11. However, when the same driving capability is obtained, the required occupation area of the MOS transistor may be small. Also, each switch is used for transmitting potential and the current flowing is small, so the minimum design size of MO
It can be configured by an S transistor or the like.

2 (a), 2 (b) and 2 (c) are diagrams showing signal waveforms at various parts in the present embodiment, and FIG.
The input signal 101 input from 51, FIG.
3 shows the control signal including the H level and the L level output from the timing generation circuit 17. In addition,
_Vb is the voltage level of the low voltage level signal 101, and _Vr is the reference voltage input from the terminal 52.

Next, a second embodiment of the present invention will be described. Third
The figure is a circuit diagram of the second embodiment. As shown in FIG. 3, this embodiment includes an inverter 18 and a reference voltage generation circuit.
19, switches 20 to 26, PMOS transistors 27 to 29,
It comprises NMOS transistors 30-33.

The difference of the present embodiment from the above-described first embodiment is that, in the first embodiment, the signal input to the gate of the N-channel MOS transistor 16 forming the output section via the switch 8 is: N-channel but only the reference voltage V _r which is input from the terminal 52, in the case of the embodiment, to form an output section
The input signal from the input terminal 54 and the reference potential input from the terminal 55 are switched and input to the gate of the MOS transistor 33 via the two switches 25 and 26, respectively. . Also, N-channel MO
Care is taken so that a voltage higher than the internal low voltage level signal is not applied to the gate of the S transistor 33. In general, when the potential difference between the source and the gate of the N-channel MOS transistor is increased, the counter pressure between the source and the drain is reduced. Thus, it is possible to convert to an output signal of a higher high voltage level.

〔The invention's effect〕

As described above, according to the present invention, in a basic configuration including a comparator circuit and a level shift circuit, the advantages of these two circuits are taken into consideration, and these circuits are appropriately used properly to increase the circuit configuration. There is an effect that can be prevented.

[Brief description of the drawings]

FIGS. 1 and 3 are circuit diagrams of first and second embodiments of the present invention, respectively, and FIGS. 2 (a), (b) and (c) show respective parts of the first embodiment. FIGS. 4 and 5 are circuit diagrams of a conventional example, and FIGS. 6 (a), 6 (b) and 6 (c) are signal waveform diagrams of respective parts in the conventional example. In the figure, 1,18,34 ... inverter, 2,19 ... reference voltage generating circuit, 3-9,20-26 ... switch, 10-12,27-2
9,35-37,41,44-46 ...... PMOS transistor, 13-16,30
~ 33,38 ~ 40,42,47 ~ 50 ... NMOS transistor.

Claims (1)

(57) [Claims] 1. A level shift circuit comprising: a level shift unit for converting an internal low voltage level signal into a high voltage level signal; and an external output unit for outputting the high voltage level signal to the outside, wherein the low voltage level signal is A timing generation circuit that outputs a predetermined control signal in a time zone before and after the change, a plurality of switches that are controlled to be in a closed state or an open state in response to the control signal, and a closed state of the plurality of switches. Or depending on the state of the open circuit,
When the output of the high output level signal is changed in response to the change of the low voltage level signal, the circuit is configured as a comparator circuit having a fast response speed, and the comparator circuit is complementary in the output value holding period of the high output level signal. And a level shift unit configured as a type level shift circuit.