JP2978872B2 - Online repair device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an online repair device, and more particularly to an online repair device for preventing a malfunction when replacing an electronic circuit package used in a computer device.

[0002]

2. Description of the Related Art Generally, an online repair device is provided to prevent a malfunction of a connected electronic circuit package when the electronic circuit package, which is a maintenance unit, is connected to a back panel such as a motherboard.

Conventionally, in this online repair device, a connection is provided with a sequence by changing the length of a contact in the insertion / removal direction with respect to a connector on a back panel, and a power supply supplied to an electronic circuit package inserted into the back panel is provided. By providing a time lag to the signal, maintenance and replacement of the electronic circuit package in an online state is enabled.

However, according to this method of changing the length of the contact in the insertion / removal direction with respect to the connector to provide a sequence of connection, chattering occurs or the time of insertion / removal when the electronic circuit package is not smoothly inserted / removed. In such a case, a sudden change in signal level may cause a failure, which may adversely affect an operating electronic device.

In order to solve this problem, Japanese Patent Laid-Open Publication No. 1-1
The method disclosed in Japanese Patent No. 12415 includes a power supply module that independently supplies power to an electronic circuit package included in an electronic device. In this case, the power supply module that controls the power supply module goes to a low level before the power supplied from the power supply module drops to the electronic circuit package, and locks the interface circuit in the electronic circuit package. After the supplied power is determined, the power becomes high and the power determination signal for unlocking the interface circuit in the electronic circuit package is transmitted.

As described above, in the conventional method, a power supply determination signal is given from the outside so as not to adversely affect the operating electronic circuit, and a power supply control module is required to generate the power supply determination signal. I have.

As a method of preventing an adverse effect on an operating electronic circuit, for example, Japanese Patent Application Laid-Open No. 60-14 / 1985
There is a power-on reset circuit disclosed in US Pat. This power-on reset circuit outputs a low level (for example, 0 V) when the voltage falls below a predetermined voltage and prevents the CPU (central processing unit) from malfunctioning when the power is turned on. It is configured to output a high level (for example, 5 V).

FIG. 14 is a timing chart showing a reset operation by a conventional power-on reset circuit. In FIG. 14, (a) is a diagram showing a change over time of the value Vcc of the supplied power, and (b) is a diagram showing a change over time of the reset signal output from the power-on reset circuit.

In FIG. 14, when the power is turned on, as shown in FIG. 14A, the value of the power supply value Vcc gradually increases. As the value Vcc of the power supply increases, the reset signal output from the power-on reset circuit also increases. When the value of the power supply Vcc increases and reaches a predetermined threshold value V1 (time t21), the output of the power-on reset circuit goes low. The power-on reset circuit maintains the low level for a predetermined time after the power-on reset circuit is reset, that is, from time t21 to time t22.

At time t22 after the lapse of the predetermined time, the output of the power-on reset circuit goes high, so that the CPU (not shown) starts operating. afterwards,
When the value Vcc of the power supply decreases and becomes equal to or less than the preset threshold value V1 (time t23), the output of the power-on reset circuit goes low, and the value of the value Vcc of the power supply further decreases to a preset value. When V2 (V1> V2), the output of the power-on reset circuit becomes the same as the power supply value Vcc,
As the value Vcc of the power supply decreases, the output of the power-on reset circuit also decreases (time t23 to t24 in FIG. 14).

As described above, in the conventional method, the power-on reset circuit outputs a low level for a predetermined time after the power is turned on, for example, until the crystal oscillation circuit is stabilized, thereby stopping the operation of the CPU. Power supply value Vcc
Prevents the CPU from outputting an erroneous signal to another device at the time of rising or falling of the signal.

On the other hand, the reset signal as described above cannot be used in an electronic circuit package. That is, an electronic element without a reset terminal, for example, an SDRAM (Synchronous) which is one of clock synchronous memory elements.
s Dynamic Random Access M
emory) may be mounted.

In an apparatus equipped with this SDRAM, FIG.
As shown in FIG. 5A, in the data control LSI 1 and the SDRAMs 2-0 to 2-n, the data line 100 is generally used by being bus-connected. Also, SDR
The AM data line is connected to the master clock input CLK (C
lock), C to determine if the next clock is valid
The output is controlled by three signals of KE (Clock Enable) and DQM (Data Mask) used for controlling the input / output buffer. In order to set the data line to high impedance (Hiz), FIG. As shown, at least two clocks are required after setting CKE and DQM to "1".

[0014]

As described above, some of the conventional online repair devices have a power-on reset circuit as described above, but the power-on reset circuit controls only a change in the value Vcc of the power supply voltage. It is done in. When an electronic circuit package is inserted, a large transient current flows through a connector of the inserted electronic circuit package. In order to prevent the transient current from damaging the connector, a power connector for passing the transient current is provided separately from the signal connector. First, temporarily stop with only the power connector connected, and the transient current is stabilized. At this point, the electronic circuit package is completely inserted.

If the electronic circuit package has not been completely inserted into the connector of the back panel for a long time in a state where the electronic circuit package has been inserted into the power connector of the back panel and only the power supply has been turned on for a long time, during that time, There is a problem that the power-on reset is completed, a guard is not activated when the electronic circuit package is inserted into the connector on the back panel, and the electronic device including the electronic circuit package may malfunction.

Some of the conventional online repair devices include a power supply module. In order to prevent any adverse effect on the operating electronic circuit, the lock of the interface circuit in the electronic circuit package is controlled. The power supply determination signal is supplied from the outside, and a power supply control module is required to generate the power supply determination signal. Power control modules are generally large compared to electronic circuit packages. In addition, a power supply control module for generating a power supply determination signal is required for each electronic circuit package to be subjected to online repair.

Accordingly, in order to perform a reliable power-on reset, the power-supply determination signal is reset (ORed) with the output of the power-on reset IC (integrated circuit) in the package. Power supply control modules and switches are required, which leads to an increase in hardware.In addition, when there are a plurality of repair targets, hardware for generating a power determination signal is required for each of the repair targets. There is a problem that costs increase.

On the other hand, in an apparatus using an SDRAM without a reset terminal, when the power connector is inserted and the insertion is stopped in a state where only the power supply is turned on (ON), FIG.
As shown in FIG. 5B, the clock (CL
K) and the control signals (CKE, DQM) are not input and the indefinite state at the time of power-on is maintained, so that the SDRAM may busfight when the online repair is inserted.

Further, in an electronic circuit package on which a large amount of SDRAM is mounted, a high-speed clock is applied to the SDRAM when a signal connector is inserted, so that the current fluctuation increases when the signal connector is inserted, which affects other electronic circuit packages. There is a risk of malfunction due to giving.

The present invention has been made in view of the above circumstances, and has been impossible with the prior art by improving a reset circuit in online repair maintenance.
It is an object of the present invention to provide an online repair device capable of temporarily stopping insertion while a power is on and inserting a signal pin after a current transition period ends.

It is another object of the present invention to provide an online repair device which can omit a power supply control module required for each electronic circuit package to be repaired and perform online repair with only one common power supply. .

A further object of the present invention is to provide an online repair device capable of performing online repair in a power supply system which is supplied with a single storage device using an SDRAM.

[0023]

A first online repair apparatus according to the present invention comprises an electronic circuit mounted on a back panel.
When replacing the road package,
Gives a time difference to the power and signals supplied to the circuit package
To prevent malfunction of the electronic circuit package.
Line repair device, wherein the back panel is
The power supply voltage supplied to the electronic circuit package is at a predetermined threshold.
When the value is exceeded and resetting in the electronic circuit package
Reset integrated circuit
One when a signal is input to the dual reset input terminal
In one case, the reset integrated circuit may cause the electronic circuit
Sends a reset signal to the package,
Reset when the page has been attached to the back panel
Instructs the integrated circuit to cancel the transmission of the reset signal
Then, after instructing cancellation of the reset signal transmission,
After a time the reset signal from the reset integrated circuit
And the power is supplied and
When the clock from the back panel is not supplied,
Clock-synchronous storage element that generates bus fight at input
Clock to the power supply and the back panel.
Generated when the signal from the
Lock of the storage element based on the lock and the reset signal.
Data lines are controlled to be high impedance.
You.

A second online repair device according to the present invention provides a method for replacing an electronic circuit package mounted on a back panel.
At the time of replacement, from the back panel to the electronic circuit package
By giving a time difference to the supplied power and signals,
Online repair device to prevent circuit package malfunction
The electronic circuit package from the back panel.
When the power supply voltage supplied to the page exceeds a predetermined threshold.
A reset signal for sending a reset signal to the electronic circuit package
Means for supplying the power to the electronic circuit package
Sending the reset signal from the reset means in response to
Generating means for generating an instruction signal for instructing exit;
When the mounting of the circuit package on the back panel is completed
The reset signal in response to the instruction signal from the generating means.
Signal to the reset means sending the signal.
Release that outputs a release signal that instructs the release of the default signal transmission
Means, said power being supplied and from said back panel
When no signal is supplied, bus fight with no clock input
The clock to the clock-synchronous storage element causing
Power is supplied and no signal from the back panel
A clock generating means for generating at the time of supply,
The reset signal from the stage and the clock generation means.
Data of the storage element based on the clock generated.
Data to control the data line to high impedance
Control means, wherein the release means outputs the release signal
After a predetermined time from the reset,
The transmission of the reset signal is canceled.

A third online repair device according to the present invention provides a method for replacing an electronic circuit package mounted on a back panel.
At the time of replacement, from the back panel to the electronic circuit package
By giving a time difference to the supplied power and signals,
Online repair device to prevent circuit package malfunction
The electronic circuit package from the back panel.
When the power supply voltage supplied to the page exceeds a predetermined threshold and
Sends a reset signal into the electronic circuit package.
Manual reset input of reset integrated circuit to indicate
When either of the signals is input to the force end,
Reset from the integrated circuit to the electronic circuit package
The electronic circuit package.
When the mounting on the panel is completed, the reset integrated circuit
Instructs cancellation of the transmission of the reset signal,
After a predetermined time from the instruction to cancel the signal transmission, the reset
Release of the reset signal from the reset integrated circuit
With the power supplied and the back panel
When these signals are not supplied, the clock synchronous storage element
Generating a clock, the clock and the reset signal
The data line of the storage element is high impedance based on
Control panel to be included in the back panel and
The power supply from the back panel to the electronic circuit package.
And a power connector for supplying power to the back panel.
And between the back panel and the electronic circuit package.
Signal connector that transmits and receives signals
The reset signal is output when the electronic circuit package is connected.
Signal is released.

A fourth online repair apparatus according to the present invention provides a method for replacing an electronic circuit package mounted on a back panel.
At the time of replacement, from the back panel to the electronic circuit package
By giving a time difference to the supplied power and signals,
Online repair device to prevent circuit package malfunction
The electronic circuit package from the back panel.
When the power supply voltage supplied to the page exceeds a predetermined threshold.
A reset signal for sending a reset signal to the electronic circuit package
Means for supplying the power to the electronic circuit package
Sending the reset signal from the reset means in response to
Generating means for generating an instruction signal for instructing exit;
When the mounting of the circuit package on the back panel is completed
The reset signal in response to the instruction signal from the generating means.
Signal to the reset means sending the signal.
Release that outputs a release signal that instructs the release of the default signal transmission
Means, said power being supplied and from said back panel
Clock signal to the clock-synchronous storage element when no signal is supplied.
Clock generating means for generating a lock;
The reset signal from the stage and the clock generation means.
Data of the storage element based on the clock generated.
Data to control the data line to high impedance
Control means; and the back panel of the electronic circuit package.
Generated by the clock generation means when mounting to the
Turn the clock into a normal clock from the back panel
Clock switching means for switching, wherein the release means
The reset is performed a predetermined time after the release signal is output.
Configured to cancel the transmission of the reset signal from the means.
doing.

[0027]

[0028]

In order to solve the above-mentioned problems, an online repair device according to the present invention is provided when a power supply voltage exceeds a predetermined threshold value or when a signal is input to a manual reset input terminal for transmitting a reset signal. IC that outputs a low level as a reset signal for a predetermined period of time
(Integrated circuit) provided in the electronic circuit package, connected to the manual reset input terminal and detecting whether or not the electronic circuit package has been inserted into the back panel, and detecting the insertion of the electronic circuit package with respect to the manual reset input terminal. And a package insertion detecting device for outputting a low level as an instruction signal for instructing release of the reset signal.

Another online repair device of the present invention is an oscillator which is connected only to a power connector when the online repair is inserted, and oscillates at a period slower than a clock of a normal operation when not connected to a signal connector. And a clock supply means for switching the clock from the oscillator to a normal operation clock when the signal connector is connected, and a SIMM (Single Inl) when only the power connector is inserted.
ine Memory Module) PLL (Ph
SIML through-mode control means for switching a circuit to a locked-loop (ase locked loop) circuit to a normal PLL mode when a signal connector is inserted, and an SDRAM (Sy) for a predetermined time when power is supplied to the electronic circuit package.
nchronous Dynamic Random
Access Memory (CKE)
SDRAM data line control means for setting Enable and DQM (Data Mask) to "1" to make the SDRAM data line high impedance (Hiz).

When only the power connector is inserted and the signal connector is not inserted until the transient current is stabilized, the electronic circuit package is in a state where no clock is input. If a clock is not input to the SDRAM, the portion connected to the bus becomes an indefinite value and bus fight occurs.
The clock supply means supplies a clock to the SDRAM even when the signal connector is not connected, and prevents bus fight of the data line.

When the signal line is connected, the operation is shifted to the normal operation by switching to the clock for the normal operation. Further, a clock in which only the power connector is inserted uses a clock that is slower than a clock in a normal operation in order to suppress a fluctuating current.

The SIMM through mode control means sets the PLL circuit on the SIMM with only the power connector in the through mode. This is because the clock in the state where only the power connector is inserted is slower than the clock in the normal operation, and the PLL circuit does not operate normally. Therefore, the PLL circuit is set to the through mode, and a slow clock can be supplied to the SDRAM. When connected to the signal connector, release the through mode for the PLL circuit,
Supply clock for normal operation.

When the power connector is inserted and the power is turned on, the SDRAM data line control means operates for a predetermined time CKE and DQ.
M is set to “1” and then set to “0” again. As a result, while CKE and DQM are “1”, the bus fight preventing clock generated by the clock supply means is supplied to the SDRAM.
To make the data line high impedance. Further, by setting CKE and DQM to “0” for a predetermined time, the clock switching noise at the time of insertion and the clock of normal operation are not recognized by the SDRAM, so that the fluctuation current at the time of signal connector insertion is suppressed. Power supply noise to other electronic circuit packages can be suppressed.

[0035]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a block diagram showing a schematic configuration of an online repair device according to an embodiment of the present invention. In FIG. 1, reference numeral 10 denotes an electronic circuit package provided with a reset circuit, and reference numeral 20 denotes a back panel having a connector into which the electronic circuit package 10 is inserted. That is, the electronic circuit package 10 is inserted into the connector provided on the back panel 20.

The connector provided on the back panel 20 includes a power connector 22 for supplying power to the electronic circuit package 10, various signals transmitted and received between the back panel 20 and the electronic circuit package 10, and other electronic components. A signal connector 24 for relaying signals transmitted to and received from a circuit package (not shown). That is, power is supplied to the electronic circuit package 10 from the back panel 20 via the power connector 22.

The electronic circuit package 10 detects power supply terminals 11a and 11b into which the power connector 22 is inserted, signal terminals 11c into which the signal connector 24 is inserted, and complete insertion into the back panel 20, and performs power-on reset. The circuit 12 has a detection terminal 11 d for canceling the input of a signal to the manual reset input terminal 14 a and a power-on reset circuit 12. The power-on reset circuit 12 sends out a reset signal into the electronic circuit package 10 when the electronic circuit package 10 is inserted into the connector of the back panel 20, and this reset signal causes the internal parts of various electronic components provided in the electronic circuit package 10 to be It controls the operation.

The power-on reset circuit 12 includes a reset IC (integrated circuit) 14, a resistor 16, and a capacitor 1
8 is provided. The above resistor 16 and capacitor 18
Are connected in series, one end of the resistor 16 is connected to the power supply,
One end of the capacitor 18 is grounded.

The connection point between the resistor 16 and the capacitor 18 is connected to the output line 12a of the power-on reset circuit 12 and to the reset IC 14 described above. The reset IC 14 has a manual reset input terminal 14a.
4a is connected to the detection terminal 11d and the pull-up resistor 13 which constitute the package insertion detection device 26.

The package insertion detecting device 26 is provided on the back panel 20 side and has a manual reset input terminal 14.
A connector electrode 26a inserted into the detection terminal 11d connected to the connector a is provided, and the electrode 26a of this connector is grounded. The electronic circuit package 10 has a detection terminal 11d.
Are provided, and the electrode 2 of the connector is provided at a position corresponding to them.
It is also possible to provide a configuration in which two of the detection terminals 11d are grounded and the signal from the electronic circuit package 10 is simply passed through the two electrodes 26a on the back panel 20 side.

Therefore, when the electronic circuit package 10 is inserted into the back panel 20, the connector electrode 26a
Since the low-level signal is input to the manual reset input terminal 14a via the detection terminal 11d, the package insertion detection device 26 can detect that the electronic circuit package 10 has been inserted into the back panel 20.

That is, if the package insertion detecting device 26 does not detect the insertion of the electronic circuit package 10, a high level is supplied to the manual reset input terminal 14 a via the pull-up resistor 13 as an instruction signal for instructing transmission of a reset signal to the input terminal 14 a. When the insertion of the electronic circuit package 10 is detected, a low level is output via the detection terminal 11d as an instruction signal for instructing the manual reset input terminal 14a to release the reset signal.

Next, the characteristics of the reset IC 14 will be described. FIG. 2 is a timing chart for explaining the characteristics of the reset IC 14. In FIG.
(A) is a figure which shows the time-dependent change of the value Vcc of a power supply,
(B) is a diagram showing an output of the reset IC 14,
(C) is a diagram showing an example of a signal input to the manual reset input terminal 14a of the reset IC 14.

The electronic circuit package 10 includes the back panel 2
When the power is supplied by being inserted into the connector No. 0, the value of the power supply Vcc gradually increases as shown in FIG. Reset IC as power supply value Vcc rises
The value of the output of 14 (reset signal) also gradually increases.

When the power supply value Vcc further rises and becomes equal to or higher than the preset threshold value Vt, the reset IC 14 changes its output terminal to low level. After setting the output terminal to low level, the reset IC 14 maintains low level for a certain period (period T1 in FIG. 2), and thereafter maintains the output terminal at high level.

On the other hand, as shown in FIG. 2C, when the manual reset signal to the manual reset input terminal 14a of the reset IC 14 is turned on, the reset IC
Numeral 14 sets its output terminal to low level and maintains the low level while the manual reset signal is being input (period T2 in FIG. 2). When the manual reset signal goes low, the reset IC 14 outputs a predetermined time (period T in FIG. 2) after the manual reset signal goes low.
3), keep its output low, and then set its output high.

As described above, from the reset IC 14, as shown in FIG. 2, a predetermined period T1 after the power supply value Vcc has exceeded the threshold value Vt, a period T2 during which the manual reset signal is input, and For a predetermined period T3 after the manual reset signal becomes low level,
A reset signal will be output.

The operation of the reset signal output from the reset IC 14 when power is supplied to the electronic circuit package 10 from the power connector 22 of the back panel 20 will be described. FIG. 3 is a timing chart for explaining characteristics of the reset IC 14 when power is actually supplied to the electronic circuit package 10. FIG.
3A is a diagram showing a change over time of the power supply value Vcc, FIG. 3B is a diagram showing an output of the reset IC 14, and FIG. 3C is a diagram showing a signal input to a manual reset input terminal 14a of the reset IC 14. It is a figure showing an example of.

The electronic circuit package 10 is mounted on the back panel 2
When the power is supplied by being inserted into the connector No. 0, the value of the power supply Vcc gradually increases as shown in FIG. Reset IC as power supply value Vcc rises
The value of the output of 14 (reset signal) also gradually increases.

When the power supply value Vcc further rises and becomes equal to or higher than a preset threshold value, the reset IC 14 changes its output terminal to a low level. Thereafter, when the value Vcc of the power supply rises to a certain value, the manual reset signal to the manual reset input terminal 14a of the reset IC 14 turns on. The low level is maintained even after the period T1) in FIG.

The reset IC 14 maintains its output at a low level while the manual reset signal is being input. Therefore, the reset IC 14 detects the insertion of the electronic circuit package 10 after the power supply value Vcc becomes equal to or higher than the threshold value, and outputs a manual reset signal to the manual reset input terminal 14a to a low level (reset signal of the reset signal). The output is maintained at a low level until the release instruction is issued (period t0 in FIG. 3).

The reset IC 14 operates for a predetermined time (period t in FIG. 3) after the manual reset signal goes low.
1), the output is kept low, and then the output is made high.

As described above, from the reset IC 14, as shown in FIG. 3, during the period t0 from when the power supply value Vcc exceeds the threshold value Vt until the manual reset signal goes low, and as shown in FIG. The reset signal is output for a predetermined period t1 after the signal goes low.

Next, the connector of the back panel 20 shown in FIG. 1 will be described. FIG. 4 is an enlarged schematic view of the connector of the back panel 20 of FIG. 4, the electronic circuit package 10 and the back panel 2 of FIG.
Members corresponding to 0 are denoted by the same reference numerals.

In FIG. 4, reference numerals 22a to 22c, 24
a, 24b and 26a are attached to the back panel 2
The electrodes of the connector provided at 0 indicate the length of the electrodes in the direction indicated by the symbol ID.

The electrodes denoted by reference numerals 22a to 22c are shown in FIG.
Of the power connector 22 of FIG. Among these electrodes, the electrode 22a is a ground electrode, and the length in the direction indicated by the symbol ID is set to be the longest. Reference numeral 22
The electrodes labeled b and 22c are respectively sub-power sources (for example, -1).
An electrode (SubV) for supplying 2 V) and an electrode (MainV) for supplying main power (for example, 12 V), and the length thereof is set shorter than the length of the electrode 22a.

The electrodes denoted by reference numerals 24a and 24b are electrodes provided in the signal connector 24 shown in FIG. 1, the electrode 24a is a ground electrode, and the electrode 24b is the electrode between the electronic circuit package 10 and the back panel 20. For connecting signal lines for relaying various signals transmitted and received between the electrodes and the electrodes 26
Reference numeral a denotes an electrode for detecting whether or not the electronic circuit package 10 is securely inserted into the back panel 20. The lengths of the electrodes 24a, 24b and 26a are set shorter than the lengths of the electrodes 22a to 22c.
b and the electrode 26a are set to be shorter in this order.

In this embodiment, the connector provided on the back panel 20 is connected to the power connector 22 as described above.
And the signal connector 24 are divided into online repair,
This is because a transient overcurrent flows through the connector particularly when the electronic circuit package 10 is inserted.

That is, since the signal connector 24 is generally vulnerable to a large current, the signal connector 24 is divided into the power connector 22 and the signal connector 24 through which a large current flows to cope with an overcurrent at the time of online repair. It is.

In the above description, the connection between the back panel 20 and the electronic circuit package 10 is made by inserting the electrodes 22a to 22c, 24a, 24b, 26a from the back panel 20 into the electronic circuit package 10. But,
The electrodes from the electronic circuit package 10 are connected to the back panel 20.
May be inserted.

Next, the operation of the online repair device according to one embodiment of the present invention will be described. FIG. 5 is a timing chart for explaining the operation of the online repair device according to one embodiment of the present invention. In FIG.
(A) is a figure which shows the time-dependent change of the value Vcc of a power supply,
(B) is a diagram showing a change over time of the reset signal of the power-on reset circuit 12, (c) is a diagram showing an example of a manual reset signal input to the manual reset input terminal 14a of the reset IC 14, (d) () Is a diagram showing the change over time of the signal on the signal line.

In the online repair according to this embodiment, only the power connector 22 is inserted and the transient current is stabilized, and then the signal connector 24 is inserted.
The time difference between the insertion of the signal connector 24 from the power connector 22 may be on the order of seconds. If the power-on reset is performed only by the change of the power supply voltage as in the related art, the reset guarantee time of the reset IC 14 is Since the time is generally several hundred ms, no reset signal is output when the signal connector 22 is inserted.

In this case, there is a possibility that the inserted electronic circuit package 10 malfunctions due to noise when the signal connector 22 is inserted. In the present embodiment, even if the insertion time difference between the power connector 22 and the signal connector 24 reaches the order of seconds, the reset can be reliably performed.

The electronic circuit package 10 is mounted on the back panel 2
0, the electrode 2 as shown in FIG.
Since the lengths 2a to 22c, 24a, 24b, and 26a are different, only the electrodes 22a to 22c provided on the power connector 22 are in conduction with the electrodes (not shown) provided on the electronic circuit package 10 during insertion. Power is supplied from the back panel 20 to the electronic circuit package 10.

The power supplied to the electronic circuit package 10 changes as shown in FIG. When power is supplied, the value of the power Vcc gradually increases in the initial stage. As the value of the power supply Vcc increases, the reset signal output from the power-on reset circuit 12 also increases.
When the power supply value Vcc becomes equal to or higher than the preset threshold value Vt,
The reset signal goes low.

When the electronic circuit package 10 is in the state shown in FIG. 4, that is, when only the power connector 22 is connected, the output is at a high level because the electrode 26a in the package insertion detecting device 26 is open. .

After the electronic circuit package 10 is inserted into the power connector 22 and until the transient current is stabilized (period t11 in FIG. 5), the signal connector 24 is not inserted. I
When the manual reset signal is output to C14, the reset signal output from reset IC 14 becomes low level (reset state).

When the signal connector 24 is inserted with an interval (on the order of seconds) at which the transient current is stabilized, FIG.
The electronic circuit package 10 is inserted into the back panel 20 until the electrode 26a becomes conductive. When the electrode 26a becomes conductive, the level of the manual reset signal output from the package insertion detecting device 26 becomes low.

When the level of the manual reset signal output from the package insertion detecting device 26 becomes low, the reset IC 14 is turned on for a preset period t12.
The reset signal is maintained at a low level, and thereafter, the reset signal is set at a high level.

FIG. 5D is a diagram showing an example of a signal change when the signal connector 24 is inserted.
As shown in (d), noise occurs during a period t13 after the period t11. The period t13 during which noise occurs is a relatively short period, and the period t13 during which the reset signal is maintained at a low level.
If the time period 12 is made sufficiently short, noise converges before various electronic components provided in the electronic circuit package 10 operate, so that normal operation is performed.

As described above, according to one embodiment of the present invention, the insertion state of the electronic circuit package 10 is detected by the package insertion detecting device 26, and a low level is set as a reset signal in accordance with the insertion state of the electronic circuit package 10. By outputting the signal, the insertion of the signal connector 24 can be stopped until the transient current becomes stable at the time of online repair insertion. Therefore, a complicated sequence and a power supply circuit at the time of online repair can be eliminated.

Further, since power is supplied to the electronic circuit packages 10 via the power connector 22 for supplying power, there is no need to provide a power supply control module corresponding to each of the electronic circuit packages 10, thereby simplifying the apparatus. And cost reduction can be achieved.

Next, an SDRAM (Syn) which cannot use a reset signal, that is, which is one of the electronic devices without a reset terminal, for example, one of clock-synchronous storage devices.
chronous Dynamic Random A
access memory) is an electronic circuit package 10
The case in which it is mounted on a device will be described.

FIG. 6 is a timing chart showing data line control of the SDRAM. In FIG. 6, the SDRAM determines whether the next clock is valid or not by CKE (Clo).
The clock is valid when the (ckEnable) signal is “1”. When a DQM (Data Mask) signal used for controlling the input / output buffer is fetched when the clock is valid, the data line becomes high impedance (H) after 2T.
iz).

FIG. 7 is a block diagram showing a general connection method of the data lines of the SDRAM. In FIG. 7, SDR
AM2-1 to AM2-4 are data control (DATA
CONTROL 1) and a data line 100.

Drivers 2a-1 to 2a-4 and 1a for transmitting and receiving signals to and from the SDRAMs 2-1 to 2-4 and the data control 1 via the data line 100 and receivers 2b-1 to 2b-4. , 1b.

FIG. 8 is a view showing a connector of an apparatus for online repair according to another embodiment of the present invention. 8, the back panel (BP) 4 includes a power connector 41 and a signal connector 42 for connecting to the electronic circuit package (PKG) 3, as in FIG.

The electrode 41a of the power connector 41 is a ground electrode (G), and has the longest pin length. The electrode 41b is an electrode (V) for supplying power, and the length of the pin is set shorter than the length of the electrode 41a.

The electrode 42a of the signal connector 42 is a ground electrode (G), the electrode 42b is an electrode (V) for supplying power, the electrode 42b is an electrode (V) for supplying power, and the electrodes 42c to 42e are electronic circuit packages. These are electrodes (Long, Sig, Short) for connecting signal lines for relaying various signals transmitted and received between the back panel 3 and the back panel 4. Since the lengths of the pins of these electrodes 41a, 41b, 42a to 42e are sequentially shortened, a connection sequence occurs between the power supply and the signal pins during insertion and removal.

Since the signal connector 42 cannot be stopped at a large current, the transient current at the time of insertion is reduced by using the power connector 41 until the transient current is stabilized using the power connector 41.
Stop by inserting only (see FIG. 8). Signal connector 4
2 is inserted when the transient current is stabilized. The pins of the connector for connecting the electronic circuit package 10 and the back panel 20 can be set so that the pins of the electronic circuit package 10 are sequentially shortened.

FIG. 9 is a block diagram showing a schematic configuration of an electronic circuit package 3 according to another embodiment of the present invention. In FIG. 9, a clock supply circuit 31 for controlling clock supply, a through mode control circuit 32, and an SDRAM (Synchronous Dy) are provided in the electronic circuit package 3.
natural Random Access Memor
y) A memory array 33 composed of groups, a normal logic reset circuit 34, and an SDRA for controlling SDRAM data lines.
An M data control circuit 35 and a control LSI (large-scale integrated circuit) 36 are mounted.

The clock supply circuit 31 supplies a pin for supplying a normal operation clock from the back panel 4 [the electrode 42 in FIG.
d pin (Sig)], an oscillator (OSC: Oscillator) 31c that oscillates at a frequency lower than the clock of the normal operation, and an enable control pin for controlling the output of the oscillator 31c [FIG.
31b connected to the pin (Long) of the electrode 42c, the resistors 31d and 43, and the PLL (Phase
Locked Loop) circuit 31e.

The resistors 31d and 43 are provided for controlling the enable of the oscillator 31c.
R1 and pull-up / pull-down. Resistance 3
1d and 43 are R0> R1, and "1" is input to the enable pin of the oscillator 31c until the pin of the electrode 42 is inserted into the connector 31b, and becomes "0" when the insertion of the pin of the electrode 42 is completed. Is controlled. The output of the oscillator 31c is wired to a signal line of a clock for normal operation (a signal line from the connector 31a to the PLL circuit 31e). The clock (S) from the PLL circuit 31e
DRAM CLK) is supplied to the memory array 33.

The through mode control circuit 32 detects that the electronic circuit package 3 has been completely inserted into the back panel 4 [pin (short) of the electrode 42e in FIG. 8).
Is not inserted into the connector 32a, it is pulled up by the resistor 32b to output "1" to the memory array 33. The through mode control circuit 32 includes a resistor 32
b and 44 are provided, and when the resistance values are R2 and R3, as in the case of the clock supply circuit 31, R2
> R3.

The SDRAM data control circuit 35 senses a rise in the voltage when the power is turned on, outputs "0" for a predetermined period, and outputs "1" after a predetermined time, and outputs a reset IC (RST).
IC) 35a (the same configuration as the reset IC 14 in FIG. 1 described above), a resistor 35b, a capacitor 35c, an inverter 35d, an inverted output of the output of the reset IC 35a by the inverter 35d, and C (not shown) in the control LSI 36.
An OR circuit (OR not shown) that takes an OR (OR) with the output of the KE normal logic circuit, OR of the inverted output of the output of the reset IC 35a by the inverter 35d and the output of the DQM normal logic circuit (not shown) in the control LSI 36. And an OR circuit (not shown).

The CKE normal logic circuit of the control LSI 36 is reset when the electronic circuit package 3 is not inserted into the back panel 4 and outputs “0”. When the reset is released, it operates based on the normal control logic. . The DQM normal logic circuit is also reset when the electronic circuit package 3 is not inserted into the back panel 4 and outputs “0”,
When the reset is released, it operates based on the normal control logic.

The reset IC 34a of the normal logic reset circuit 34 for resetting the CKE normal logic circuit and the DQM normal logic circuit has the same characteristics as the reset IC 14 of FIG. 1 described above, and "1" is input to the manual reset input terminal of the reset IC 34a. , "0" is continuously output, and when "0" is input to the manual reset input terminal, "1" is output after a predetermined time.

At this time, a pin for detecting that the electronic circuit package 3 has been completely inserted into the back panel 4 in the connector 32a of the through mode control circuit 32 is connected to the manual reset input terminal [the pin (Shor of the electrode 42e in FIG. 8).
t)], and “0” output from the through mode control circuit 32 when the insertion of the electronic circuit package 3 into the back panel 4 is completely completed is input. This reset IC 34a is not special and is generally commercially available.

The normal logic reset circuit 34 may be provided with an internal configuration of the through mode control circuit 32 exclusively for this circuit. Further, the resistors 43 and 44 provided in the back panel 4 can be provided in the electronic circuit package 3. In this case, a signal from the electronic circuit package 3 is passed through the back panel 4. Good.

FIG. 10 is a block diagram showing a configuration of the memory array 33 of FIG. In FIG. 10, a memory array 33 is a SIMM (Single Inline Mem).
ory Module) 33-1 to 33-m,
Each of the SIMMs 33-1 to 33-m has a PLL inside.
Circuits 33a-1 to 33a-m and a storage element (SDRA
M) 33b-1 to 33n-1, 33b-2 to 33n-
2,..., 33b-m to 33n-m.

Each of the PLL circuits 33a-1 to 33a-m is supplied with a clock (SDRAM CLK) from the PLL circuit 31e of the clock supply circuit 31, and is supplied from the through mode control circuit 32 with a through mode (Toughth mod).
e) is provided. PLL circuits 33a-1 to 33a-m
When a "1" is input from the through mode control circuit 32 when a pin for detecting that the electronic circuit package 3 is completely inserted into the back panel 4 is not inserted into the connector 32a, a clock supply circuit is provided. 31 PLLs
The clock is passed from the circuit 31e and the storage elements 33b-1 to 33n-1, 33b-2 to 33n-2,.
, 33b-m to 33nm.

FIG. 11 is a block diagram showing the configuration of the control LSI 36 shown in FIG. In FIG. 11, the control LSI 36
Are the CKE normal logic circuit 36a and the DQM normal logic circuit 3
6b, and an SDRAM inside thereof.
OR circuits 35e and 34f constituting the data control circuit 35
Are arranged.

CKE normal logic circuit 36 of control LSI 36
a indicates the reset I of the normal logical reset circuit 34 when the electronic circuit package 3 is not inserted into the back panel 4.
It is reset by a reset signal from C34a and outputs "0". When the reset is released, it operates based on normal control logic. When the electronic circuit package 3 is not inserted into the back panel 4, the DQM normal logic circuit 36b also
The normal logic reset circuit 34 is reset by a reset signal from the reset IC 34a and outputs "0". When the reset is released, the circuit operates based on the normal control logic.

The CKE normal logic circuit 36a and DQ
The output of each of the M normal logic circuits 36b is an OR circuit 35e,
Reset IC of SDRAM data control circuit 35 at 35f
The output of the inverter 35a is ORed with the inverted output of the inverter 35d, and the OR result is the CKE signal and the DQM signal, respectively.
The storage elements 33b-1 to 33b-3 of the memory array 33 are used as signals.
3n-1, 33b-2 to 33n-2, ..., 33b-m
~ 33 nm.

FIG. 12 is a timing chart showing the operation of another embodiment of the present invention. In FIG. 12, the power connector 41 and the signal connector 42 of the back panel 4 are shown.
When the electronic circuit package 3 is inserted into the back panel 4, firstly,
The electrodes 41a and 41b (G, V) of the power connector 41 are inserted (at time A and time B in FIG. 12).

At this time, power is supplied to the electronic circuit package 3 from the power connector 41, and a transient current flows through the power connector 41. If the electronic circuit package 3 is inserted into the back panel 4 as it is, a transient current also flows through the signal connector 42 that is weak against large currents. Therefore, the insertion of the electronic circuit package 3 is stopped between the point B and the point C (about several seconds). ).

At the time point B, the oscillator 31c of the clock supply means 31 oscillates, and the clock from the oscillator 31c is supplied to the SIMMs 33-1 to 33-m. The through mode control circuit 32 also outputs “1” at the point B, and the PLL circuit 31 e of the clock supply circuit 31 and the SIMM 33
-1 to 33-m PLL circuits 33a-1 to 33a-
m in the through mode, the storage element 33b-1
~ 33n-1, 33b-2 ~ 33n-2, ..., 33b
The clock is supplied to −m to 33 nm.

When the power is turned on at the point B, the reset IC 35a of the SDRAM data control circuit 35 outputs "0", so that the reset IC 35 is provided to the off circuits 35e and 35f.
The output of "a" is inverted by the inverter 35d and "1" is input. Therefore, CKE from the OR circuits 35e and 35f
“1” is output as the signal and the DQM signal. The above storage elements 33b-1 to 33n-1, 33b-2 to 33
n-2,..., 33b-m to 33n-m
By receiving the KE signal and the DQM signal, the storage element 33b
-1 to 33n-1, 33b-2 to 33n-2, ..., 3
The data lines 3b-m to 33nm (not shown) are initialized to high impedance, and bus fight on the data lines can be prevented.

A predetermined time after the point B (several 100 ms)
), Reset IC of SDRAM data control circuit 35
Since 35a becomes "1", the output of the reset IC 35a is inverted by the inverter 35d and "0" is inputted to the off circuits 35e and 35f. Therefore, the OR circuit 35e,
The CKE signal and the DQM signal from 35f become “0”. However, the storage elements 33b-1 to 33n-1, 33b-
.., 33b-m to 33n-m are initialized to high impedance once, so that the storage elements 33b-1 to 33n-1, 33b-2 to 33n-
2,..., 33b-m to 33n-m, the state of the high impedance does not change unless a command is input.

When the CKE signal becomes "0", the storage element 3
3b-1 to 33n-1, 33b-2 to 33n-2, ...
, 33b-m to 33n-m do not recognize the clock, so that the storage elements 33b-1 to 33n-1, 33b-2 to
33n-2,..., 33b-m to 33n-m consume less current. Storage elements 33b-1 to 33n-1, 33
Since the currents of b-2 to 33n-2,..., 33b-m to 33n-m are proportional to the clock frequency, a low-speed oscillator 31c of the clock supply circuit 31 is used (for example, 5 MHz).

As described above, the storage elements 33b-1 to 33b-1 to 33b-3
3n-1, 33b-2 to 33n-2, ..., 33b-m
When the bus fight of the data line of ~ 33 nm is prevented and the transient current of the power connector 41 is stabilized, the insertion of the electronic circuit package 3 into the back panel 4 is restarted.

At time E, when the enable control pin [pin (Long) of the electrode 42c in FIG. 8] of the back panel 4 is connected to the connector 31b of the clock supply circuit 31, and the output of the oscillator 31c is disabled, The clock stops once. Further, the insertion of the electronic circuit package 3 into the back panel 4 proceeds, and a clock for normal operation (for example, 100 MHz) is given at the time of F. At this time, the output of the oscillator 31c of the clock supply circuit 31 is disabled. There is no bus fight with the clock of normal operation.

Finally, at the point of G, the electronic circuit package 3
Is inserted into the connector 32a of the through mode control circuit 32 when a pin (pin (Short) of the electrode 42e in FIG. 8) for detecting that the is completely inserted into the back panel 4 is inserted.
The output of the through mode control circuit 32 becomes “0”, and the PLL circuit 31 e of the clock supply circuit 31 and the SIMM 33
-1 to 33-m PLL circuits 33a-1 to 33a-
m initiates the PLL lock.

At the time point G, a pin [pin (Short) of the electrode 42e in FIG. 8] for detecting that the electronic circuit package 3 is completely inserted into the back panel 4 is connected to the connector 32a of the through mode control circuit 32. By being inserted, the reset IC 34a of the normal logic reset circuit 34 releases the reset to the CKE normal logic circuit 36a and the DQM normal logic circuit 36b after a predetermined time.
KE normal logic circuit 36a and DQM normal logic circuit 36b
Enters normal operation.

The CKE signal is controlled to “0” from the time when several 100 ms has passed from the time B to the start of the normal logic, and the storage elements 33b-1 to 33n-1, 33b-2 to 33b-2 are controlled.
The clocks to 33n-2,..., 33b-m to 33n-m are suppressed. This is because the high-speed clock when the signal connector 42 is inserted is stored in the storage elements 33b-1 to 33n-1, 33b.
-3 to 33n-2,..., 33b-m to 33n-m, the fluctuation current when the signal connector 42 is inserted is suppressed, and the influence on other packages is prevented.

In the above description, the case where the SDRAM is used as the clock synchronous storage element has been described. However, another embodiment of the present invention is an RDRAM (Rambus Dynamic Random) which is another clock synchronous storage element.
Om Access Memory).

FIG. 13 is a block diagram showing a configuration of an electronic circuit package 3 according to another embodiment of the present invention. FIG.
In 3, the electronic circuit package 3 according to another embodiment of the present invention selects the output of the oscillator 31c of the clock supply circuit 31 and the clock signal of the normal operation (the signal from the connector 31a to the PLL circuit 31e) by the selector 31f. Except for this, the configuration is the same as that of the electronic circuit package 3 according to another embodiment of the present invention shown in FIG. 9, and the same components are denoted by the same reference numerals. The operation of the same component is the same as that of the other embodiments of the present invention.

The selector 31f selects one of the output of the oscillator 31c and the clock signal of the normal operation according to the signal from the connector 31b connected to the pin (Long) of the electrode 42c in FIG. That is, when “1” is input until the pin of the electrode 42 is inserted into the connector 31b, the selector 31f selects the output of the oscillator 31c. When the insertion of the pin of the electrode 42 is completed and “0” is input, the selector 31 f selects the clock signal of the normal operation.

[0109]

As described above, according to the present invention,
Detecting means that can know the insertion state of the electronic circuit package is provided, and a low level is output when the electronic circuit package is inserted, so that the signal connector is inserted until the transient current is stabilized during online repair insertion. Can be stopped. Therefore, there is an effect that a complicated sequence and a power supply circuit at the time of online repair can be eliminated.

Further, since power is supplied to the electronic circuit package via the connector for supplying power, it is not necessary to provide a power supply module corresponding to each electronic circuit package, so that the apparatus is simplified and the cost is reduced. There is an effect that can be achieved.

Further, even when only the power supply is turned on and the signal pins are not connected in the electronic circuit package inserted in the online repair, a clock is generated by the internal oscillator and supplied to the SDRAM to control the data lines. Therefore, only the power supply during the online repair transition period is turned on, and there is an effect that a bus fight between SDRAMs in a state where a clock is not turned on can be prevented.

Further, after the bus fight of the SDRAM is suppressed, the CKE signal is set to “0”, so that
By suppressing the high-speed clock entering the DRAM,
There is an effect that it is possible to suppress a fluctuating current when a signal connector is inserted into an electronic circuit package on which a large number of SDRAMs are mounted.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of an online repair device according to an embodiment of the present invention.

FIG. 2A is a diagram showing a change over time of a power supply value Vcc;
2B is a diagram illustrating an output of the reset IC of FIG. 1, and FIG. 2C is a diagram illustrating an example of a signal input to a manual reset input terminal of the reset IC of FIG.

3A is a diagram showing a change with time of a power supply value Vcc when power is actually supplied to the electronic circuit package of FIG. 1, and FIG. 3B is a diagram showing a change over time of the electronic circuit package of FIG. FIG. 3C shows an output of the reset IC when power is actually supplied, and FIG. 3C shows an input to a manual reset input terminal of the reset IC when power is actually supplied to the electronic circuit package of FIG. FIG. 3 is a diagram illustrating an example of a signal.

FIG. 4 is an enlarged schematic view of a connector of the back panel of FIG. 1;

FIG. 5A is a diagram showing a change over time of a power supply value Vcc;
(B) is a diagram showing a change over time of the reset signal of the power-on reset circuit of FIG. 1, (c) is a diagram showing an example of a manual reset signal input to the manual reset input terminal of the reset IC of FIG. 1, (d) 2) is a diagram illustrating a change over time of a signal input to the electronic circuit package via the signal connector of FIG. 1.

FIG. 6 is a timing chart showing data line control of the SDRAM.

FIG. 7 is a block diagram showing a general connection method of data lines of an SDRAM.

FIG. 8 is a diagram illustrating a connector of an online repair device according to another embodiment of the present invention.

FIG. 9 is a block diagram showing a configuration of an electronic circuit package according to another embodiment of the present invention.

FIG. 10 is a block diagram showing a configuration of the memory array of FIG. 9;

FIG. 11 is a block diagram illustrating a configuration of a control LSI of FIG. 9;

FIG. 12 is a timing chart showing the operation of another embodiment of the present invention.

FIG. 13 is a block diagram showing a schematic configuration of an electronic circuit package according to another embodiment of the present invention.

14A is a diagram showing a change over time of a power supply value Vcc supplied to a conventional power-on reset circuit, and FIG. 14B is a diagram showing a change over time of a reset signal output from the conventional power-on reset circuit. FIG.

FIG. 15A is a block diagram showing a state in which a conventional SDRAM performs bus fight, and FIG. 15B is a timing chart for explaining a state in which a conventional SDRAM performs bus fight.

[Explanation of symbols]

2-1 to 2-4, 33b-1 to 33n-1, 33n-m
SDRAM 3,10 Electronic circuit package 4,20 Back panel 12 Power-on reset circuit 14,34a, 35a Reset IC 14a Manual reset input terminal 22,41 Power connector 24,42 Signal connector 26 Package insertion detecting device 31 Clock supply circuit 31c Oscillator 31e, 33a-1 PLL circuit 32 Through mode control circuit 33-1 to 33-m SIMM 34 Normal logic reset circuit 35 SDRAM data control circuit 36 Control LSI 36a CKE normal logic circuit 36b DQM normal logic circuit

Claims (25)

(57) [Claims] An electronic circuit package mounted on a back panel.
When replacing the cage, replace the electronic circuit pack from the back panel.
Time delay for power and signals supplied to the package
To prevent the electronic circuit package from malfunctioning.
Repair device, wherein the electronic device is connected to the back panel.
The power supply voltage supplied to the circuit package exceeds a predetermined threshold.
Signal and reset signal into the electronic circuit package
Manual for reset integrated circuit to instruct transmission of data
When a signal is input to the reset input terminal
The electronic circuit package from the reset integrated circuit.
A reset signal to the electronic circuit package.
When the attachment to the back panel is completed, the reset integration circuit
Command to cancel the transmission of the reset signal to the
After a predetermined time from the instruction to cancel the transmission of the reset signal
Sending the reset signal from the reset integrated circuit
And the power is supplied and the battery is
When the clock is not input when the signal from the
Clocks to clock-synchronous storage elements that cause busfights
Lock the power supply and from the back panel
Is generated when no signal is supplied, and the generated clock
And the data of the storage element based on the reset signal.
It is important to control the wire to have high impedance.
Online repair equipment. 2. A signal to the manual reset input terminal.
Input is either pull-up or pull-down
The method according to claim 1, wherein
Line repair device. 3. The electronic circuit package from the back panel.
A power connector for supplying the power to the cage;
Between the back panel and the electronic circuit package.
And a signal connector for transmitting signals to the back panel.
3. The method according to claim 1 or 2, wherein
Online repair device. 4. The power connector and the signal connector
Before the electronic circuit package is connected to both
The transmission of the reset signal is canceled.
The online repair device according to claim 3, wherein 5. The backpack of the electronic circuit package.
At the completion of mounting to the
It was to switch to the normal clock from the back panel
The method according to any one of claims 1 to 4, wherein
Online repair equipment. 6. A method for generating a clock to said storage element.
Clock that is slower than the normal clock from the back panel.
2. A lock is generated.
The online repair device according to any one of claims 1 to 5. 7. The power supply and the back panel
To the storage element that is generated when the signal from the
Clock triggers the phase locked loop circuit in the storage element.
Claim 1 to Claim 2, wherein
Item 7. An online repair device according to any one of Items 6. 8. An electronic circuit package mounted on a back panel.
When replacing the cage, replace the electronic circuit pack from the back panel.
Time delay for power and signals supplied to the package
To prevent the electronic circuit package from malfunctioning.
Repair device, wherein the electronic device is connected to the back panel.
The power supply voltage supplied to the circuit package exceeds a predetermined threshold.
Sends a reset signal to the electronic circuit package when
Reset means for resetting, and the electronic circuit package of the power supply.
Reset from the reset means in response to the supply to the
Generating means for generating an instruction signal for instructing the transmission of a reset signal
Mounting the electronic circuit package on the back panel.
At the time of completion of the arrival, the previous
To the reset means which is transmitting the reset signal.
Release signal for instructing the release of the reset signal to be transmitted.
Release means for outputting the power;
When the clock is not input when the signal from the
Clocks to clock-synchronous storage elements that cause busfights
Lock the power supply and from the back panel
Clock generation means for generating when no signal is supplied,
The reset signal and the clock from the reset means.
The clock based on the clock generated by the generating means.
The data line of the storage element is controlled to be high impedance.
And a data control means for controlling
After a predetermined time from the output of the reset signal,
Configuration to cancel the transmission of the reset signal.
And an online repair device. 9. The method according to claim 8, wherein the generating means includes a pull-up and a pull-down
The instruction signal is generated in one of the
On of claim 8, wherein the form has Rainripe
A device. 10. The electronic circuit panel from the back panel.
A power connector for supplying the power to the package;
Exchanged between the back panel and the electronic circuit package
A signal connector for transmitting a signal to the back panel;
10. The method according to claim 8, wherein
Online repair device. 11. The power connector according to claim 11 , wherein
And the electronic circuit package in both the signal connector
Is configured to output the release signal when is connected.
The online repair device according to claim 10, wherein
Place. 12. The back of the electronic circuit package.
Generated by the clock generation means when mounting to the panel is completed.
Normal clock from the back panel.
Clock switching means for switching between clocks.
Online according to any one of claims 8 to 11
Repair device. 13. The clock generating means according to claim 1 , wherein
Generate a clock that is slower than the normal clock from the panel
9. The apparatus according to claim 8, wherein the apparatus is configured such that:
3. The online repair device according to any one of 2. 14. The power supply and said back-up
When the signal from the channel is not supplied,
The generated clock is a phase locked loop in the storage element.
Including means for controlling the circuit to slew.
The online method according to any one of claims 8 to 13,
Repair device. 15. An electronic circuit panel mounted on a back panel.
When the package is replaced, the electronic circuit is removed from the back panel.
This may give a time difference to the power and signals supplied to the package.
To prevent malfunction of the electronic circuit package.
An repair device, comprising:
The power supply voltage supplied to the sub-circuit package exceeds a predetermined threshold.
Reset signal to the electronic circuit package when
Manual for reset integrated circuit to instruct signal transmission
One when a signal is input to the reset port
In the case of the above, the electronic circuit package is
Sends a reset signal to the electronic circuit package.
Reset integration upon completion of mounting on the back panel
Instructing the circuit to cancel the transmission of the reset signal;
A predetermined time after instructing the cancellation of the reset signal transmission
Later, the reset signal is transmitted from the reset integrated circuit.
And the power is supplied and the battery is
Clock synchronous type when no signal is supplied from the clock panel.
Generate a clock to the storage element, and
The data line of the storage element goes high based on the set signal.
The back panel is controlled to be impedance.
And the electronic circuit package from the back panel.
A power connector for supplying the power to the
Panel and the back panel and the electronic circuit package.
Signal connector for transmitting signals to and from the cage
And when the electronic circuit package is connected to both
The transmission of the reset signal is canceled.
Online repair equipment. 16. A signal to the manual reset input terminal.
Signal input is either pull-up or pull-down
16. The method according to claim 15, wherein
Online repair device. 17. The back of the electronic circuit package.
When the mounting to the panel is completed, the clock to the storage element
Switch to the normal clock from the back panel
17. The method according to claim 15, wherein
Online repair device. 18. A method for generating a clock to said storage element.
And is slower than the normal clock from the back panel
A clock is generated.
The online repair according to any one of claims 15 to 17.
apparatus. 19. The power supply and said back-up
The storage element which is generated when a signal from the channel is not supplied
Clock to the phase locked loop circuit in the storage element
16. The method according to claim 15, wherein the through operation is performed.
The online repair device according to claim 18. 20. An electronic circuit panel mounted on a back panel.
When the package is replaced, the electronic circuit is removed from the back panel.
This may give a time difference to the power and signals supplied to the package.
To prevent malfunction of the electronic circuit package.
An repair device, comprising:
The power supply voltage supplied to the sub-circuit package exceeds a predetermined threshold.
A reset signal to the electronic circuit package when
Reset means for output, the electronic circuit package of the power supply
The reset from the reset means in response to the supply to the
Generating means for generating an instruction signal for instructing transmission of a reset signal
Mounting the electronic circuit package on the back panel.
At the time of completion of the arrival, the previous
To the reset means which is transmitting the reset signal.
Release signal for instructing the release of the reset signal to be transmitted.
Release means for outputting the power;
Clock synchronous type when no signal is supplied from the
A clock generation means for generating a clock to the storage element;
The reset signal and the clock from the reset means.
The clock based on the clock generated by the generating means.
The data line of the storage element is controlled to be high impedance.
A data control means for controlling the electronic circuit package;
The clock generating means upon completion of attachment to the back panel.
The clock generated by the back panel.
Clock switching means for switching to a normal clock.
A predetermined time after the release means outputs the release signal
Release of the reset signal from the reset means
Online repair equipment characterized in that
Place. 21. A method according to claim 21, wherein said generating means includes a pull-up and a pull-up.
To generate the instruction signal in one of the down states.
21. The on-line according to claim 20, wherein:
Repair device. 22. The electronic device according to claim 19, further comprising :
A power connector for supplying the power to the package;
Exchanged between the back panel and the electronic circuit package
A signal connector for transmitting a signal to the back panel;
22. The method according to claim 20, wherein
Online repair device. 23. The power connector according to claim 23, wherein the releasing means is a power connector.
And the electronic circuit package in both the signal connector
Is configured to output the release signal when is connected.
23. The online repair device according to claim 22, wherein
Place. 24. The clock generating means, comprising:
Generate a clock that is slower than the normal clock from the panel
21. The apparatus according to claim 20, wherein:
24. The online repair device according to any one of 23. 25. The power supply and said back-up
When the signal from the channel is not supplied,
The generated clock is a phase locked loop in the storage element.
Including means for controlling the circuit to slew.
The online method according to any one of claims 20 to 24, wherein
Repair device.