JP2977576B2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary of the Invention] The present invention relates to a semiconductor integrated circuit that facilitates the attachment of an external PROM, and an object thereof is to provide a semiconductor integrated circuit device that can handle an external PROM in the same manner as a built-in PROM. In a semiconductor integrated circuit having a processor, a built-in memory including a PROM, and a boosted power supply for writing the PROM on one chip, an output terminal of the boosted power supply, an output terminal of an address for accessing an external PROM, A data terminal, a write / read signal terminal, and an enable signal terminal are provided.

[Industrial Application Field] The present invention relates to a semiconductor integrated circuit in which an external PROM is easily provided.

PR for semiconductor integrated circuits called one-chip microcomputers
Some have a built-in OM (EPROM, EEPROM) and store information that you do not want to be erased by turning off the power in this PROM. However, the capacity of a PROM made on the same chip as the processor (CPU) is limited.
It is desired to add a PROM to expand the memory capacity.

[Conventional technology]

As shown in FIG. 5, a one-chip microcomputer of the above type includes a processor 12, ROM, RA on a chip (semiconductor substrate) 10.
Built-in memory 14 such as M and PROM, boost power supply 16 for PROM writing
Is composed. To write the PROM, the detailed circuit is known and not shown, but the high voltage (V _CC = 5V
High voltage such as V _PP = 20V) to the processor
Supply write data from 12 and put PROM in write mode. Reading is performed using a normal power supply V _CC .

2. Description of the Related Art Semiconductor integrated circuits are used in various fields, and their usage is various. Depending on how it is used, it may be better to initialize at power-on and then start the control.Otherwise, store the information at the time of power-off, and then control at power-on. Some are good to restart. The use of a PROM allows the latter control.

If you want to keep the information while the power is shut down,
SRAM with external backup power supply
There is also a method of transferring to such as. Of course, this requires a backup power supply such as a battery.

[Problems to be solved by the invention]

A PROM configured on the same chip as a processor or the like has a limited memory capacity. Therefore, if it is desired to extend this, an external PROM may be provided, but high voltage _VPP is required for writing to the PROM. Then, using a writer, write to the PROM with the writer, and write the PR
A method of connecting the OM to a one-chip microcomputer is conceivable, but this requires a writer and is complicated.

It is an object of the present invention to improve such a point and to provide a semiconductor integrated circuit device capable of handling an external PROM in the same manner as a built-in PROM.

[Means for solving the problem]

As shown in FIG. 1, according to the present invention, a high-voltage output terminal _VPP0 for PROM writing / writing is applied to a processor, an internal memory, and a semiconductor integrated circuit (one-chip microcomputer) 20 with a boosted power supply.
Read signal output terminal WR, memory address output terminal ADD,
A data input / output terminal DATA and an enable signal terminal DO are provided.

As shown in FIG. 2, in the present invention, a write / read interface 18 is provided in the chip (10), an external output terminal V _PP0 for high voltage, an external output terminal for control signals are provided around the chip.
Provide external input / output terminals A / D for CNT, address and data.

Reference numeral 30 in FIG. 1 denotes an EPROM, which is a high voltage terminal for writing V _PP ,
Program terminal PROG for write / read control, address terminal ADD for memory access, data terminal DATA for memory input / output data, signal terminal for chip enable ▲
With ▼. This external EPROM 30 is
As shown, terminals V _PP0 and V _PP , WR and PRO
G, ADD and ADD, DATA and DATA, ▲ ▼ and ▲ ▼ should be connected.

Figure 2 of 24 and 26 is an external memory (EPROM), terminal V power supply line l ₁ To annexed it to one-chip microcomputer 20
From _PP0, from a control line l ₂ terminal CNT, also drawn out respectively bus B from the terminal A / D, it may be connected as shown external memory 24. 22 is an address / data latch.

[Action]

1, the external EPROM 30 can be handled in the same manner as the built-in EPROM of the one-chip microcomputer 20, and the internal data and state are written to the external EPROM 30 and the internal data and The state can be fetched and the processing can be resumed (continued).

If it becomes possible to save data in the non-volatile memory PROM, not only will data be saved, but also all necessary information
It can be stored in the OM, and the scale of data processing becomes large.

FIG. 2 is similar, and the external memories 24 and 26 can be handled in the same manner as the internal memory 14. There is no need to provide an external boost power supply for PROM writing.

〔Example〕

In order to write to the external PROM 30 in FIG. 1, the terminal ▲ ▼ of the one-chip microcomputer 20 is set to L level, and the external PR
Enable OM30. Further to the terminal V _PP0 high voltage (20
V), the terminal WR is set to the H level, and the address and data are sequentially output.

FIG. 2 is similar, except that WR and ▲ ▼
The address and data are output through the bus B and the terminal A / D. The address and data are taken into the latch 22 and after sending them, the CPU can move on to other tasks. The bus can be used in a time-sharing manner with addresses and data.

FIG. 3 shows a specific example of the boost power supply 16. TP ₁ ~TP ₃₀ is p
Channel MOS transistors, TN _{1 to} TN ₂₀ are n-channel MOS
As transistors, these constitute a CMOS inverter, a NAND gate, a flip-flop and the like as shown.
A capacitor C is connected between terminals C1 and C2, a capacitor 2C (twice the capacitance of C) is connected between terminals C1 and C3, a power supply V _DD is connected to terminal V1, and a voltage is applied between terminal V2 and ground. And a capacitor 2C is connected between the terminal V3 and the ground. CK1 and CK2 are clocks, as shown in FIG.
K2 is obtained by dividing CK1 by 1/2.

In this circuit, when the first CK1 is L and CK2 is H, the node is H, the node is L, the node is H and TP ₂₆ is off, and the node is H and the node is H and TN _{20 is} on, so the terminal C1 is L. . Since the node is H and the node is L
TP ₂₈ is on and C2 = V1 = V _DD . Node is H
If the node is H, TP ₁₁ is on, TN ₁₀ is off, TP
₁₃ is off, TN ₁₁ is on, and thus TP ₁₀ is on, so the node is H (= V2), so the node is L, TP ₃₀ is on and terminal C3 is H (= V2). At this time, V2 and V3 are H
It is.

Next, when CK1 = CK2 = H, L, H, L,
Since TP ₂₆ is ON, L is L, TN _{20 is} OFF, C1 =
V1 = V _DD . At this time, there is no change in C2, C3, and the like. CK1
There is no change even when = CK2 = L. CK1 = H, CK2 = a to L H, also H, TN ₂₀ is turned on, the terminal C1 becomes L. This is repeated thereafter, and C1 changes like C1 in FIG.

When CK1 and CK2 both become H for the second time, the voltage of the terminal C2 is doubled by capacitive coupling. Capacitor C of the terminal V2 is the voltage at the terminal C2 is accumulated through the transistor TP _27. At this time, the transistor TP ₂₈ is off. Similarly,
The potential of the terminal V3 also becomes the same potential as the terminal V2.

The above is repeated at the third, fourth,... CK1 = CK2 = H, and the potentials of the terminals C3 and V3 gradually rise as shown in the figure. C3 is a high voltage output terminal. The capacitors at the terminals V2 and V3 reduce voltage fluctuation.

〔The invention's effect〕

As described above, in the present invention, the EPRO
A write operation to M or the like is possible, and data can be saved and the system can be restarted. The system can be simplified without the necessity of specially preparing a boost power supply unit for writing the EPROM.

[Brief description of the drawings]

1 and 2 are principle diagrams of the present inventions 1 and 2, FIG. 3 is a circuit diagram showing an embodiment of a step-up power supply unit, FIG. 4 is an operation explanatory diagram of FIG. 3, and FIG. FIG. 1 and 2, 20 is a one-chip microcomputer, 12 is a processor, 14 is a built-in memory, 16 is a step-up power supply, 18 is an interface, V _PP0 , WR, ADD, DATA, ▲, CNT, A / D Terminal.

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int.Cl. ⁶ , DB name) H01L 27 / 112,21 / 8246 H01L 27/10 461

Claims (2)

(57) [Claims] 1. A semiconductor integrated circuit having a processor, a built-in memory including a PROM, and a boosted power supply for writing the ROM on a single chip, comprising: an output terminal (V _PPO ) of the boosted power supply;
Address output terminal (ADD), write data terminal (DATA), write / read signal terminal (W
R), an enable signal terminal () is provided. 2. A semiconductor integrated circuit having a processor (12), a built-in memory (14) including a PROM, and a step-up power supply (16) for writing the PROM on a single chip, wherein a write / read interface on the chip is provided. (18), and the chip has a boosted voltage output terminal (V _PPO ), an external memory control signal terminal (CNT), and an address and data input / output terminal (A / D) of the memory. A semiconductor integrated circuit characterized by the above-mentioned.