JP2976640B2 - Design support equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a description of a logic circuit described by a hardware description language expressing a function or a structure of the logic circuit, comprising a primitive logic element of an integrated circuit realizing the function or the structure. A logic synthesizing device for converting into a logical structure, and a logical compression device for extracting a redundant logical structure from a logical structure composed of primitive logical elements of an integrated circuit and optimizing the logic with respect to the redundant logical structure. The present invention relates to a design support device using a computer.

[0002]

2. Description of the Related Art In recent years, in the development of integrated circuits, the description of a logic circuit described by a hardware description language that expresses the function or structure of the logic circuit is replaced by the primitive logic of the integrated circuit that realizes the function or structure. From a logic synthesis device that converts to a logic structure consisting of elements, and a logic structure consisting of primitive logic elements of an integrated circuit,
A circuit diagram of an integrated circuit is automatically extracted from the description of the function or structure in the hardware description language by using a logical compression device that extracts a redundant logical structure and optimizes the logic with respect to the redundant logical structure. Is often adopted.

In such a case, the logic optimization processing for the redundant logical structure in the logical compression apparatus is performed for all circuit descriptions described in a hardware description language, or The user of the logical compression apparatus specifies a circuit block to be targeted (or a circuit block not targeted for optimization processing) each time, and compresses a redundant logical structure for the circuit block targeted for optimization processing. Had to be done either way.

[0004]

However, integrated circuits for signal processing, which have been actively developed in recent years, have a large circuit scale. High processing costs. Also,
In an integrated circuit for signal processing as described above, the basic elements constituting the data path system, such as registers and adders, are each independently converted to a logical structure composed of primitive logic elements of the integrated circuit. In many cases, it is not necessary to optimize a redundant logical structure from the mutual connection relationship.

However, as described above, the user of the logical compression apparatus determines that the basic block constituting such a data path system is a circuit block which is not subject to optimization processing each time. Inputting to the device requires a great deal of trouble. The conventional method has such a problem.

In view of the above problems, the present invention provides a development flag indicating whether or not to be subjected to logic optimization processing for each logical component in advance, and defines a connection structure between the logical components. An object of the present invention is to provide a design support apparatus that inputs a structure of a logic device and efficiently performs a logic optimization process based on the expansion flag.

[0007]

In order to solve the above-mentioned problems, a design support apparatus according to the present invention is described in a hardware description language that expresses a function or a structure of a logical device so as to realize a specific function or structure. The functional model,
Whether the logic structure composed of primitive logic elements converted from the description of the function or the structure using the logic synthesis device from the description of the function model is used as the target of optimization of the logic circuit in the logic compression device. The structure of the designed logic circuit is defined and registered based on the connection relationship between the component library and the logic component model extracted from the component library, having the logic component model as an element having a development flag indicating whether or not the logic circuit is designed. Converting the description of the function or structure described in the function model for each of the logic component models registered in the circuit diagram editor into a logical structure composed of primitive logic elements. A logic synthesizing apparatus for replacing a primitive logic element with a logical structure model, and a circuit editor In the case of a logical part model to be optimized for the logical circuit in the processing of the optimization of the logical circuit, the expansion flag of each logical part model is inspected in the connection relation between the registered logical part models. Expands the logical component model into a logical structure represented by the logical structure model, otherwise, retains the logical component model as it is, a logical developing device, and a logical developing device developed by the logical developing device. A logical compression device that extracts a redundant logical structure from the logical structure of the primitive logical element group and optimizes the logic with respect to the redundant logical structure.

[0008]

According to the present invention, a logical component model is extracted from the component library and connection information between the extracted logical component models is defined by a circuit diagram editor by the circuit configuration editor. sign up. In the logic synthesis device, the description of the function or structure described in the function model for each logic component model registered in the circuit diagram editor is converted into a logic structure composed of primitive logic elements, and the function model is converted into a logical structure. , Is replaced with a logical structure model composed of the converted primitive logical elements.

Here, as a method of converting a function model in a hardware description language into primitive logic elements constituting an integrated circuit, a conventionally used automatic logic synthesis system is used. [Edited by Kazunari Fujishiro; CAD / CAM 116]
(1990)].

In the logic development device, the development flag for each logic component model is checked in the connection relationship between the logic component models registered in the circuit diagram editor, and in the process of optimizing the logic circuit, In the case of a logical component model to be optimized for a logical circuit, the logical component model is developed into a logical structure represented by the logical structure model. Otherwise, the logical component model is held as it is.

In the logical compression device, a redundant logical structure is extracted from the logical structure of the primitive logical element group developed by the logical developing device, and the logic is optimized for the redundant logical structure. . Here, as a method of optimizing the logic, a logic optimizing method widely used in recent years is used.

By performing the above processing, the description of the logic circuit described by the hardware description language expressing the function or structure of the logic circuit is made up of the primitive logic elements of the integrated circuit realizing the function or structure. A logic synthesizing device for converting into a logical structure, and a logical compression device for extracting a redundant logical structure from a logical structure composed of primitive logical elements of an integrated circuit and optimizing the logic with respect to the redundant logical structure. It is possible to efficiently perform the logic optimization process in the integrated circuit design method using the logic.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a design support apparatus according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a design support apparatus according to a first embodiment of the present invention. In FIG. 1, reference numeral 10 denotes a hardware description language that expresses a function or a structure of a logical device, and a function model described so as to realize a specific function or structure, and a function or structure describing the function model. A logical structure composed of primitive logic elements, which has been converted from the description of the logical synthesis device using a logic synthesis device, in a logical compression device, indicates whether or not the logic circuit is to be optimized, The component library 11 having a logic component model as an element defines and registers the structure of the designed logic circuit based on the connection relationship of the logic component models extracted from the component library 10. The description of the function or structure described in the function model for each logical component model registered in the circuit diagram The logic synthesizing device 13 which converts the functional model into a logical structure composed of the converted primitive logical elements and converts the functional model into a logical structure model composed of the converted primitive logical elements. In the connection relationship between the component models, the expansion flag for each logical component model is checked, and in the process of optimizing the logic circuit, in the case of the logical component model to be optimized, the logical component The logical development device 14 expands the model into a logical structure represented by the logical structure model, and otherwise holds the logical component model as it is.
3 is a logical compression device that extracts a redundant logical structure from among the logical structures of the primitive logical element group developed by 3 and optimizes the logic for the redundant logical structure.

The design support apparatus configured as described above will be described below with reference to FIG. 1, FIG. 2, FIG. 3, FIG. 4, FIG. 5, FIG. 6, FIG. The operation will be described.

First, FIG. 2 shows an example of a logical component model which is an element of the component library 10 and shows a multiplexer. In FIG. 2, reference numeral 20 denotes a function model of the logical component model, which describes a function of a multiplexer in a hardware description language. Reference numeral 21 denotes an expansion flag of the logical component model. In this example, since the expansion flag is ON, the multiplexer may be a target of optimization processing for a redundant logical structure. It is shown.

FIG. 3 also shows an example of a logical component model which is an element of the component library 10 and represents a 3-bit inverter. In FIG. 3, reference numeral 30 denotes a function model of the logical component model, in which the function of a 3-bit inverter is described in a description language. 31
Is a development flag possessed by this logical component model. In this example, since the development flag is ON,
It is shown that the 3-bit inverter is also subjected to optimization processing for a redundant logical structure.

FIG. 4 is also an example of a logical component model, which is an element of the component library 10, and represents a register. In FIG. 4, reference numeral 40 denotes a function model of the logical component model, in which a function of a register is described in a hardware description language. Reference numeral 41 denotes an expansion flag of the logical component model. In this example, since the expansion flag is OFF, the register is not subject to optimization processing for a redundant logical structure. It is shown.

FIG. 5 shows an example of the connection information between the logic component models defined and registered in the circuit diagram editor 11. In this way, the designer of a logical device
Using the logical component model, which is an element of the component library 10, the structure of the designed logical device is registered in the circuit diagram editor 11. In this example, among the registered logical part models, the expansion flags of only the registers are OFF, and the expansion flags of the other logical part models are ON.

FIG. 6 shows, for all the logic component models registered in the circuit diagram editor 11 as shown in FIG. 5, using the logic synthesizer 12 for each logic component model. Description of the function described in the function model
This figure shows a state where the function model is converted into a logical structure composed of primitive logical elements, and the functional model is replaced with a logical structure model composed of the converted primitive logical elements. As described above, first, the logic synthesis is performed for each logical component. The dotted-line box indicates that this processing is synthesis within each logical component model, and that primitive logical element groups have not been expanded yet.

FIG. 7 shows, in the connection information between the logical part models shown in FIG. 6, for the logical part model for which the development flag is ON, the logical development unit 13 shows the logical structure of the primitive logical element group. It shows a state where it has been unfolded. In this example, the logical component model other than the register is expanded as shown in FIG. 7 because the expansion flag is ON. A box surrounded by a dotted line indicates that the logical component model of the register is not expanded.

FIG. 8 shows the use of a logical compression device to extract a redundant logical structure from the logical structure of a group of primitive logical elements developed as shown in FIG. The figure shows a state in which optimization has been performed. In this example,
The redundant logic structure of the OR gate and the inverter is replaced with a NOR gate. In this optimization processing, since the logical structure in the register is not expanded, it is not included in the object of the optimization processing, and only based on the connection relationship between the logical structure of the multiplexer and the logical structure of the 3-bit inverter. Circuit compression was done.

As described above, according to the present embodiment, the function model described in the hardware description language that expresses the function or structure of the logical device so as to realize a specific function or structure is provided. In the logical compression device, it is determined whether or not a logical structure composed of primitive logical elements, which has been converted from the description of the function or structure using the logical synthesis device, is to be optimized by the logical compression device. A part library having a development flag and a logical part model as an element, and a connection relationship between the part library and the part model extracted from the part library,
A circuit diagram editor for defining and registering the structure of the designed logic circuit, and a description of the function or structure described in the function model for each logic component model registered in the circuit diagram editor as a primitive logic. A logical synthesis device that converts the functional model into a logical structure model composed of the converted primitive logic elements and converts the functional model into a logical structure model, and a logical component model registered in the circuit diagram editor. In the connection relationship, the expansion flag for each logical component model is checked, and in the process of optimizing the logical circuit, in the case of the logical component model to be optimized, the logical component model is replaced by A logical expansion device that expands the logical component model into a logical structure represented by the logical structure model, and otherwise holds the logical component model as it is. Deployed Te, from the logical structure of primitive logic element group, to extract the redundant logic structure,
A logic compression device for optimizing the logic with respect to the redundant logic structure, extracting a logical component model from the component library, and specifying connection information between the extracted logical component models by a circuit diagram editor. Registers the structure of the designed logic device, and in the logic synthesis device,
The function or structure description described in the function model for each logic component model registered in the circuit diagram editor is converted into a logical structure composed of primitive logic elements, and the function model is converted The logic development model is replaced with a logic structure model composed of primitive logic elements, and the logic development device checks the development flag for each logic component model in the connection relationship between the logic component models registered in the circuit diagram editor. In the process of optimizing logic circuits,
In the case of a logic component model to be optimized for a logic circuit, the logic component model is expanded into a logic structure represented by the above-described logic structure model, otherwise, the logic component model is held as it is, In the logical compression device, a redundant logical structure is extracted from the logical structure of the primitive logical element group expanded by the logical expansion device, and the logic is optimized for the redundant logical structure. A logic synthesis device that converts a description of a logic circuit described by a hardware description language that expresses a function or structure of the logic circuit into a logic structure composed of primitive logic elements of an integrated circuit that realizes the function or structure; A redundant logical structure is extracted from a logical structure composed of primitive logical elements of a circuit, and logic is optimized for the redundant logical structure. It is possible to carry out the optimization process of the logical efficiently in the design method for an integrated circuit using a physical compression device.

Hereinafter, a second embodiment of the present invention will be described with reference to the drawings. FIG. 9 is a configuration diagram of a design support apparatus according to the second embodiment of the present invention. In FIG. 9, 91 is a circuit diagram editor, 92 is a logic development device, 93
Is a logical compression device, which has the same configuration as that of FIG. The difference from the configuration of FIG. 1 is that instead of the component library 10 in FIG. 1, a logical structure composed of primitive logical elements constituting an integrated circuit, a logical structure model configured to realize a specific function, A logic having an expansion flag indicating whether or not a logic structure composed of primitive logic elements defined by the logic structure model is to be subjected to optimization of the logic circuit in the logic circuit optimization processing. Component library 9 with component models as elements
0 and the point where the logic synthesis device 12 is deleted.

A second embodiment of the design support apparatus constructed as described above will be described with reference to FIGS. 9, 10, 11, 12, 5, 6, 7, and 8. Will be described.

First, FIG. 10 shows an example of a logical component model, which is an element of the component library 90, and represents a multiplexer. In FIG. 10, 100 is
This is a logical structure model possessed by the logical component model, in which functions are represented by a connection structure of primitive logic elements constituting an integrated circuit. Reference numeral 101 denotes an expansion flag included in the logical component model. In this example, since the expansion flag is ON, the multiplexer may be a target of optimization processing for a redundant logical structure. It is shown.

FIG. 11 also shows an example of a logical component model, which is an element of the component library 90, and represents a 3-bit inverter. In FIG. 11, reference numeral 110 denotes a logical structure model of the logical component model;
The function is expressed by a connection structure of primitive logic elements that constitute an integrated circuit. Reference numeral 111 denotes an expansion flag of the logical component model. In this example, since the expansion flag is ON, the 3-bit inverter is also subjected to optimization processing for a redundant logical structure. It has been shown.

FIG. 12 is also an example of a logical component model, which is an element of the component library 90, and represents a register. In FIG. 12, reference numeral 120 denotes a logical structure model of the logical component model, whose functions are represented by a connection structure of primitive logical elements forming an integrated circuit. Reference numeral 121 denotes an expansion flag of the logical component model. In this example, the expansion flag is
Since it is F, it is indicated that the register is not subjected to the optimization processing for the redundant logical structure.

FIG. 5 shows an example of the connection information between the logic component models defined and registered in the circuit diagram editor 91. In this way, the designer of a logical device
Using the logical component model, which is an element of the component library 90, the structure of the designed logical device is registered in the circuit diagram editor 91. In this example, among the registered logical part models, the expansion flags of only the registers are OFF, and the expansion flags of the other logical part models are ON.

FIG. 6 shows a state before the logic is developed by the logic developing device 92 for all the logic component models registered in the circuit diagram editor 91 as shown in FIG. The dotted box indicates that the primitive logic element group has not been expanded yet.

FIG. 7 shows, in the connection information between the logical part models shown in FIG. 6, with respect to the logical part model for which the development flag is ON, the logical development unit 92 shows the logical structure of the primitive logic element group. It shows a state where it has been unfolded. In this example, the logical component model other than the register is expanded as shown in FIG. 7 because the expansion flag is ON. A box surrounded by a dotted line indicates that the logical component model of the register is not expanded.

FIG. 8 shows a case where a redundant logical structure is extracted from the logical structure of a group of primitive logical elements developed as shown in FIG. The figure shows a state in which optimization has been performed. In this example,
The redundant logic structure of the OR gate and the inverter is replaced with a NOR gate. In this optimization processing, since the logical structure in the register is not expanded, it is not included in the object of the optimization processing, and only based on the connection relationship between the logical structure of the multiplexer and the logical structure of the 3-bit inverter. Circuit compression was done.

As described above, according to the present embodiment, a logical structure model configured to realize a specific function by a logical structure composed of primitive logical elements constituting an integrated circuit, and a logical structure model configured to realize a specific function. A logic component model having a development flag indicating whether or not a logic structure composed of defined primitive logic elements is to be optimized in the logic circuit in the process of optimizing the logic circuit. A circuit diagram editor, which defines and registers the structure of the designed logic circuit based on the connection relationship between the component library and the logical component model extracted from the component library, and the respective logical components registered in the circuit diagram editor In the connection relationship between the models, the expansion flag for each logical component model is checked, and in the process of optimizing the logic circuit, the logic to be optimized for the logic circuit is checked. In the case of a product model, the logical component model is developed into a logical structure represented by the logical structure model. Otherwise, the logical component model is retained as it is, by a logical developing device and a logical developing device. A logical compression device that extracts a redundant logical structure from the expanded logical structure of the primitive logical element group and optimizes the logic with respect to the redundant logical structure. The part model is taken out, the connection information between the taken out logical part models is defined by the circuit diagram editor, and the structure of the designed logic device is registered. In the connection relationship between the respective logical component models, the development flag of each logical component model is inspected, and the logic circuit optimization For logical component model to be subjected to reduction, the logical component model, developed in the logical structure represented by the above logical structure model, otherwise, a logical component model, and held as it is,
In the logical compression device, a redundant logical structure is extracted from the logical structure of the primitive logical element group expanded by the logical expansion device, and the logic is optimized for the redundant logical structure. A logical compression apparatus for extracting a redundant logical structure from a logical structure composed of primitive logical elements of an integrated circuit and optimizing the logic with respect to the redundant logical structure. Optimization processing can be performed efficiently.

[0034]

As described above, the present invention relates to a hardware description language that expresses the function or structure of a logical device, and describes a function model and a function model described so as to realize a specific function or structure. Indicates whether a logic structure composed of primitive logic elements, which has been converted from the described function or structure description using the logic synthesis device, is to be subjected to optimization of a logic circuit in the logic compression device. A circuit diagram editor for defining and registering the structure of a designed logic circuit based on a connection relationship between a component library having a logic component model having an expansion flag and a logic component model extracted from the component library. And the description of the function or structure described in the function model for each logical component model registered in the circuit diagram editor A logic synthesis device that converts the functional model into a logical structure model that is converted to a logical structure composed of logical elements and that converts the functional model to a logical structure model that is composed of the converted primitive logical elements; In the connection relationship of, the expansion flag for each logical component model is inspected, and in the process of optimizing the logical circuit, in the case of the logical component model to be optimized for the logical circuit,
The logical component model is developed into a logical structure represented by the logical structure model. Otherwise, the logical component model is retained as it is, and a logical developing device and a primitive developed by the logical developing device are developed. A logical compression device that extracts a redundant logical structure from the logical structure of the logical element group and optimizes the logic with respect to the redundant logical structure;
A logic for converting a description of a logic circuit described by a hardware description language expressing a function or a structure of the logic circuit into a logic structure composed of primitive logic elements of an integrated circuit realizing the function or the structure An integrated circuit using a synthesizing device and a logical compression device that extracts a redundant logical structure from a logical structure composed of primitive logical elements of the integrated circuit and optimizes the logic with respect to the redundant logical structure. In the design method, it is possible to efficiently perform logic optimization processing.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a design support apparatus according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating an example of a logical component model in which a development flag is ON;

FIG. 3 is a diagram illustrating an example of a logical component model in which a development flag is ON;

FIG. 4 is a diagram illustrating an example of a logical component model in which a development flag is OFF;

FIG. 5 is a diagram showing a state in which the structure of a designed logic device is defined by a circuit diagram editor;

FIG. 6 is a diagram showing a state in which each logical component model is synthesized into a primitive logical element by a logical synthesizer.

FIG. 7 is a diagram showing a state where a logical component model is developed into a logical structure by primitive logical elements by a logical developing device.

FIG. 8 is a diagram showing a state where a redundant logical structure is optimized by a logical compression device;

FIG. 9 is a configuration diagram of a design support apparatus according to a second embodiment of the present invention.

FIG. 10 is a diagram illustrating an example of a logical component model in which a development flag is ON;

FIG. 11 is a diagram showing an example of a logical component model whose development flag is ON.

FIG. 12 is a diagram illustrating an example of a logical component model in which a development flag is OFF.

[Explanation of symbols]

10, 90 parts library 11, 91 circuit diagram editor 12 logic synthesis device 13, 92 logic development device 14, 93 logic compression device 20, 30, 40 functional model 100, 110, 120 logical structure model 21, 31, 41, 101, 111, 121 Expansion flag

Claims (3)

(57) [Claims] 1. A logic for converting a description of a logic circuit described by a hardware description language expressing a function or a structure of a logic device into a logic structure composed of primitive logic elements of an integrated circuit realizing the function or the structure. A logic circuit, comprising: a synthesis device; and a logic compression device that extracts a redundant logic structure from a logic structure including primitive logic elements of an integrated circuit and optimizes the logic with respect to the redundant logic structure. A function model written to realize a specific function or structure in a hardware description language that expresses the function or structure of a logical device, and a description of a function or structure describing the above function model The logic structure composed of the primitive logic elements converted by using the logic synthesis device from Indicate whether to target for optimization,
A logical component model having an expansion flag as an element,
A circuit diagram editor for defining and registering the structure of the designed logic circuit based on the connection relationship between the component library and the logical component model extracted from the component library;
The function or structure description described in the function model for each logical component model registered in the circuit diagram editor is converted into a logical structure composed of primitive logic elements, and the function model is converted into the converted primitive model. A logic synthesis device to be replaced with a logic structure model consisting of logic elements, and a connection flag between the logic component models registered in the circuit diagram editor, inspecting a development flag for each logic component model, In the optimization process of (1), if the logical component model is to be optimized for the logic circuit, the logical component model is expanded to the logical structure represented by the logical structure model. From the logic structure of primitive logic elements developed by the logic development device and the logic development device that holds the model as it is, Extract the physical structure, design support device having a logical compression apparatus for performing a logic optimization to the redundant logic structure. 2. A primitive for constructing an integrated circuit by extracting a redundant logical structure from a logical circuit and providing a design support device having a logical compression device for optimizing the logic with respect to the redundant logical structure. A logical structure model composed of various logical elements, and configured to realize a specific function;
A logic having an expansion flag indicating whether or not a logic structure composed of primitive logic elements defined by the logic structure model is to be subjected to optimization of the logic circuit in the logic circuit optimization processing. A circuit diagram editor that registers and registers the structure of the designed logic circuit based on the connection relationship between the component library having the component model as an element and the logical component model extracted from the component library. In the connection relationship between the respective logical part models, the development flag of the logical part model is inspected for each logical part model, and is used as a target of the logical circuit optimization in the processing of the optimization of the logical circuit. In the case of a logical part model, the logical part model is developed into a logical structure represented by the logical structure model. Or to hold, and the logical deployment device,
A design having a logical compression device that extracts a redundant logical structure from the logical structure of a group of primitive logical elements developed by the logical expander and optimizes the logic for the redundant logical structure Support equipment. 3. The hardware description language is a text language that expresses the function or structure of a logical device by lexical expression, a graphical language that expresses the function or structure of the logical device graphically, or the text language described above. 2. The design support apparatus according to claim 1, wherein the language is a language that expresses the function or structure of the logic device by mixing a graphical language.