JP2975722B2 - Computer data communication system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data communication system of a computer, and more particularly to a data communication system of a parallel computer for performing data communication between a plurality of processors.

[0002]

2. Description of the Related Art In recent years, with the advance of semiconductor technology, it has become easy to arrange a large number of hardware of the same kind, and research on a parallel computer capable of interconnecting a plurality of element processors and performing arithmetic processing in parallel has been active. It is.

For example, as disclosed in the 38th (early 1989) Transactions of Information Processing Society of Japan 2T-2, the inventor of the present application has proposed to use a one-chip element processor LSI of up to 10
24 large-scale data-driven computers (Enhanced Data
Driven Engine). All communication between element processors in such a large-scale data driven computer is bidirectional communication, and data communication is possible between any two processors over the shortest distance.

Further, in a communication system of a large-scale data driven computer of this kind, an input / output interface for transmitting to the outside of a processor array comprising a processor connection network is connected to a specific processor, and data to the outside is connected. It is proposed that by holding the number (row number, column number) of the processor to which this input / output interface is connected, the outbound data can be transmitted to the processor with the output interface. .

However, as described above, the number of the nearest processor of the input / output interface must be completely specified as the destination processor number of the data going outside the processor connection network. Therefore, both the row number and the column number are specified as the destination processor number. For example, if the destination processor number field held by the data is 10 bits, at most 2 ¹⁰ = 102
Only a system consisting of four processors can be constructed.

In such a data driven computer, in order to further increase the number of processors, it is necessary to further increase the bit length of the processor number. However, increasing this bit length reduces the data word length of the communication data. However, there is a disadvantage that the hardware of the entire computer system is increased.

[0007]

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and has been made by adding a part of a destination processor number connected to an output interface to data going outside a processor connection network in a parallel processing computer system. Just by holding it, it can be output to the outside, so that the number of processors in the computer can be greatly increased without increasing the data length of the destination processor number held by the communication data. Is to provide a system.

[0008]

According to the data communication system of the present invention, a plurality of processors having at least four communication ports of east, west, north and south are arranged in a matrix, and each processor identifies a row in the matrix. East-west communication in which a processor array identified by a processor number consisting of a row number and a column number identifying a column is connected, and each processor in the row direction of the array is connected using its two east-west communication ports. Line, and a north-south communication line that couples each processor in the column direction of the array using its two north-south communication ports, allowing data communication between any of the processors in the processor array via these communication lines. In the data communication system of a computer, the data communicated through the communication line includes a destination processor number,
And an external flag indicating whether or not the data should be output to the outside of the processor array. The external flag included in the communication data arriving at the processor or generated by the processor indicates that the communication data is When it is indicated that the communication data is not going to the outside, the communication data is selectively used by using any of the communication ports to transmit the data to the processor of the destination row number and column number included in the communication data. Output the data, and when the external flag included in the communication data arriving at the processor or generated by the processor indicates that the communication data is going out of the processor array, the destination included in the data. To transmit the data to a processor having a specific row number and a specific column number predetermined separately from the data. The processor array is used as one processor group, and a plurality of processor groups are interconnected to perform data communication between all the processors. Enabled, each processor group having an input / output interface coupled to at least one of the processor groups in the particular column of the processor array, wherein the destination contains data to be output outside each processor group. Column number field is used as a field for storing the group number of the destination processor group, and according to the group number stored in the field, the plurality of processor groups can be connected via the input / output interface. It is characterized by performing data communication.

Further, in the data communication system according to the present invention, the processor array is formed as one processor group,
Further, in a computer data communication system in which a plurality of processor groups are mutually connected to perform data communication between processors, each processor group is connected to at least one of the processor groups in the aforementioned specific column of the processor array. An input / output interface is provided, wherein a destination column number field included in data to be output to the outside of each processor group is used as a field for storing a group number of a destination processor group, and a group stored in the group number field is used. According to the numbers, data communication is performed between a plurality of processor groups via the aforementioned input / output interface.

[0010]

According to the data communication system of the present invention, regardless of the value of the column number field among the destination processor numbers held in the data going to the outside of the processor array, the communication control is performed toward a predetermined specific column. Done. Therefore, the outbound data of the processor array includes
If only the line number of the destination processor is designated, the communication control of the outbound data can be performed correctly. That is, the destination column number field of the outbound data can be freely used for another purpose.

Further, according to the data communication system of the present invention, the column number field of the destination processor number held by the outward data of one processor group including the processor array is used as the destination processor group number, The number of processors constituting the system can be greatly increased without newly adding a field for designating a group number.

[0012]

FIG. 1 shows a parallel data driven computer system as an embodiment of the present invention, and FIG. 2 shows a configuration of an element processor which is a basic component of the parallel data driven computer system.

First, in FIG. 1, PE is an element processor, and NIF is a network interface. In this embodiment, element processors (PE) are connected in a torus. That is, a plurality of element processors (PEs) each having four communication ports of the east, west, north and south are arranged in a matrix, and each row direction, that is, the east-west direction element processor group, and each column direction, that is, the north-south element processor group, are provided in plural numbers. They are cyclically connected by communication links in a ring. Also, a network interface (NIF) is inserted in each row-direction ring. A host interface is connected to the network interface (NIF), and a host computer is further connected to the host interface. With such a configuration, first, a program, a program, and a program are transmitted from the host computer via the host interface and the network interface (NIF). And initial data are loaded. Each element processor performs operations in parallel according to this program while performing data communication between the processors.

The element processor (PE) of FIG. 2 basically includes a program storage (PS), a firing control / color management unit (FCCM), an instruction execution unit (EXE), and a queue memory (Q). (Ring) structure. The program storage (PS) updates the node number, assigns a constant, and copies the result. The firing control and color management unit (FCCM) performs firing control and color acquisition / release management in a two-stage waiting storage system. The instruction execution unit (EXE) includes floating-point arithmetic integer arithmetic, condition determination, branching, and simple processing. Execute instructions such as constant generation and their composite instructions.

The queue memory (Q) is a buffer memory that absorbs any data flow fluctuations on the ring. Buffering is required for copying, forcing the ring,
This is when an output delay from the ring, a search of a waiting list in the FCCM, or the like occurs. The present element processor (PE) is provided with a function of dynamically changing the operation mode (1) to (3) according to the amount of data in the queue (Q), thereby controlling the degree of parallelism. When the queue (Q) overflows unavoidably, an external queue is formed on the external data memory (EDM) to absorb this and to continue the program execution.

The network control unit (NC) holds the communication ports (1), (2), (3) and (4) of the four systems of east, west, north and south, and controls routing based on a torus connection network of up to 1024 processors (PE). I do. Also, an input port (5) for inputting a data packet arriving at itself to the cyclic pipeline unit and an output port (6) for outputting a data packet from the cyclic pipeline to the network control unit. Is provided.

A vector operation control unit (VC) controls execution of vector operation related instructions and ordinary memory access instructions. A vector input bus (7) for inputting vector data is provided between the vector operation control unit (VC) and the input control unit (IC). The vector operation control unit (VC) and the input control unit (IC) IC)
And a vector output bus (8) for outputting vector data.

In the data driven computer having the above configuration,
FIG. 4 shows the configuration of a communication data packet used for inter-processor communication. Communication data packets are roughly classified into a scalar packet shown in FIG. 4A and a structure packet shown in FIG. 4B.

In FIG. 4, PE-X and PE-Y are the column number and row number of the destination PE, respectively. The CTL is control information such as a color or a code indicating a load dump destination. OT is an external flag that identifies a packet destined to the outside of the processor interconnection network. The NODE number is a node number for identifying an instruction in a data flow graph. DATA is a data value. A scalar packet holds single 32-bit data in upper and lower parts, and a structure packet holds a plurality of, that is, n-word 32-bit data. By the upper 2 bits of each word,
The header, tail, and other words of the packet can be identified. The uppermost flag also serves as a transfer control bit indicating the presence of data by inverting the value every word.

The input control section (IC) on the pipeline ring has a processor number register for storing its own processor number. FIG. 5 shows the configuration of the processor number register. PE-X is a processor number (column number) in the east-west direction, and PE-Y is a processor number (row number) in the north-south direction. Together, the processor numbers uniquely identify each processor.

A flag bit called PEACT shown in FIG. 5 is a flag indicating whether a processor number has already been set. The PEACT flag becomes “0” in response to the system initialization signal (hardware reset).

The communication control unit (NC) is shown in FIG.
The packet as shown in (b) is received via the communication port.

When PEACT = 0, the communication control unit regards all data packets input from any of the east, west, north and south ports as data packets to the communication control unit, and inputs the data packets to the pipeline to perform processing. When PEACT = 1, when a packet for loading data into the processor number register arrives, the communication control unit inputs this to the input control unit (IC), where a predetermined processor number is loaded into the processor number register. At the same time, the PEACT flag is "1"
Is set to

When PEACT = 1, the communication control unit determines whether an incoming packet is to be output to any communication port or to be input to the pipeline ring according to a predetermined algorithm.

When a packet of OT = 1 arrives, the communication control unit controls communication so that the packet is transferred to the outside of the processor connection network via the network interface (NIF).

Although not shown, a mode signal TAN for discriminating whether the direction of data communication at the time of inter-processor communication is a bidirectional mode or a unidirectional mode is externally provided to each element processor of this embodiment. Is entered.

The main feature of the present invention is that OT =
The communication control of each processor when one packet arrives. That is, if OT = 1, communication control is performed with all bits being regarded as "1" regardless of the value of the column number (PE-X) of the destination processor held by the packet.

To explain this, the operation of the communication control unit will be described in more detail. FIG. 3 schematically shows the configuration of the communication control unit. In the figure, (RWI) and (RWO) are self-synchronous input shift registers constituting the west input / output port, and similarly, (REI) (REO) is the east input / output port and (RN
I) (RNO) constitutes the north input / output port, and (RSI) (RSO) constitutes the south input / output port. ○ indicates a merging circuit, and 、 indicates a branch circuit.

The routing algorithm in the communication control unit will be described with reference to FIG.

Each of M1 to M5 is a packet merging circuit which merges packets with the priority shown in the figure (1 is the highest priority). R1 to R5 are packet branch circuits, respectively, which perform processing according to the following algorithm. 1. Own processor number (row number, column number) = (x,
y), destination processor number of packet = (X, Y), network array size = p × q (p rows and q columns), Δx≡ (X−x) mod q, | Δx | ≦ q / 2 Δy ≡ (Y−y) mod p, | Δy | ≦ p / 2. (Mod indicates a modulo operation.) The processor numbers are assumed to be y = 0, 1, 2,... P in the order from N to S x = 0, 1, 2,. 3. OT means the value of the OT bit of the packet, and OT
= 1 indicates that the packet is directed to the outside of the processor connection network. 4. When the packet OT = 1, the column number X of the destination processor number of the packet in the above み な is regarded as all bits “1”, and the above Δx is calculated.

The processing in the branch circuit will be described below. 1. When PEACT = 0 Packets from any of W, E, N, and S are also input to P. 2. When PEACT = 1 (1) R3: Output to S if Δx = 0 and Δy> 0.

If Δx = 0, Δy <0, and TAN = 1, output to S.

If Δx = 0, Δy <0 and TAN = 0, output to N.

If Δx = 0, Δy = 0 and OT = 0, input to P.

Otherwise, output to E. (2) R2: Output to S if Δx = 0 and Δy> 0.

If Δx = 0, Δy <0 and TAN = 1, output to S.

If Δx = 0, Δy <0, and TAN = 0, output to N.

If Δx = 0, Δy = 0 and OT = 0, input to P.

Otherwise, output to W. (3) R1: input to P if Δy = 0 and OT = 0.

If Δy = 0 and OT = 1, output to E.

Otherwise, output to S. (4) R4: Input to P if Δy = 0 and OT = 0.

If Δy = 0 and OT = 1, output to E.

Otherwise, output to N. (5) R5: Output to S if Δx = 0 and Δy> 0.

If Δx = 0, Δy <0 and TAN = 1, output to S.

If Δx = 0, Δy <0, and TAN = 0, output to N.

If Δx <0 and TAN = 0, output to W.

Otherwise, output to E.

The details of the routing algorithm have been described above, but the present invention is not limited to this.

As can be seen from the above description, when PEACT = 1, the packet communicated between the processors is transferred on the communication line in the east-west (E 通信 W) direction until the column numbers match, and the column numbers match. Then, it moves on the communication line in the north-south (S⇔N) direction, and is further transferred on the north-south communication line until the line number matches, and reaches the target processor.

Furthermore, regarding the packet (OT = 1) destined to the outside of the processor interconnection network, the destination is regarded as the processor in the east (E) side column regardless of the destination column number. Routing takes place. When the outbound packet is transferred to the eastmost processor, it is further output to the east (E) port and output to the outside via the network interface.

As described above, according to the data communication system of the present invention, the column number field of the destination processor in the packet going out of the processor interconnection network can be used as a field for storing other information.

Therefore, in the embodiment shown in FIGS. 6 and 7, the above-mentioned column number field is used as the destination processor group number.

FIG. 6 shows a configuration example of one processor group (PG) in which a group interface (61) for exchanging data with another processor group is connected to the processor connection network (60) described above. It is. GI
Is a group input line, and GO is a group output line.

FIG. 7 shows a configuration example of a highly parallel computer system in which a plurality of the processor groups shown in FIG. 6 are further connected. In the figure, PG0, PG1, PG2PG3,.
PG30 is a processor group, and the host computer is identified as the 32nd processor group PG32.

The CMU is a data communication unit that controls data communication during data communication between the processor groups.

As described above, the column number field (PE-X) of the destination processor number of the data packet communicated between the host computer and each processor group contains the destination processor group number, that is, "0", "".
1 ”,“ 2 ”,“ 3 ”,...,“ 31 ”are stored in. Outgoing packets are output from each processor group by the mechanism described with reference to FIGS. The data communication unit CMU outputs the packet to the destination processor group in accordance with the destination processor group number of the input packet, thus setting the destination column number field of the packet in each processor group to the processor group number. By using a destination processor number field of at most 10 bits, a high-performance parallel processing computer system composed of 30,000 or more processors can be constructed.

[0057]

As is apparent from the above description, a data communication system of a computer capable of outputting to the outside only by holding a part of the destination processor number in the data to the outside of the processor connection network. Can be provided. Accordingly, it is possible to greatly increase the number of processors constituting the system without increasing the data length of the destination processor number held by the communication data in the parallel processing computer system.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing a parallel processing computer according to the present invention;

FIG. 2 is a configuration diagram showing an element processor which is a basic component of the parallel processing computer according to the present invention;

FIG. 3 is a schematic diagram showing a main part of an element processor according to the present invention;

FIG. 4 is a configuration diagram of a data packet;

FIG. 5 is a configuration diagram of a processor number register inside an element processor according to the present invention;

FIG. 6 is a configuration diagram of one processor group in the parallel processing computer of the present invention;

FIG. 7 is a configuration diagram showing a highly parallel computer system of the present invention.

[Explanation of symbols]

 (PE): Element processor, (NIF): Network interface, (NC): Communication control unit, (PS): Program storage unit, (EXE): Instruction execution unit, (PG ): Processor group, (CMU): Data communication unit.

Claims (1)

(57) [Claims] A plurality of processors having at least four communication ports of east, west, north and south are arranged in a matrix, and each of the processors includes a row number for identifying a row in the matrix and a column number for identifying a column. An east-west communication line that connects the processors in the row direction of the array by using two east-west communication ports, and the north-south processor in the column direction of the array. comprising a north-south communication line for coupling with the two systems communications port in a computer data communication system which enables data communication even between any processor in Purosetsusaare through these communication lines, before SL communication line Yotsute data communication, an external off the processor number of the destination, and the data indicating whether or not to be output to the outside of Purosetsusaare over It will hold the lugs, when the external flag included in the communication data generated by the arrival in the processor, or the processor indicates that the communication data does not go outside the Purosetsusaare over the
And it outputs the data selectively using one of the previous SL communication port to transmit the data to the processor of the line number and column number of the destination of the communication data comprises, whereas, arrives at processor, or external flag included in the communication data generated by the processor is the communication data when the identification information indicates that the external go of Purosetsusaare over the destination of the line number that the data includes, and separately from predetermined and the data toward processor specific column number outputs the data by using selectively one of the previous SL communication port to transmit the data, and one of the pro-broken group said Purosetsusaare
Multiple processor groups to interconnect
Data communication between all processors
Sub-groups are assigned to the specific row of the processor array.
An input / output interface coupled to at least one of the
Face, and output to the outside of each process group.
Destination column number field that contains the data to be read
And the group number of the destination processor group
Field stored in the
According to the group number, via the input / output interface
To communicate data between multiple processor groups
A data communication system for a computer , characterized in that :