JP2869100B2 - Element processor of parallel computer - Google Patents

Description

The present invention relates to an element processor as a constituent unit of a parallel computer, and more particularly to a high-performance element processor having both a data processing function and a communication control function between processors.

(B) Conventional technology In recent years, research has been conducted toward the realization of a practical parallel processing computer. In particular, with the advance of semiconductor technology, a combination of a communication control unit and a data processing unit has been integrated into one chip. Of this element processor LSI
Many studies have been conducted to realize a parallel processing processor by connecting a large number of devices.

The inventor of the present application is the IPSJ 38th (early 1989)
As disclosed in Collection of Papers 2T-2, the development of a large-scale parallel data driven computer EDDEN (Enhanced Data Driven ENgine) in which a maximum of 1024 one-chip element processor LSIs are connected is underway. The present applicant has already applied for a "data communication system for parallel computers" in Japanese Patent Application No. 1-153276 as an improvement of the data communication system with the outside of the parallel processing device in EDDEN.

(C) Problems to be Solved by the Invention However, in the data communication system of the parallel computer as described above, not only a plurality of element processors for configuring the parallel processing device, but also the data communication with the outside of the parallel processing device. An input / output interface for mediating transmission and reception is required. Further, when the scale of the parallel processing device becomes large, it is required that input and output with the outside be performed in parallel at high speed, and a plurality of input / output interfaces are required.

Therefore, in order to reduce the size of the entire system, the input / output interface must be LSI, as well as the element processor.
Is desirable. However, these two types
Developing an LSI requires a great deal of labor and time, and consequently raises the cost of the entire system.

Accordingly, an object of the present invention is to provide a high-performance element processor that can operate as a processor that is a constituent unit of a parallel computer and also as an input / output interface between those processors and the outside. Furthermore, the object of the present invention is to greatly shorten the development period of a parallel processing system by realizing both the function as a unit processor of parallel processing and the function as an input / output interface by developing one kind of hardware or LSI. In addition to reducing the cost of development and manufacturing, it is also necessary to reduce the size of the system.

(D) Means for Solving the Problems The element processor of the present invention comprises at least a communication control unit and a data processing unit, and the communication control unit has a communication control unit and a data processing unit. One adjacent communication port and an internal communication port for communication with the data processing unit.

Each element processor operates in one of the processor mode and the interface mode.
The element processors in the processor mode are arranged in a matrix, and constitute a parallel processing device based on a so-called torus connection network in which processors in each row direction and processors in each column direction are cyclically connected via the above-described four adjacent communication ports. . The element processor in the interface mode applies the row direction, the row direction, or the column direction connection line to the row direction,
Alternatively, it is inserted using two adjacent communication ports in the column direction, and the remaining two adjacent communication ports are used for connection with the outside of the parallel processing system.

The communication data between the element processors or between the processor and the outside of the system includes a destination processor number and an external flag indicating whether the communication data is to be processed inside the parallel processing system or to be output outside the system. Hold.

When communication data arrives at the communication control unit of the element processor via any of the communication ports, when the element processor is in the processor mode, the destination processor number held by the communication data is compared with its own processor number. If they do not match, the data is selectively output to a communication port of the four adjacent communication ports such that the distance to the destination processor is shortest. But,
If it indicates that the data is to be processed inside the parallel processing device, the data is input to the data processing unit of its own processor via the internal communication port and the data is processed, and the two match, When the external flag held by the data indicates that the data is to be output to the outside of the parallel processing device, the data is not processed by its own processor, and the data is not processed by its own processor. Output to the specified communication port.

When the element processor is in the interface mode and the communication data is transmitted from the processor of the parallel processing device, an external flag held by the data indicates that the data is to be processed inside the parallel processing device. If the data is passed as it is and returned to the inside of the parallel processing device, and if the external flag held by the data indicates that the data should be output to the outside of the parallel computer, the data is sent to the outside of the parallel processing device. Branch.

When the element processor is in the interface mode and the communication data is transmitted from outside the parallel processing device, the data is directed to the inside of the parallel processing device if the processor number held by the communication data is within a predetermined range. If the processor number is not within the predetermined range, the data is passed in the same direction as it is.

(E) Function If the element processor of the present invention is used as a unit processor and an input / output interface device of a parallel computer, a so-called self-routing function for performing communication between processors within the parallel processing device at the shortest distance based on a grid-like processor connection network, The function of branching and outputting the result packet as the operation result to the outside of the parallel processor (such as a host computer) and the function of branching and inputting the data input from the outside of the parallel processor to a predetermined processor group are provided. All can be realized.

(F) Embodiment FIG. 1 shows a highly parallel data driven computer system as an embodiment of the present invention, and FIG. 2 shows the configuration of an element processor.

First, the element processor (PE) shown in FIG. 2 basically includes a program storage unit (PS), a firing control / color management unit (FC).
CM), an instruction execution unit (EXE), and a queue memory (Q) are connected in a cyclic pipeline (ring) structure.

The program storage unit (PS) updates the node number, assigns a constant, and copies the result. The firing control and color management unit (FCCM) manages the queuing of left and right operands and the acquisition and release of colors. The instruction execution unit (EXE) executes instructions such as floating-point / integer operation, condition determination, and branching. The queue (Q) is a buffer memory that absorbs any data flow fluctuations on the ring.

The vector operation control unit (VC) controls execution of a vector operation related instruction and an external data memory access instruction. The external data memory (EDM) is a memory for storing structures, vector data, and the like.

The communication control unit (NC) has four communication ports of north, south, east and west, and performs routing control based on a torus connection network of up to 1024 processors (PE). The input control unit (IC) performs a process of inputting a data packet from the communication control unit to the ring. The output control unit (OC) performs a process of outputting a data packet from the ring to the communication control unit. A bypass line for structure (vector) data communication is provided between the vector operation control unit (VC), the input control unit (IC), and the output control unit (OC).

The basic configuration of an EDDEN using a large number of such element processors (PE) is based on the connection of n × n element processors by a torus connection network as shown in FIG. With the torus connection network, a large number of processors are arranged in a matrix,
A plurality of vertical communication lines that cyclically connect each vertical processor group and a plurality of horizontal communication lines that cyclically connect each horizontal processor group enable data communication between arbitrary processors. is there.

In the system of this embodiment, data exchange between the network and the outside is performed by a network interface (NIF).
And insert it. As this NIF, one in which the element processor is set to the interface mode is used. An element processor has two operation modes, a processor mode and an interface mode. An element processor set to the processor mode is called a PE, and an element processor set to the interface mode is called an NIF.

The data packets used in the data driven computer having the above configuration are roughly classified into an execution packet used for program execution and a non-execution packet used for other than program execution. FIGS. 4A to 4E show examples. Is shown. The packet format is fixed length except for the packet holding the structure data, and is 33 bits x 2 words on the pipeline in the processor (PE) and 18 bits x 4 words on the network (communication control unit). is there. The contents of each field in the packet format of FIG. 4 will be described below.

HD (1 bit): An identifier of the first word (header) and the second word (tail) in a two-word packet. “1” when header.

EX (1 bit): A flag for identifying a packet to be output from the pipeline ring to the communication control unit.

MODE (2 bits): An identification code for identifying the type of packet such as an execution packet and a non-execution packet.

S-CODE: An identification code that defines processing for a packet together with MODE.

OPCODE-M (5 bits) and OPCODE-S (6 bits): Instruction codes for identifying the type of instruction.

NODE # (11bit): Node number of data flow graph.

COLOR (4bit): An identification number that identifies the environment when multiple executions of the same data flow graph are performed, such as sharing a program by a subroutine call.

DATA (32bit): Numeric data such as integers and floating point numbers.

HT (1bit): Flag for identifying header, tail and intermediate words in a packet on the network. RQ (1bit): Flag added to the packet transmitted on the network. One word of data is transmitted on the network. Each time the value is inverted, the presence of the word can be recognized.
Further, the inversion of the value becomes a transfer request signal for transferring the packet forward. The header and the tail can be identified together with the HT flag.

ADDRESS (16bit): Stores the memory address when loading / dumping each memory.

The input control unit (IC) on the pipeline ring has a processor number register for storing its own processor number. FIG. 6 shows the configuration of the processor number register. The PE number X is a horizontal (east-west) PE number (column number), and the PE number Y is a vertical (south-north) PE number (row number). Together, the processor numbers uniquely identify each processor.

A flag bit called PEACT shown in FIG. 6 is a flag indicating whether or not the processor number has already been set, and is "0" if not set, and "1" when set.

The communication control unit (NC) receives a packet as shown in FIGS. 4C and 4E via a communication port.

In the special operation mode (PEACT = 0), the communication control unit regards all data packets input from all ports in the east, west, north and south as packets to itself, inputs them to the pipeline ring, and is indicated by the identification code. A predetermined process is performed. At this time, when a non-executable packet having an identification code indicating a load to the processor number register shown in FIG. 6 arrives at one of the east, west, north and south ports, the communication control unit sends this to the input control on the pipeline Unit (IC), where the processor number register is loaded with the specified processor number and PEACT
The flag is set to "1". When the PEACT flag is set to "1" in this manner, the communication control unit (NC) of the processor operates in the normal operation mode.

In the normal operation mode (PEACT = 1), the communication control unit sets the PE # (the destination processor number of the packet) in the first word of the arriving packet and the own processor number set in the own processor number register. The packet is input to the pipeline ring only when the two match, and when the two do not match, the packet is output to one of the east, west, north, south and north ports in accordance with a predetermined routing algorithm to be directed to the adjacent processor. Transfer.

FIG. 5 shows the types of packets identified by MODE. As shown in the figure, a packet holding MODE = 00 is identified as a result packet output to the host computer.

Although not shown, a signal INS for specifying whether to operate in the processor mode or the interface mode is externally input to the element processor of the present embodiment. When INS is 0, the element processor operates as a unit processor PE of the parallel computer, and when INS is 1, the element processor operates as an input / output interface NIF.

The main features of the element processor of the present invention are as described above.
The element processor can operate as either a PE or an NIF according to the INS signal.

To explain this, the operation of the communication control unit will be described in more detail. FIG. 3 schematically shows the configuration of the communication control unit (NC). In the figure, (RWI) and (RWO) are a self-synchronous input shift register and an output shift register constituting the west (W) input / output port, and are composed of four stages of 18-bit registers. Similarly, (REI) (REO) means east (E)
The input / output port, (RNI) (RNO) constitutes a north (N) input / output port, and (RSI) (RSO) constitutes a south (S) input / output port. ○ indicates a merging circuit, and 、 indicates a branch circuit.

The routing algorithm in the communication control unit will be described with reference to FIG. Each of M1 to M5 is a packet merging circuit that assigns a priority in the order of the numbers shown in the figure and merges arriving packets (number 1 has the highest priority).

R1 to R5 are packet branch circuits, respectively, which perform processing according to the following algorithm.

I. Change your processor number (row number, column number) to (y,
x), the array size of the network is p × q (p: vertical direction,
q: horizontal direction), specify the destination processor number of the packet as (Y,
X), and Δx≡ (X−x) mod q, | Δx | ≦ q / 2 Δy≡ (Y−y) mod p, | Δy | ≦ p / 2. (Mod indicates a modulo operation.) II. Processor numbers are in the order from N to S, y = 0, 1, 2,..., P in the direction from W to E. x = 0, 1, 2,. ... Q.

III.MODE means the value of the MODE field of the packet, MO
DE = 00 means that the packet is destined for the host computer.

 The processing in the branch circuit will be described below.

(1) R1: MODE ≠ 00 and (PEACT = 0 or (Δy = 0 and INS =
At 0)), output the packet to P.

(MODE = 00 and PEACT = 1) and (Δy = 0 or INS
= 1), the packet is output to E.

 Otherwise, output the packet to S.

(2) R2: MODE ≠ 00 and (PEACT = 0 or (Δx = 0 and Δy
= 0 and INS = 0)), the packet is output to P.

When INS = 0, PEACT = 1, Δx = 0, and Δy> 0, output the packet to S.

When INS = 0, PEACT = 1, Δx = 0, and Δy <0, output the packet to N.

 Otherwise, output the packet to W.

(3) R3: MODE ≠ 00 and (PEACT = 0 or (Δx = 0 and Δy
= 0 and INS = 0)), the packet is output to P.

(INS = 0 and PEACT = 1 and Δx = 0 and Δy> 0)
Or, when (INS = 1 and PEACT = 1 and the destination processor number is within a predetermined range), output the packet to S.

When INS = 0, PEACT = 1, Δx = 0, and Δy <0, output the packet to N.

 Otherwise, output the packet to E.

(4) R4: MODE ≠ 00 and (PEACT = 0 or (Δy = 0 and INS =
At 0)), output the packet to P.

(MODE = 00 and PEACT = 1) and (Δy = 0 or INS
When = 1), the packet is output to E.

 Otherwise, output the packet to N.

(5) R5: When Δx = 0 and Δy> 0, output the packet to S.

 When Δx = 0 and Δy <0, output the packet to N.

 When Δx <0, output the packet to W.

 Otherwise, output the packet to E.

As can be seen from the above description, PEACT = 1 and INS = 0
In the processor operation mode, when the destination of the packet = (Y, X) and the processor number of each processor = (y, x), X is not x. As long as the packet is transferred from W to E or from E to W. If X = x, forward the packet from N to S or from S to N unless Y = y. Further, when transferring a packet from a port of W or E to a port of N or S, or transferring a packet from the inside of the pipeline ring to any port of W, E, N, or S, a modulo operation is performed by the processor. The direction in which the distance becomes smaller is selected, and the packet communication control function (self-routing function) at the shortest distance is always realized.

Further, the packet arrives at the destination processor, and Δ
When x = Δy = 0 is detected, if MODE ≠ 00, it is input to the pipeline of the destination processor and processed,
If the packet is destined for the host computer of MODE = 00, the packet is not input to the pipeline ring but is output to a specific communication port (all packets except the packet arriving at E are output to the E port).

When PEACT = 1 and INS = 1, it operates in the interface mode, and packets arriving at the N port and the S port are S ports except those destined for the host computer.
Branch to the N port, and branch to the host computer to the E port. The packet arriving at the W port is branched in the S direction only when the destination processor number is within a predetermined range, and the other packets are passed toward the E port.

The above is an example of the routing algorithm, but the present invention is not limited to this.

Next, FIG. 7 shows an example of a parallel processing computer system constituted by using the element processor of the present invention provided with the communication control unit as described above, and the embodiment of the present invention will be described in more detail.

In FIG. 7, PE00 to PE33 are element processors set to the processor mode, and NIF is an element processor set to the interface mode. In the figure, the data output from the host computer is shown in FIG. 4 (c) or (e) in the host interface.
Is input to the WIF port of the NIF via the input line (IN), and is branched to the S port only when the destination processor number is within the range of 00 to 33, and reaches the W port of PE00. . In the 4 × 4 processor group set in the processor mode, the parallel processing type program is executed while performing packet communication at the shortest distance by the self-routing function as described above. A packet destined for the host computer having MODE = 00 is generated in the PE. This packet is transferred to PE03 and reaches the N port or S port of the NIF. In the NIF, a packet of MODE = 00 is branched to an E port and output to a host interface via an output line (OUT).

Next, FIG. 8 shows another example of the parallel processing computer system constituted by using the element processor of the present invention provided with the communication control unit as described above, and the embodiment of the present invention will be described in more detail. .

In FIG. 8, PE00 to PE73 are element processors set to the processor mode, and include NIF13, NIF33, and NIF5.
3. NIF 73 is an element processor set to interface mode. In the figure, data output from the host computer is converted into the format shown in FIG. 4 (c) or (e) by the host interface, input to the W port of the NIF 73 via the input line (IN), and processed at the destination processor. Only when the number falls within the range of 60 to 73, the port is branched to the S port and reaches the W port of the PE 60. Otherwise, it is passed to the W port of NIF53. Similarly, P
In the E53 W port, the destination processor number is 40-5
Only data within the range of 3 is branched to the S port, and the destination processor number is
Only the data within the range of 20 to 33 is branched to the S port, and only the data having the destination processor number within the range of 00 to 13 is branched to the S port at the W port of PE13. The operation in the element processor group set to the processor mode is almost the same as that described in FIG.

From the above description, by the element processor of the present invention,
A so-called self-routing function for performing communication between processors in the parallel processing device at the shortest distance based on a lattice-like processor connection network, a function of branching and outputting a result packet as a calculation result to the outside of the parallel processor (host computer), It can be seen that all the functions of branching data input from outside the parallel processor toward a predetermined processor group and inputting the data can be realized.

(G) Effects of the present invention As is apparent from the above description, according to the present invention, a high-performance element that can operate as a processor that is a constituent unit of a parallel computer and as an input / output interface between those processors and the outside. A processor can be provided. Furthermore, the present invention realizes both the function as a unit processor for parallel processing and the function as an input / output interface by developing one kind of hardware or LSI, thereby greatly shortening the development period of a parallel processing system, , While reducing manufacturing costs,
It is also possible to reduce the size of the system.

[Brief description of the drawings]

FIG. 1 is a system diagram showing a parallel computer constituted by element processors of the present invention, FIG. 2 is a block diagram showing a schematic configuration of the processor of the present invention, and FIG. 3 is a schematic diagram of a main part of the processor of the present invention. 4 (a) to 4 (e) are diagrams showing the structure of a packet, FIG. 5 is a correspondence diagram showing a part of the identification code of the packet, FIG. 6 is a diagram showing the structure of a processor number register inside the processor of the present invention, FIG. 7 is another block diagram of a parallel computer configured using the element processor of the present invention.
The figure is a further configuration diagram of a parallel computer configured using the element processor of the present invention. (PE): Processor, (PS): Program storage,
(EXE) Command execution unit, (NC) Communication control unit, (NI
F)… Network interface.

Claims (2)

(57) [Claims] A plurality of processors are arranged in rows and columns, and a plurality of vertical communication lines for cyclically connecting each vertical processor row and a plurality of horizontal communication lines for cyclically connecting each horizontal processor row. A parallel processing device for performing data communication between the processors, and further, inserted into at least one of the plurality of vertical communication lines or the plurality of horizontal communication lines to mediate transmission and reception of data with the outside of the parallel processing device. An element processor serving as a constituent unit of a parallel computer system having at least one input / output interface for performing, the element processor having at least two types of operation modes of a processor operation and an interface operation. Operates as a processor which is a structural unit of the parallel processing device configured in the matrix mode, and operates in an interface operation mode. Operates as an input / output interface that mediates the transmission and reception of data to and from the outside of the parallel processing device. And four internal communication ports for communication with the data processing unit. The communication control unit of the element processor communicates with the communication data through one of the communication ports. When the element processor is in the processor mode, the destination processor number held by the communication data is compared with its own processor number. If the two do not match, the data is replaced by
Of the four adjacent communication ports, the communication port selectively outputs to the communication port whose distance to the destination processor is the shortest, and the two match, and the external flag held in the communication data indicates that the data is processed in parallel. If it is indicated that the data is to be processed inside the device, the data is input to the data processing unit of its own processor through the internal communication port, and the data is processed. When the external flag held by indicates that the data is to be output to the outside of the parallel processing device, the data is not processed by its own processor, and the data is not processed by its own processor. Output to the specified communication port, wherein the element processor is in the interface mode and the communication data is transmitted from the processor of the parallel processing device. When the external flag held by the data indicates that the data is to be processed inside the parallel processing device, the data is passed through as it is and returned to the parallel processing device, and the data is held. If the external flag indicates that the data is to be output outside the parallel computer, the data is branched out of the parallel computer; the element processor is in the interface mode; One adjacent communication port is used for coupling to the parallel processing device, and two adjacent communication ports in the row direction are used for connection with the outside of the parallel processing device. When communication data from the outside of the parallel processing device arrives via the CPU, if the value of the destination processor number held by the data is within a predetermined range, the data is queued. And the data is transferred to the parallel processing device, and if the value of the destination processor number does not fall within a predetermined range, the data is passed to the other communication port in the row direction. Element processor of parallel computer. 2. A plurality of processors are arranged in rows and columns, and a plurality of vertical communication lines cyclically connecting each vertical processor row and a plurality of horizontal communication lines cyclically connecting each horizontal processor row. A parallel processing device for performing data communication between the processors, and further, inserted into at least one of the plurality of vertical communication lines or the plurality of horizontal communication lines to mediate transmission and reception of data with the outside of the parallel processing device. An element processor serving as a constituent unit of a parallel computer system having at least one input / output interface for performing, the element processor having at least two types of operation modes of a processor operation and an interface operation. Operates as a processor which is a structural unit of the parallel processing device configured in the matrix mode, and operates in an interface operation mode. Operates as an input / output interface for mediating data transmission / reception with the outside of the parallel processing device, wherein the element processor is in an interface mode, and two adjacent communication ports in the column direction are connected to the parallel processing device. When two adjacent communication ports in the row direction are used for connection with the outside of the parallel processing device, communication data from outside the parallel processing device through one communication port in the row direction is used. Upon arrival, if the value of the destination processor number held by the data falls within a predetermined range, the data is branched to a communication port in the column direction and transferred to the parallel processing device, and the value of the destination processor number is obtained. If the data does not fall within a predetermined range, the data is passed to the other communication port in the row direction.