JP2975460B2 - Logarithmic compression type differential amplifier circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logarithmic compression type differential amplifier among differential amplifiers of a basic integrated circuit.

[0002]

2. Description of the Related Art As a conventional example of this kind, there is a circuit shown in FIG. The two-input signal α input to the differential input terminal D _IN is differentially amplified by a first differential amplifier circuit D including transistors Q1, Q2, and the like. The first and second logarithmic compression diodes Q5 and Q6 are connected to the collectors of the transistors Q1 and Q2, respectively.
Are connected respectively. Two differential outputs of the first differential amplifier circuit D are connected to first and second logarithmic compression diodes Q5 and Q6.
, And is converted into a voltage, and is guided to a second differential amplifier circuit B via a level shift circuit E described later. The second differential amplifier circuit B includes a transistor Q
7, are composed of Q8 like, the second output of the level shift circuit E and the differential amplifier, and outputs a differential second output signal to the differential input terminal D _OUT in voltage.

The level shift circuit E includes a transistor Q101
, The diode Q103 ·· Q _n-1, a level shift circuit comprising a constant current source I _7, transistors Q102, the diode Q104 · · Q _n, and a level shift circuit comprising a constant current source I _8, both The circuit is exactly the same. The former circuit includes a first logarithmic compression diode Q
5, the level of the cathode voltage of the transistor Q7 is shifted.
In the latter circuit, the cathode voltage of the second logarithmic compression diode Q6 is lowered, and output to the base of the transistor Q8. The level shift amount is determined by the number of diodes Q103 and Q104.

FIG. 3 shows only one of the different types of level shift circuits E '. That is, those with a resistor R4 instead of the diode Q103, the level shift amount is determined by the resistance value and the constant current source I ₇ of the resistor R4.

[0005]

SUMMARY OF THE INVENTION Second differential amplifier circuit B
The reason why the level shift circuit E (or E ′) is provided in the input stage is that the bias voltage of the transistors Q7 and Q8 is set to be lower, so that the dynamics of the differential output of the second differential amplifier circuit B The idea is to have a large range. However, when the level shift circuit E using a diode is used, there is a disadvantage that the dynamic range of the differential output is limited due to the temperature coefficient of the diode Q103 and the like. In particular, when the number of the diodes Q103 and the like is large, the above-mentioned disadvantage becomes remarkable. On the other hand, when the level shift circuit E 'using a resistor is used, there is a disadvantage that the frequency characteristic of the differential output is impaired by an inductance component and a capacitance component included in the resistor R4.

SUMMARY OF THE INVENTION The present invention has been made in view of the above background, and an object of the present invention is to provide a logarithmic compression type differential amplifier circuit capable of maximizing an output dynamic range without deteriorating frequency characteristics. To provide.

[0007]

Logarithmic compression type differential amplifier circuit according to the present invention SUMMARY OF THE INVENTION, the first for outputting the second input signal input to the differential input amplifier and a differential second output signal with current differential Current
And output differential amplifier circuit, the first, second logarithmic compression diode for each logarithmically compress the differential second output signal output from the first current output type differential amplifier circuit, the first current Out
Differential output terminal of the force type differential amplifier circuit and the first and second logarithms
Inserted between the anode of the compression diode and
First and second buffer transistors ,
A second differential amplifier circuit that differentially amplifies each anode voltage of the second logarithmic compression diode as two differential inputs and outputs a differential output to a differential output terminal; and the first and second logarithmic compression circuits. For
It is characterized by Ru comprising <br/> a voltage setting circuit for setting the respective cathode voltage of the diode.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a logarithmic compression type differential amplifier according to the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram of the embodiment circuit. The two-input signal α input to the differential input terminal D _IN is guided to the differential input of the first differential amplifier circuit A.

The first differential amplifier circuit A includes a transistor Q
1, Q2, the constant current source _{I 1, I 2, I 3} , I 4, resistors R1
And differentially amplifies the two-input signal α input to each base of the transistors Q1 and Q2, and outputs the differential two-output signal β as current from each collector of the transistors Q1 and Q2. I have. One of the two differential dual output signals β is guided to the first logarithmic compression diode Q5 via the emitter and the collector of the transistor Q3, and similarly, the other of the differential dual output signal β is connected to the emitter and the collector of the transistor Q4. A second logarithmic compression diode Q6 through the collector
It is led to.

The bases of the transistors Q3 and Q4 are common, and a constant voltage source V2 is connected to the bases. The transistors Q3 and Q4 are provided to keep the collector potentials of the transistors Q1 and Q2 constant irrespective of the anode voltages of the first and second logarithmic compression diodes Q5 and Q6, and function as buffers. .

The first and second logarithmic compression diodes Q5,
The differential input of the second differential amplifier circuit B is connected to each anode of Q6, while the cathodes of the first and second logarithmic compression diodes Q5 and Q6 are shared, and will be described later. The voltage setting circuit C is connected. The first and second logarithmic compression diodes Q5 and Q6 logarithmically compress the two differential output signals β and convert them into voltages.

The second differential amplifier circuit B includes a transistor Q
7, Q8, constant current source I _5, resistors R2, R3 are composed of a second input to the base of the anode voltage and the transistor Q8 of the first logarithmic compression diode Q5 which is input to the base of the transistor Q7 Is differentially amplified using the anode voltage of the logarithmic compression diode Q6 as a differential input, and the differential output is converted into a voltage by resistors R2 and R3 and output to a differential output terminal _DOUT .

Next, the voltage setting circuit C will be described. In this embodiment, the voltage setting circuit C comprises a transistor Q9, a constant voltage source V ₁ , and a constant current source I ₆ . A power supply is connected to the collector of the transistor Q9, and first and second logarithmic compression diodes Q5 and Q6 are connected to the emitter.
Besides common cathodes of which are connected, it is grounded via a constant current source I _6. The base of the transistor Q9 is connected to a constant voltage source V _1. That is, the voltage setting circuit C, the cathode voltage of the first, second logarithmic compression diode Q5, Q6, the voltage V ₁ of the constant voltage source V ₁
Is set to a voltage obtained by subtracting the base-emitter voltage of the transistor Q9 from the above equation. Therefore, the bias voltage of the transistors Q7, Q8 of the second differential amplifier circuit B is determined by the voltage V _1.

In the present embodiment, the constant current source I ₆ in the second differential amplifier circuit B is constituted by a current mirror circuit. However, the constant current source I ₆ is set to such a value that the transistors constituting the current mirror circuit are not saturated. When setting the voltage V _1, it can be set to maximize the dynamic range of the differential output of the second differential amplifier circuit B.

Therefore, according to the logarithmic compression type differential amplifier circuit having the above-described configuration, the voltage setting circuit C merely sets the bias voltages of the transistors Q8 and Q9 in the second differential amplifier circuit B. Since the configuration is such that the differential two output signal β does not flow, unlike the case of the conventional example,
The dynamic range of the differential output of the second differential amplifier circuit B is not limited due to the temperature coefficient, and the frequency characteristics are not impaired. Therefore, it is possible to sufficiently exhibit the inherent performance of the circuit.

The logarithmic compression type differential amplifier circuit according to the present invention is not limited to the above-described embodiment. The voltage setting circuit has a configuration capable of setting each cathode voltage of the first and second logarithmic compression diodes. Any form may be adopted as long as it exists.

[0017]

Effect of the Invention above, in the case of logarithmic compression type differential amplifier circuit according to the present invention, FIG. 2, the level shift circuit of FIG. 3
The bias voltage of the input stage of the second differential amplifier circuit is not used.
Since the pressure can be set, unlike the conventional case, the temperature coefficient does not become a problem and the dynamic range of the output of the second differential amplifier circuit is not limited, and the frequency characteristic is not changed. There is no loss. Therefore, the dynamic range of the output can be maximized without impairing the frequency characteristics. The logarithm of the present invention
According to the compression type differential amplifier circuit, the first current output type differential amplifier is used.
The gain adjustment of the width circuit is performed by the input stage of the second differential amplifier circuit.
The configuration does not affect the setting of the bias voltage at all.
Gain and output dynamic range, respectively.
First, it has the advantage that it can be set to the optimum value.
Things.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a circuit according to an embodiment of the present invention.

FIG. 2 is a diagram corresponding to FIG. 1 for explaining a conventional example.

FIG. 3 is a circuit diagram showing a part of a level shift circuit having a configuration different from that shown in FIG. 2;

[Explanation of symbols]

D _IN differential input terminal D _out differential output terminal α dual input signal β differential dual output signal A first differential amplifier circuit Q5 first logarithmic compression diode Q6 second logarithmic compression diode B second Differential amplifier circuit C voltage setting circuit

Claims (1)

(57) [Claims] A first current output for differentially amplifying a two-input signal input to a differential input terminal and outputting a differential two-output signal as a current.
And a force-type differential amplification circuit, a first, second logarithmic compression diode for each logarithmically compress the differential second output signal output from the first current output type differential amplifier circuit, the first current Out
Differential output terminal of the force type differential amplifier circuit and the first and second logarithms
Inserted between the anode of the compression diode and
First and second buffer transistors ,
A second differential amplifier circuit that differentially amplifies each anode voltage of the second logarithmic compression diode as two differential inputs and outputs a differential output to a differential output terminal; and the first and second logarithmic compression circuits. For
A logarithmic compression type differential amplifier circuit comprising: a voltage setting circuit for setting each cathode voltage of an electrode.