JP2974398B2 - Automatic wiring method - Google Patents

Description

The present invention relates to an automatic wiring system for automatically designing a wiring pattern of a semiconductor integrated circuit.

(Prior Art) A layout CAD program operating on a general-purpose computer is used for automatic design of a wiring pattern of a semiconductor integrated circuit. An example of this is shown in FIG. Figure 12 shows the wiring area
This is an example in which a wiring route between terminals of the same number on 110 is to be determined. A typical method for determining the wiring route between terminals is the maze method (CYLee, “An algorithm for path connec
tions and its applications, "IRE Trans.Electron.Com
put., Vol. EC-10, pp. 346-365, 1961.) and the line segment search method (K. Mikami etc., “Acomputer program for optimal ro
uting of printed circuit connections. "IFIPSProc., p
pp. 1475-1478, 1968.). Regardless of the wiring processing using either the maze method or the line segment search method, in the conventional automatic wiring method, as shown in FIGS. To ask for. In such an automatic wiring method, a huge processing time is consumed when the circuit becomes large-scale.

In order to solve this problem, an automatic wiring method that performs wiring processing in parallel by a plurality of computers (processors) has been proposed in recent years (H. Nelson Brady, “MIMD Organization for the Ex
ecution of Interconnection routing Alogorithm. "IEE
E Circuits and Device Magazine, pp. 39-43, 1985; JP-B-62-115574; JP-B-62-186351).

An example of this method will be described with reference to FIG. FIG. 13 is an example in which a wiring route between terminals of the same number is to be determined. In this parallel wiring method, first, as shown in FIG. 13B, a wiring area 110 is divided into a plurality of small areas 120, 121, 122, 123.
(In this example, four divisions). Subsequently, FIG. 13 (c)
The wiring route between the terminals of the same number included in the same small area is determined as follows (in this example, terminals 1, 2, 3, 4, 5, 6
Determine the path between). If the wiring paths between all the terminals are determined, the process is terminated. However, if there are unwired terminals, some small areas are combined to form a new small area. In the example of FIG. 13 (c), there are unwired terminals 7, 8, 9 and 10, so as shown in FIG. 13 (d), a small area is synthesized and a new small area 125 (in this example, the wiring (Same as the area 110), and a wiring path between terminals included in the new small area 125 is determined. Further, when there is an unwired terminal, the synthesis of the small area is repeated to determine the wiring route between all the terminals.

Here, consider a case where the wiring area 110 is divided into N small areas and the processing is performed using N processors. In the first step, the parallelism is N because all N processors can be operated. Next, in order to determine the wiring route between the unwired terminals in the processing of the first step,
It is necessary to combine several small areas into a new small area and determine a wiring path between unwired terminals in the new small area. This is the second step. In order to simplify the problem, it is assumed that four (2 × 2) adjacent small areas are combined to form a new small area. At this time, the wiring region 110 is divided into N / 4 small regions. Thus, in the second step, only N / 4 processors need to be operated. In the third step, N /
You only need to run 16 processors. As described above, in the parallel wiring method as exemplified, the small area is synthesized every time there is an unwired terminal pair, and thus the number of divided wiring areas decreases as the processing proceeds. As a result, the degree of parallelism gradually decreases, resulting in waste of hardware.

On the other hand, FIG. 14 shows a distribution graph of the number of wirings as a layout result of a general actual circuit. In this graph, a cut line 130 is inserted in the wiring region 110 as shown in FIG. 15, and the number of wires crossing each cut line 130 is shown on a vertical axis. From this graph, it can be seen that the wiring crosses all the cut lines 130 almost uniformly. Therefore, in the parallel wiring method as exemplified, the wiring always crosses the boundary between the small areas, so that finally, if all the small areas are not hierarchically combined into one area, the wiring may not be formed. It cannot be completed.

(Problems to be Solved by the Invention) As described above, the conventional automatic wiring method has a problem that it becomes impossible to perform wiring processing of a large-scale circuit in a practical processing time. Further, the parallel wiring method for solving this problem also has a drawback that the processor utilization efficiency is poor.

Therefore, the present invention has been made in view of such a conventional situation, and an object of the present invention is to execute a wiring route by performing automatic wiring processing simultaneously and in parallel by efficiently using a plurality of processors. An object of the present invention is to provide an automatic wiring processing method capable of shortening a processing time to be determined.

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, the present invention provides a method for determining a wiring path between a plurality of terminals arranged on a semiconductor integrated circuit or a printed circuit board. The length of one side of the small region is obtained from the analysis result of the plurality of terminal distances that become potentials, the wiring region is divided by the small region of this size, and the small regions are combined to form a plurality of middle regions, In these middle areas, the horizontal or vertical distance between the terminals is shorter than one side of the small area. Wiring paths between terminals are simultaneously determined in parallel, and the middle area in which the wiring paths are determined is returned to the small area again. Divide and combine the divided small areas to form a new middle area different from the previous one, and in this new middle area, a terminal whose horizontal or vertical distance between terminals is shorter than one side of the small area. Decision of wiring route between them in parallel It is configured to Migihitsuji.

(Operation) In the above configuration, the present invention determines the length of one side of a small region for dividing a wiring region from analysis of a plurality of distances between terminals to be connected, and decomposes the wiring region into a plurality of small regions. I do. A wiring path longer than the length of one side of the small area is sequentially wired.

Combining two or more small areas to form a plurality of medium areas,
The processing for determining the wiring route in the middle area is performed by a plurality of processors simultaneously and in parallel. As a result, the wiring paths between the terminals whose horizontal or vertical distance between the terminals is shorter than one side of the small area are determined simultaneously and in parallel. Each time a wiring route in the middle area is determined, the middle area is decomposed again into small areas. Recombines the decomposed small areas again,
Construct a new middle area different from the previous one. The process of causing the processor that has completed the process to determine the wiring route in the new middle area is repeatedly performed.

As a result, wiring paths between terminals in a plurality of middle regions, in which the distance between terminals in the horizontal or vertical direction is shorter than one side of the small region, can be determined simultaneously in parallel, and the utilization efficiency of the processor decreases. There is no.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is an example of a system configuration for realizing the automatic wiring system of the present invention.

The system shown in FIG. 1 includes a LAN (local area network) 1, one client computer (hereinafter abbreviated as a client) 2, and a plurality of server computers (hereinafter abbreviated as "client").
3).

The client 2 performs reading of element and terminal data whose arrangement is determined, preprocessing, division of a small area of a wiring area, synthesis of a medium-sized area (hereinafter, abbreviated as a medium area), and the like. The client 2 also has a function of controlling the server 3.

The server 3 is about to perform wiring within the small area specified by the client 2. With a plurality of servers 3,
Wiring processing in a plurality of middle areas is performed simultaneously in parallel.

The client 2 and the server 3 perform communication and transfer data 4 using the LAN 1.

Although FIG. 1 shows a system configuration using LAN1, the present invention is not limited to this, and a parallel processing computer having a semiconductor memory device shared by a plurality of processors connected by one bus, or a plurality of processors It is also possible to realize with a parallel processing computer connected between them by a communication channel.

The above is the configuration of the automatic wiring system according to the present invention. Next, the wiring processing according to the present invention will be described.

FIG. 2 is a process flow showing an embodiment of the automatic wiring system according to the present invention.

In the figure, the portion of the process 11 indicated by a broken line is a process performed by the client 2 alone, and the portion of the process 12 is a process performed by the server 3 and the client 2 in parallel. Processing 12
Steps 31 to 33 in the middle are steps performed by the plurality of servers 3 in parallel.

First, when the client 2 reads the arrangement data (step 21), it sets a net (a set of equipotential terminals to be connected to each other by a wiring pattern. In the wiring processing by the server 3, a wiring route connecting terminals included in the same net is determined. Usually, the net is composed of two or more terminals.) Into two-terminal nets (step 22). For example, a net 41 composed of terminals P1 to P5 shown in FIG. 3A is disassembled into four two-terminal nets 42, 43, 44 and 45 shown in FIG. 3B. In the wiring processing described below, the wiring paths of these two-terminal nets are determined. In the example of FIG. 3 (b), the terminal P1
Between P4 and P4, between P4 and P5, between P3 and P4, between P2 and
The route between P3 will be determined. When disassembling into two-terminal nets, they are disassembled into two terminals so that the distance between the terminals is as short as possible. That is, on a complete graph in which the terminals are the nodes on the graph and the Manhattan length between the terminals is the weight of the branch, the maximal tree with the minimum cost is obtained (JBKuruskal, “On the shor
test spanning subtree of a graph and the traveling
salesman problem, "Proc.Amer.Math.Soc. 7: 1, pp-48-
50,1956.).

Next, the distribution of the distance between the terminals of the two-terminal net is obtained (step 23). Here, for example, as shown in FIG.
When P1 and P4 are arranged, the distance n1 between the terminals is defined by the following function.

n1 = MAX (Δx, Δy) Δx: horizontal distance between terminals Δy: vertical distance between terminals In FIG. 4, since Δx> Δy, the distance n1 between these two terminals is Δx.

This distance n1 is obtained for all the two-terminal nets, and the cumulative frequency distribution of n1 of the post-arrangement data of elements and terminals is analyzed. FIG. 5 shows an example of the analyzed cumulative frequency distribution. The horizontal axis is n1, and the vertical axis is the cumulative number of nets ([number of 2-terminal nets / total number of all 2-terminal nets] × 100 [%]). Step 2
In 3, we find such a distribution.

Subsequently, the length L of one side of the small area is obtained from the cumulative frequency distribution (step 24). That is, as shown in FIG.
As a parameter, the cumulative α of the two-terminal net (0.0 ≦ α <1.
0, generally 0.8-0.9) is manually entered and this α
The distance L between the two terminals corresponding to is obtained.

Furthermore, the distance n1 (Δ
x or Δy) is selected as a two-terminal net larger than L, and a wiring route between these terminals is determined (step 2).
Five).

Next, the wiring area is decomposed into small areas each having a length of L (step 26), and the data of each small area is stored in a storage area in the client 2 (step 27). Each small area data is given a unique identification number.

The processing performed by the client 2 alone has been described above. After these processes are completed, the client 2 instructs the server 3 to perform wiring processes in parallel. Hereinafter, processing performed by the client 2 and the server 3 in parallel will be described. In the present embodiment, a case will be described in which one middle area is synthesized from four adjacent small areas.

At first, since all the servers 3 are not performing the processing, the processing moves from step 28 to step 29 (Yes in step 28). The client 2 reads out four (2 × 2) adjacent small area data from the storage area, synthesizes one middle area, and transfers the middle area data to the server 3 (steps 29 and 30). .

The plurality of servers 3 receive the middle area data, and perform wiring between two unwired terminals in the middle area in parallel at the same time (step
31 and step 32). Of the plurality of servers 3, the server 3 that has completed the wiring process in the middle area returns the result to the client 2 (step 33).

The client 2 again divides the middle area data sent from the server 3 after the processing into four small area data and stores them in the storage area (steps 35 to 3).
7). Since the wiring processing of all the servers 3 has not been completed and the termination condition described later has not been satisfied, the process returns to Step 28 (No at Step 38).

Since there is a server 3 that has not performed the processing, the client 2 synthesizes a new middle area. At this time, if the new middle area geometrically overlaps with the middle area being processed,
The server 3 waits until the processing of the middle area ends and the server 3 is decomposed into small areas. When there is no longer any geometric overlap in the new middle area, steps 30 to 38 are repeated.

As described above, the wiring processing in the middle area can be performed simultaneously and in parallel as long as the middle area does not have a geometrical overlap. Therefore, when the wiring area is divided into 4N small areas, the processing can be performed in parallel by the N processors (servers 3). However, the number of processors is smaller than the number of middle areas because the number of middle areas is several hundred in actual processing.

If it is determined in step 28 that all servers 3 are performing the process, the process proceeds to step 34, and if none of the servers 3 is completed, steps 28, 34, and 38 are repeated (step 28).
28 denial, 34 denial, 38 denial). During this time, if there is any server 3 whose processing has been completed in step 34, data in the middle area is received from this server 3 (step 34 affirmative and step 35), and the same processing is performed thereafter.

The above processing (steps 28 to 38) is repeated until there are no unwired terminals. Specifically, the process is repeated until the following condition is satisfied.

First, in FIG. 6 (a), there are four types of configuration patterns of the middle area 62 including the small area 61 as shown in FIGS. 6 (b) to 6 (e); PT-A, PT-B, There are PT-C and PT-D. FIG. 7 shows an example of the wiring region 110. The small region 70 is a small region generated inside, and the small regions 71 to 74 are small regions generated at four corners. The small regions 75 to 78 (hatched portions in the drawing) are small regions generated outside.

The repetition of steps 28 to 38 stops when all of the following nine conditions are satisfied. (1) Each small area 70 was processed in all the middle areas of the four patterns shown in FIGS. 6 (b) to 6 (e).

(2) The small area 71 was processed in the middle area of the PT-A pattern shown in FIG.

(3) The small area 72 was processed in the middle area of the PT-B pattern shown in FIG. 6 (c).

(4) The small area 73 was processed in the middle area of the PT-C pattern shown in FIG.

(5) The small region 74 was processed in the middle region of the PT-D pattern shown in FIG.

(6) Each small region 75 was processed in both the PT-B and PT-C middle regions shown in FIGS. 6 (c) and 6 (d).

(7) Each small area 76 was processed in both the PT-A and PT-C pattern middle areas shown in FIGS. 6 (b) and 6 (d).

(8) Each small region 77 was processed in both the PT-A and PT-D pattern middle regions shown in FIGS. 6 (b) and 6 (e).

(9) Each small region 78 was processed in both the PT-B and PT-D pattern middle regions shown in FIGS. 6 (c) and 6 (e).

When all of the above nine conditions are satisfied, the client 2
Reads out all the small area data from the storage area, combines them, and outputs the wiring result (steps 38 to 40).

In step 25, since the wiring of the two-terminal net in which the distance n1 (Δx or Δy) between the terminals is longer than L is performed, all the remaining unwired two-terminal nets are within the two small areas where the terminals are adjacent. I'm in it. Therefore, when the middle area is formed by the above four patterns and wiring is performed, wiring of all two-terminal nets is completed.

 FIGS. 8 and 9 are schematic diagrams of the above processing.

FIG. 8 is a schematic diagram showing the processing of steps 22 to 27 by the client 2. As shown in the figure, a plurality of terminals 81 having the same potential are decomposed into a two-terminal net 82. L between terminals 81
The wiring path 111 of the longer two-terminal net 82 is determined. Then, the wiring area 110 is decomposed into a plurality of small areas 61 each having a side length L, and the small area data 4 is stored in the storage area 83.

FIG. 9 is a schematic diagram showing the parallel processing of steps 28 to 38. In this figure, the wiring area 110 is divided into 16 small areas 16 and four adjacent small areas 16
Are synthesized. Also, a case where parallel processing is performed by two servers 3 is shown.

FIG. 9 (a) shows steps 28 to 32, in which the small area 1,2,5,6 and the small area 11,12,15,
16 are combined to form two middle regions 91. The data 4 in the middle area 91 is transferred to two servers 3 respectively. Further, the wiring processing in the middle area 91 is performed by the server 3 that has received the data 4.

FIG. 9 (b) shows steps 33 to 37, and the server 3 (the left side in the figure) that has completed the process transmits the data 4 in the middle area 91 to the client 2. The client 2 decomposes the received data 4 into small areas 1, 2, 5, and 6 again and stores the data in the storage area 83. By this wiring processing, the processing of the PT-B pattern shown in FIG. 6 (c) is completed. Therefore, the wiring paths between the terminals in the small area 1 and between the terminals in the small areas 2, 5, and 6 to be connected to the terminals in the small area 1 are all determined. The server 3 on the right side in the figure is in the process of wiring.

FIG. 9C shows steps 28 to 32 which are repeated when the server 3 ends the processing. The small areas 5, 6, 9, and 10 are combined by the client 2 to form a new middle area 91. This new middle area 91 is transferred to the server 3 as in FIG. 9 (a), and the wiring processing in the middle area 91 is performed.

As described above, in the present invention, the wiring processing of the middle area is performed by the plurality of servers 3 in parallel. Next, an estimation of the processing speed according to the present invention will be described.

In general, the performance of the parallel processing can be evaluated by the following equation.

P = (Sp + Ss) / (Sp / N + Ss) (1) P is a processing speed improvement ratio by parallelization. Sp is the processing time when the part that can be parallelized during processing is performed by a single processor, Ss is the processing time of the part that cannot be parallelized during processing, and N is the number of processors. If Ss = 0, the value of P is N, which means that N-times speedup can be obtained by using N processors. P = N is a performance value by ideal parallel processing. Therefore, if Ss can be made small and N can be made large, the performance by parallel processing can be improved.

In the present invention, Ss is the time required for the processing 11 performed by the client 2 alone, and Ss is the processing 12 performed in parallel.
Is the processing time required when it is performed by a single processor. To simplify the problem, only the actual wiring time is considered, the portion required for Ss is only step 25, and the time for determining the wiring path is assumed to be a constant value.

In the present invention, the larger the number of two-terminal nets (nets whose terminals are longer than L) for determining the wiring route in step 25, the greater the number.
Since Ss increases, the performance due to parallel processing decreases.
Further, as the number of divisions of the wiring area is smaller, more processors cannot be used, so that the performance is reduced. This is the value of L obtained in step 24 and the parameter α
(0.0 ≦ α <1.0). From the simplification assumption above, the value of Ss is Ss = Sp (1−α) / α. Further, when the length of one side of the wiring region and V, (V / L) can be divided into ^two subregions, in this case ^{N = (V / L) 2} /4
Becomes From the above, the equation (1) becomes P = 1 / {4α (L / v) ² + (1−α)}. Therefore, if α can be increased and V / L can be increased, the performance by parallel processing can be improved. (1-α) is the ratio of sequential processing included in the processing, V /
L is a value proportional to the number of divisions of the wiring area.

10 and 11 show graphs of the number of inter-terminal distances n1 and the cumulative frequency distribution after the actual circuit is arranged by the layout arrangement program. FIGS. 10 (a) and 11 (a) are graphs showing the number of distances n1 between terminals.
FIGS. 10 (b) and 11 (b) are cumulative frequency distribution graphs of the distance n1 between terminals. FIG. 10 is a graph in the case where a circuit having about 1700 two-terminal nets is arranged in a gate array matrix having a scale of 5000 gates. FIG. 11 is a graph showing a case where a circuit having about 13000 two-terminal nets is arranged in a gate array matrix having a scale of 38000 gates. As can be seen from these graphs, the inter-terminal distance n1 in the net of the circuit arranged by the normal layout arrangement program is extremely concentrated on a short place. In addition, this tendency does not depend on the circuit scale and the size of the wiring area. From this, it is possible to reduce L while maintaining α at a sufficiently large value. Furthermore, since the cumulative frequency of the inter-terminal distance does not depend on the circuit scale and the size of the wiring area, the size of the small area becomes almost constant regardless of the circuit scale. Therefore, as the circuit becomes larger, V / L becomes larger and the number of divided wiring regions can be increased, so that the effect of the parallel processing is increased.

In the present embodiment, the process (step 25) of determining the wiring path between the terminals whose distance n1 between the terminals is equal to or greater than the length L of one side of the small region is performed before the process 12 of performing the parallel processing. However, the present invention is not limited to this. For example, a similar effect can be obtained by performing this processing after step 39.

[Effects of the Invention] As described above, according to the automatic wiring method according to the present invention, the determination processing of the wiring routes in the plurality of middle regions is performed simultaneously and in parallel using the plurality of processors. As a result, the processor can be used efficiently, and the processing time for determining the wiring path can be significantly reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an example of a system configuration for realizing the automatic wiring system of the present invention. FIG. 2 is a processing flow for explaining the processing operation of the automatic wiring system of the present invention. FIG. 4 is a diagram for explaining the decomposition into two-terminal nets and the distance between terminals. FIG. 5 is a cumulative frequency distribution graph used for obtaining the length L of one side of a small region. FIGS. FIGS. 8 and 9 are schematic diagrams showing the state of the wiring process according to the present invention, and FIGS. 10 and 11 are diagrams showing the number of distances between terminals. 12 and 13 are diagrams for explaining a conventional automatic wiring method, and FIGS. 14 and 15 are diagrams showing distribution of wiring paths on a wiring region. 1 LAN (local area network) 2 Client computer 3 Server computer 4 Data 41 Net 42,43,44,45,82 2-terminal net 61,70-78 Small area 62: Middle area 81: Terminal 83: Storage device 91: Middle area being processed 110: Wiring area 111: Wiring path

Claims (1)

(57) [Claims] When a wiring path between a plurality of terminals arranged on a semiconductor integrated circuit or a printed circuit board is determined, the length of one side of a small region is determined from an analysis result of a distance between a plurality of terminals having the same potential. The wiring area is divided by the small area of this size, the small areas are combined to form a plurality of middle areas, and the horizontal or vertical distance between the terminals in the middle area is equal to one side of the small area. Determination of the wiring path between the shorter terminals is performed simultaneously and in parallel, the middle area in which the wiring path is determined is again divided into the small areas, and the divided small areas are combined to form a new middle area different from the previous one. An automatic wiring method in which a wiring path between terminals in the new middle area, in which the distance between terminals in the horizontal or vertical direction is shorter than one side of the small area, is determined simultaneously and in parallel.