JP2971683B2 - Burst signal generator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a burst signal generator for outputting a burst signal used in TDMA (Time Division Multiple Access) communication.

[0002]

2. Description of the Related Art Generally, TDMA is used as a communication system in JDC (Japanese digital car phone), ADC (US digital car phone), GSM (European digital car phone), JDCT (Japan digital cordless car phone) and the like.
(Time Division Multiplexing) communication is employed.

In this TDMA communication, data is transmitted and received between a fixed station and a plurality of mobile stations. In this case, as shown in FIG. 8, each mobile station transmits from its own station to a fixed station or another fixed station via this fixed station in a time slot 1 designated to itself in a transmission frame repeated at a constant period _TF . The data to be transmitted to the station is incorporated and transmitted.

[0004] Further, in a time slot 1 having a fixed time width T _S assigned to each mobile station, for example, a total of 24
0-bit data is set. More specifically, as shown, a 4-bit transient response ramp time R, a 2-bit start symbol SS, and a 6-bit preamble P
R, 16-bit synchronization word UW, 4-bit channel type CI, 16-bit SACCH (synchronous allocation control)
A channel SA, a 160-bit information (text) channel TCH in which data to be transmitted is set, a 16-bit cyclic code CRC, a 4-bit transient response ramp time R, and a 12-bit guard time G are set.

The data incorporated in the time slot 1 intermittently allocated in the transmission frame repeated at a constant cycle T _F is called burst data 2. When such burst data 2 is transmitted to a distant place, it is modulated by a high-frequency carrier frequency signal and emitted as a burst signal 3 as shown in FIG.

[0006] Each burst signal 3 incorporated in each time slot 1 assigned to itself by each mobile station is received by the fixed station. In this case, the fixed station can receive each burst signal 3 of each time slot 1 allocated in each transmission frame without interference. The fixed station demodulates each received burst signal 3 into the original burst data 2 and extracts the data of the information channel TCH in the burst data 2.

In the burst signal generator,
A high frequency switch circuit that is turned on / off in synchronization with the duration T _S of the time slot is inserted in the final output stage. By providing such a high-frequency switch circuit, the duration T of the time slot 1 assigned to itself is maintained.
Since no signal leaks other than _S , adverse effects on the burst data 2 in the time slot 1 of another station are prevented beforehand.

In other words, the on / off ratio indicated by the power ratio between the on period T _S and the off period (T _F -T _S ) in the burst signal 3 increases, so that the fixed station receives a signal from each mobile station. The S / N for receiving the burst signal 3 increases.

[0009]

However, in the burst signal generator for outputting a burst signal as described above, a high-frequency switch circuit is used to simply turn on / off a high-frequency carrier modulated with burst data.
In the case where only the off-state control is performed, the high-speed on / off operation of the high-frequency switch circuit causes a problem that the frequency occupied bandwidth of the burst signal 3 is greatly increased.

Hereinafter, the problem will be specifically described.

FIGS. 10A and 10B show the same carrier frequency f.
FIG. 4 is a waveform diagram showing a continuous signal 4 having a _C and a burst signal 3. FIG. 10C is a frequency characteristic diagram of the continuous signal 4, and FIG. 10D is a frequency characteristic diagram of the burst signal 3.

[0012] peak level from the specified value (A dB) reduced frequency bandwidth W _B of the burst signal 3 at the position,
It can be seen that it is much wider than the frequency bandwidth W _C of the continuous signal 4. This is because the signal level of the burst signal 3 sharply rises and falls sharply at the start and end times of the time slot 1.

[0013] Thus, when the frequency bandwidth W _B of the burst signal 3 is large, it influences the burst signal 3 having the other carrier frequencies adjacent to the burst signal 3. That is, the leakage power to the adjacent channel increases. Therefore, it is necessary to increase the interval between adjacent carrier frequencies, which causes a problem that the frequency band of radio waves cannot be used effectively.

The present invention has been made in view of such circumstances, and by gradually increasing and decreasing the amplitude data of each bit data at the leading end and the trailing end of the burst data output from the burst data generating section, It is an object of the present invention to provide a burst signal generator capable of greatly reducing the frequency occupied bandwidth of an output burst signal and suppressing leakage power to adjacent channels as much as possible.

[0015]

In order to solve the above-mentioned problems, a burst signal generating apparatus according to the present invention provides a burst start signal input signal which indicates the start of a pre-assigned time slot in a transmission frame repeated at a constant period. In response, a burst data generator for outputting burst data stored in a time slot and generating an I / Q gate signal, and converting the burst data output from the burst data generator into a pair of baseband data I /
A Q data generating section, an envelope adding section for gradually increasing and decreasing each amplitude data of a predetermined number of bits at a leading end and a trailing end of each base band data output from the I / Q data generating section, and an envelope adding section A D / A converter for converting each baseband data with the envelope added thereto into each analog baseband signal, a quadrature modulator for orthogonally modulating each baseband signal output from the D / A converter, A frequency conversion circuit that amplitude-modulates the quadrature modulation signal output from the quadrature modulator with a high-frequency carrier frequency signal, a gate delay circuit that delays the I / Q gate signal by a signal delay in the I / Q data generation unit, An extended gate signal generation circuit for generating an extended gate signal obtained by extending the delayed gate signal output from the gate delay circuit backward by a predetermined number of bits. When a high-frequency switch circuit for outputting a burst signal is passed through a high-frequency quadrature modulated signal output from the frequency conversion circuit only extended gate signal application period is provided.

[0016]

In the burst signal generator having the above-described configuration, the burst data having the specified bit length output from the burst data generator is transmitted to the next pair of baseband by the next I / Q data generator. Converted to data. Then, the pair of baseband data is input to the envelope adding unit.

The envelope adding section gradually increases and decreases the amplitude data of a predetermined number of bits at the leading end and the trailing end of the input baseband data. Therefore, each amplitude data corresponding to a period from the start point in the baseband data until a predetermined number of bits such as 4 bits elapses is sequentially increased, becomes constant amplitude data after the predetermined number of bits elapses, and becomes a predetermined amplitude data before the end point. Each amplitude data corresponding to the period from the bit number position to the end position sequentially decreases. Therefore, each amplitude data of the baseband data output from the envelope adding section has a trapezoidal shape.

The digital baseband data to which the envelope has been added by the envelope adding section is converted into an analog baseband signal by the D / A converter. Then, each baseband signal is quadrature-modulated by the quadrature modulator. The quadrature modulated signal output from the quadrature modulator is converted into a signal having a high carrier frequency by a frequency conversion circuit.

On the other hand, the burst data generator generates an I / Q gate signal simultaneously with the generation of the burst data. This I
The / Q gate signal is delayed by a signal delay generated in the process of converting the burst data in the I / Q data generation unit into a pair of baseband data by the gate delay circuit to become a delayed gate signal. Further, the delayed gate signal becomes an extended gate signal extended backward by a predetermined number of bits by the next extended gate signal generating circuit.

The high frequency switch circuit allows the quadrature modulation signal to pass only during the application time of the extension gate signal. In this case, the transit time includes the duration of the baseband generated by the I / Q data generator, added to the envelope by the envelope adder, and converted to analog by the D / A converter. The leading and trailing ends of the burst-like quadrature modulated signal having the trapezoidal envelope characteristic are not blocked. Therefore, a steep rise and a steep fall do not occur in the burst signal output from the burst signal generator.

[0021]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a schematic configuration of a burst signal generator according to an embodiment. The clock signal generation circuit 11 sends a clock signal a having a cycle T _C corresponding to the data transmission rate to the continuous data generation unit 12, the burst data generation unit 13, and the extension gate signal generation circuit 14.
When an external clock is applied, the clock signal a is synchronized with the external clock.

The burst start signal generation circuit 15 sends a burst start signal b indicating the rise of the time slot 1 to the next burst data generation unit 13 at every fixed period T _F shown in FIG. When the external burst start signal c has been applied, the burst start signal generating circuit 15 outputs a burst start signal b in synchronization with the external burst start signal c. The external burst start signal c is applied to the terminal a of the switching circuit 16.

The continuous data generator 12 generates, for example, continuous data corresponding to the continuous signal 4 shown in FIG. 10A and applies the same to the terminal d of the switching circuit 17 instead of the burst data shown in FIG. Each time the burst start signal b is input, the burst data generation unit 13 creates burst data e having a format obtained by removing the last 12-bit guard time G in which no data exists from the format shown in FIG. The voltage is applied to the terminal b of the switching circuit 17.

Further, as shown in FIG. 7, the burst data generator 13 outputs a 16-bit output time obtained by adding the transient response ramp time R and the guard time G from the time slot duration from the burst start signal b input time. An I / Q gate signal g which is at a high (H) level only during the shortened period is sent to the terminal b of the switching circuit 16.

Normally, the common terminal c of each of the switching circuits 16 and 17
Is connected to the terminal b. Burst data e input from burst data generation unit 13 via switching circuit 17
Is converted into a pair of baseband data I and Q of, for example, 12 bits by an I / Q signal generation section 18 and then input to an envelope adding section 19.

The I / Q gate signal g passed through the switching circuit 16 is input to the gate delay circuit 24. The gate delay circuit 24 converts the I / Q gate signal g to, for example, 2 bits in order to compensate for a delay time generated when the burst data e in the I / Q data generation section 18 is converted into baseband data I and Q. And the like, and delays it by a predetermined bit and applies it to the envelope adding section 19 as a delayed gate signal m.

The I / Q data generating section 18 and the envelope adding section 19 are configured, for example, as shown in FIG.

The burst data e having the bit configuration shown in FIG. 8 and inputted from the burst data generator 13 to the I / Q data generator 18 is subjected to two systems of burst data e ₁ , It is separated into e _2. Each separated burst data e ₁ , e of the two systems
₂ in the next differential encoding circuit 18b
Differential encoding is performed based on a differential encoding rule specified by DC, JDCT, ADC, or the like. In addition, actually, the above-mentioned J
Since DC, JDCT, and ADC adopt the same differential encoding rule, differential encoding is performed based on one type of differential encoding rule.

Each of the differentially encoded burst data e ₁ ,
e ₂ is input to the next Nyquist / root Nyquist filter circuit 18c. In the Nyquist / root Nyquist filter circuit 18c, an FIR filter having a sufficient tap length is incorporated therein in order to achieve high modulation accuracy and reduction of adjacent channel leakage power. And 0.
Each filter having four types of roll-off rates α from 35 to 0.50 can be used. Each of the burst data e ₁ and e ₂ that have passed through this digital filter is converted to baseband data I and Q by an I / Q data generator 18.
Output from

Each of the baseband data I and Q output from the I / Q data generator 18 is transmitted to the next envelope adding unit 1.
9 is input. As shown in FIG. 2, the envelope adding section 19 includes a pair of amplitude control memories 19a, 19b and 1
And up / down counters 19c.

Each of the amplitude control memories 19a and 19b has the same configuration, and the input baseband data I and Q having a 12-bit configuration are applied to their lower addresses. The upper address of each of the amplitude control memories 19a and 19b includes a count value CN of the up / down counter 19c.
Is applied.

The up / down counter 19c has a delay gate signal m which is at a high (H) level for a period shorter than the duration T _S of the burst data e by a 4-bit output time corresponding to the final transient response ramp time R. When the clock signal a rises, the count-up operation of the clock of the clock signal a is started, and when the count operation of a predetermined specified number of bits (clock number) such as 4 bits is completed, the count value CN is maintained. When the delay gate signal m falls four bits before the end of the duration T _S of the burst data e,
The countdown operation of the count value is started. When the duration T _S of the burst data e ends, the counting operation is stopped.

That is, the up / down counter 19c
Is 0 before the duration T _S of the burst data e is started (CN = 0), and increases sequentially when the duration T _S is started, and is increased by 4 bits. Thereafter, a constant value is maintained (CN = CN _S ), and the duration T
4 bits before the end of _S gradually decrease.

[C] of each of the amplitude control memories 19a and 19b
For example, an amplitude data value represented by, for example, 12 bits is set in the address indicated by [N1], and an amplitude data value of 0 is set in the address indicated by [CN0]. When the address value of [CN1] increases, the amplitude data value stored at the corresponding address also increases.

Therefore, each baseband data I and Q quantized by 12 bits is stored in each amplitude control memory 19.
a, 19b each time [CN]
1] or 12 bits of amplitude data stored at the address specified by [CN0]. Therefore.
Baseband data I _D of 12 bit configuration having an envelope characteristics (amplitude characteristics) as shown in FIG. 5, Q _D is output from the envelope adding section 19.

The 12-bit amplitude data constituting the baseband data I _D , Q _D output from the envelope adding section 19 is converted into analog amplitude data by the D / A converters 20a, 20b. Therefore, each D / A
The baseband signals I (t) and Q (t) output from the converters 20a and 20b have amplitude characteristics shown in FIG. The baseband signals I (t) and Q (t) are input to the quadrature modulator 21.

The quadrature modulator 21 is configured, for example, as shown in FIG. The intermediate frequency signal having the frequency f _I output from the intermediate frequency oscillator 21c is applied to the modulator 21a
Is modulated by one baseband signal I (t). The intermediate frequency signal output from the intermediate frequency oscillator 21c is phase-shifted by π / 4 by the 90 ° phase shifter 21d, and then modulated by the other baseband signal Q (t) in the modulator 21b. Each modulator 21
Each of the phase modulated signals output from a and 21b is signal-synthesized by a signal synthesizer 21e and output as a QPSK signal (quadrature modulated signal) h.

The QPSK signal h output from the quadrature modulator 21 is converted to a high frequency by a frequency conversion circuit 22 comprising a mixer circuit 22a and a local oscillator 22b for outputting a carrier frequency signal having a frequency f _C.
The QPSK signal i frequency-converted from the intermediate frequency f _I to the high-frequency carrier frequency f _C is transmitted to the next high-frequency switch circuit 23.
Is input to

The high-frequency switch circuit 23 conducts the circuit only during the period _TG when the extension gate signal j input from the extension gate signal generation circuit 14 is at the high (H) level, and during the period when the extension gate signal j is at the low (L) level. Open circuit.

As shown in FIG. 4, the extension gate signal generation circuit 14 comprises a falling position counter 14a and an RS flip-flop 14b. The RS flip-flop 14b is set at the rising edge of the delay gate signal m output from the gate delay circuit 24. as a result,
The extension gate signal j output from the Q terminal of the flip-flop 14b rises.

When the delay gate signal m falls, the falling position counter 14a starts clocking by the clock signal a. When the measurement of the predetermined time of 4 bits is completed, a time-up signal is output. The flip-flop 14b is reset by this time-up signal. As a result, the extension gate signal j output from the Q terminal of the flip-flop 14b falls.

As shown in FIG. 7, the delay gate signal m is
The QPSK signal i rises at the same time as the rising start time,
The signal falls four bits before the falling end time of the PSK signal i. Therefore, the extension gate period _TG of the extension gate signal j output from the extension gate signal generation circuit 14 is a period obtained by extending the gate period of the delay gate signal m by four bits backward, and the burst of the high-frequency QPSK signal i is continued. It is equal to the period T _S.

Therefore, the burst signal k output from the burst signal generator is output from the frequency conversion circuit 23 during the extended gate period _{TG due to} the presence of the high frequency switch circuit 23 as shown in FIG. Q
The signal becomes the PSK signal i, and the signal level during the period other than the extension gate period _TG becomes substantially zero.

Next, the features of the burst signal generator configured as described above will be described.

As shown in the time chart of FIG. 7 and the amplitude characteristics of the baseband data I _D and Q _D of FIG. 5, the burst data e of the binarized display stored in one time slot 1 is, for example, 12 bits. After conversion into a pair of baseband data I and Q having a configuration, only the amplitude data at the front end and the rear end are sequentially increased and decreased.

[0047] Thus, the baseband data I _D having such envelope characteristics, the signal waveform of the burst signal k obtained from Q _D, as shown in FIG. 7, the rising smoothly, smoothly falls.

The high-frequency switch circuit 23 controls on / off of the QPSK signal i by an extension gate signal j having a pulse width _TG matching the burst duration T _S. Therefore, the rising portion or the falling portion of the burst signal k is not interrupted by the presence of the high-frequency switch circuit 23.

FIG. 6 is a frequency characteristic diagram of the burst signal k output from the burst signal generator. As shown, by adopting the enveloping and extended gate time T _G, it can be greatly reduced as compared with the frequency bandwidth W _B of a conventional burst signal 3 indicating the frequency bandwidth W in FIG. 10 (d) . Therefore, leakage power to adjacent channels can be significantly reduced. According to the experiment of the inventor, a value substantially equal to the leakage power in the continuous signal 4 shown in FIG. 10A could be obtained.

By inserting the high-frequency switch circuit 23, the on / off ratio between the on-period and the off-period of the burst signal k becomes 80 dB or more. As a result, it is possible to greatly improve the S / N when the fixed station receives each burst signal k.

[0051]

As described above, according to the burst signal generator of the present invention, the envelope for gradually increasing and decreasing the amplitude data of each bit data at the leading end and the trailing end of the burst data output from the burst data generating unit. Processing is being performed. Further, the conduction time of the high-frequency switch circuit inserted in the output stage is set equal to the duration of the burst data. Therefore, the frequency occupied bandwidth of the burst signal can be greatly reduced while the on / off ratio of the output burst signal is maintained at a high value, and the leakage power to the adjacent channel can be suppressed as much as possible.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of a burst signal generator according to one embodiment of the present invention;

FIG. 2 is a block diagram showing a schematic configuration of an I / Q data generating unit and an envelope adding unit of the device of the embodiment;

FIG. 3 is a block diagram showing a schematic configuration of a quadrature modulator of the device of the embodiment.

FIG. 4 is an extended gate signal generation circuit diagram of the device of the embodiment;

FIG. 5 is an amplitude characteristic diagram of baseband data in the device of the embodiment;

FIG. 6 is a diagram showing a frequency characteristic of a burst signal of the device of the embodiment;

FIG. 7 is a time chart showing the operation of the apparatus of the embodiment;

FIG. 8 is a diagram showing a relationship between a transmission frame and each time slot in general TDMA communication;

FIG. 9 is a time chart showing a relationship between conventional burst data and a burst signal;

FIG. 10 is a diagram showing a comparison between a continuous signal and a burst signal and each frequency characteristic of each signal.

[Explanation of symbols]

1: time slot, 11: clock signal generation circuit, 1
2 continuous data generation unit, 13 burst data generation circuit, 14 extended gate signal generation circuit, 15 burst start signal generation circuit, 16, 17 switching circuit, 18 I / Q
Data generator, 19 ... Envelope adder, 20a, 2
0b: D / A converter, 21: quadrature modulator, 22: frequency conversion circuit, 23: high-frequency switch circuit, 24: gate delay circuit.

Claims (1)

(57) [Claims] 1. In response to a burst start signal input indicating the start of a pre-assigned time slot (1) in a transmission frame repeated at a fixed period, burst data to be stored in the time slot is output; A burst data generator (13) for generating an I / Q gate signal, and an I / Q data generator for converting the burst data output from the burst data generator into a pair of baseband data
(18) and an envelope adding unit (1) for gradually increasing and decreasing the amplitude data of a predetermined number of bits at the leading end and the trailing end of each baseband data output from the I / Q data generating unit.
9) a D / A converter (20a, 20b) for converting each baseband data to which an envelope has been added by the envelope adding section into each analog baseband signal;
A quadrature modulator (21) for orthogonally modulating each baseband signal output from the converter, and a frequency conversion circuit (22) for amplitude-modulating the quadrature modulated signal output from the quadrature modulator with a high-frequency carrier frequency signal. , The I / Q gate signal to the I / Q
A gate delay circuit (24) for delaying by a signal delay in the Q data generator, and an extended gate signal generating circuit for generating an extended gate signal obtained by extending the delayed gate signal output from the gate delay circuit backward by a predetermined number of bits (14),
A high-frequency switch circuit (23) that passes a high-frequency orthogonal modulation signal output from the frequency conversion circuit only during the extended gate signal application period and outputs the burst signal.