JP2960465B2 - Device simulation method for semiconductor device - Google Patents

Device simulation method for semiconductor device

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Publication number
JP2960465B2
JP2960465B2 JP6094890A JP6094890A JP2960465B2 JP 2960465 B2 JP2960465 B2 JP 2960465B2 JP 6094890 A JP6094890 A JP 6094890A JP 6094890 A JP6094890 A JP 6094890A JP 2960465 B2 JP2960465 B2 JP 2960465B2
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JP
Japan
Prior art keywords
difference
insulating film
electric field
average depth
quantum
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP6094890A
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Japanese (ja)
Other versions
JPH03263851A (en
Inventor
康幸 大倉
仁司 松尾
弘造 片山
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Hitachi Ltd
Original Assignee
Hitachi Ltd
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Publication of JPH03263851A publication Critical patent/JPH03263851A/en
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Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体素子の特性を数値計算によりシミユ
レーシヨンする方法及びそれを用いたシユレーシヨンシ
ステムにより、半導体素子の特性を予測する技術に関す
る。
Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for simulating the characteristics of a semiconductor device by numerical calculation and a technique for predicting the characteristics of a semiconductor device by a simulation system using the method.

〔従来の技術〕[Conventional technology]

従来の方法については、ジヤーナル オブ アプライ
ド フイジツクス 59(1986年)第3175頁から第3183頁
(J.Appl.Phys.59 pp3175−3183(1986年))において
論じられている。上記論文は、1次元(MOS深さ方向)
のポテンシヤルと波動関数を連立して解いたものであ
る。現状では1次元方向での量子的計算結果と古典的計
算結果の比較に留まつている。
Conventional methods are discussed in Journal of Applied Physics 59 (1986) pp. 3175 to 3183 (J. Appl. Phys. 59 pp. 3175-3183 (1986)). The above paper is one-dimensional (MOS depth direction)
Is a simultaneous solution of the potential and the wave function. At present, it is limited to the comparison between the one-dimensional quantum calculation result and the classical calculation result.

〔発明が解決しようとする課題〕[Problems to be solved by the invention]

電界によつて半導体−絶縁膜界面にキヤリアを誘起さ
せるMIS型半導体素子ではキヤリアが界面付近に局在す
るためフエルミ,デラツク統計に従つた量子力学的挙動
を示す。素子特性を数値計算により予測するためには、
前記挙動を正確に扱うために粒子の密度分布を波動方程
式とポアソン方程式を連立させて解く(量子的方法と呼
ぶ)必要があるが、計算量が膨大であるという問題点が
あつた。そのため、従来は量子力学的挙動を無視し、キ
ヤリアの運動を古典的な流体として扱う(古典的方法と
呼ぶ)デバイスシミユレータが多く用いられてきた。し
かしながら、基板の不純物濃度が高くなると(1017/cm3
以上)反転層内のキヤリア密度に対する量子力学的挙動
が無視できなくなり、素子特性を正確に予測出来ないと
いう問題点があつた。すなわち、反転層内のキヤリア密
度のゲート電圧依存性を示した第3図に示したように、
不純物濃度NAが高くなると2つの計算方法で古典的方法
(CL)と量子的方法(QM)の差が目立ち古典的方法では
実験値からずれてしまうという問題点がある。
In an MIS type semiconductor device in which a carrier is induced at a semiconductor-insulating film interface by an electric field, the carrier is localized near the interface, and thus exhibits a quantum mechanical behavior according to Fermi-Delack statistics. In order to predict the element characteristics by numerical calculation,
In order to accurately handle the above behavior, it is necessary to solve the particle density distribution by simultaneously combining the wave equation and the Poisson equation (referred to as a quantum method), but there is a problem that the amount of calculation is enormous. Therefore, conventionally, a device simulator that ignores the quantum mechanical behavior and treats the motion of the carrier as a classical fluid (referred to as a classical method) has been widely used. However, when the impurity concentration of the substrate is increased (10 17 / cm 3
Above) There is a problem that the quantum mechanical behavior with respect to the carrier density in the inversion layer cannot be ignored and the device characteristics cannot be accurately predicted. That is, as shown in FIG. 3 showing the gate voltage dependency of the carrier density in the inversion layer,
The impurity concentration N A is high comes to classical methods conspicuous difference classical methods (CL) and quantum method (QM) in two calculation methods is a problem that deviates from the experimental values.

本発明の目的は、上記の問題点を解決するため古典的
計算と同程度の計算時間で量子的計算と同様な結果を得
る方法を提供することにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a method for solving the above-described problem, which can obtain a result similar to that of the quantum calculation in a calculation time approximately equal to that of the classical calculation.

〔課題を解決するための手段〕[Means for solving the problem]

上記目的を達成するために量子的方法と古典的方法の
結果の違いは反転層の深さ方向のキヤリア密度分布のず
れとして考えることにより酸化膜厚、フラツトバンド電
圧にキヤリア密度分布のずれに比例した量を足し込んで
古典的計算をおこなう。第5図には、反転層電荷密度の
平均深さの差を示す。横軸は反転層の感じる平均的なゲ
ート電界でゲート実効電界と呼ぶ。電界の範囲(105〜1
06V/cm)は、このゲートと界面に0.6Vから6V印加されて
いることに相当する。閾値電圧の電界は基板濃度4×10
16/cm3以上の領域で105V/cm以上である。また、通常の
デバイスが酸化膜厚20nmでゲート電圧5V以下で動作して
いる。一方105V/cm以下では電界が弱いため量子準位の
間隔が狭くなり、また反転層の平均深さが大きくなるた
め2つの計算結果の差が小さくなり量子効果が重要でな
くなる。そして106V/cm以上の電界では強電界のため酸
化膜中のホツトキヤリアが問題となるため通常のデバイ
ス動作として使われることは少ない。第5図を見ると反
転層電荷密度の平均深さの差は実用的な電界領域で約1.
6nmから1.0nmまで電界に対してなだらかな減少関数にな
つている。また基板濃度依存性も少ない。そこで平均深
さの差を一定値(約1.2nm)と仮定するかあるいは電界
及び基板濃度の関数とて表現する。そしてその平均深さ
の差に誘電率の比を掛けた長さを絶縁膜の厚さに加え、
フラツトバンド電圧にも平均深さの差に定数を掛けた電
圧を加えて入力データとする。この方法により従来の古
典的計算と同程度の計算時間で量子的計算と同惨な結果
を得ることが出来る。
The difference between the results of the quantum method and the classical method to achieve the above objective was considered as the shift of the carrier density distribution in the depth direction of the inversion layer, and was proportional to the shift of the carrier density distribution in the oxide film thickness and flat band voltage Perform the classical calculation by adding the quantities. FIG. 5 shows the difference in the average depth of the inversion layer charge density. The horizontal axis is the average gate electric field felt by the inversion layer and is called the gate effective electric field. Range of electric field (10 5-1
0 6 V / cm) is equivalent to being 6V applied from 0.6V to the gate and the interface. Electric field of threshold voltage is substrate concentration 4 × 10
It is 10 5 V / cm or more in a region of 16 / cm 3 or more. Further, a normal device operates at a gate voltage of 5 V or less with an oxide film thickness of 20 nm. On the other hand, at 10 5 V / cm or less, the electric field is weak, so that the interval between quantum levels becomes narrow, and the average depth of the inversion layer becomes large. In an electric field of 10 6 V / cm or more, a hot electric field in an oxide film causes a problem due to a strong electric field, so that it is rarely used as a normal device operation. Referring to FIG. 5, the difference in average depth of the inversion layer charge density is about 1.
From 6 nm to 1.0 nm, it has a gentle decreasing function with respect to the electric field. Also, there is little substrate concentration dependency. Therefore, the difference in the average depth is assumed to be a constant value (about 1.2 nm) or expressed as a function of the electric field and the substrate concentration. Then, add the length obtained by multiplying the difference in the average depth by the ratio of the dielectric constant to the thickness of the insulating film,
The flat band voltage is added to a voltage obtained by multiplying the average depth difference by a constant to obtain input data. With this method, it is possible to obtain a result that is as disastrous as the quantum calculation in the same calculation time as the conventional classical calculation.

〔作用〕[Action]

古典的方法と同程度の計算時間で量子的方法と同様な
答えを得る方法であるため、デバイスの設計の高速化高
精度化に大きな寄与を与える。
Since this method obtains an answer similar to that of the quantum method in the same calculation time as that of the classical method, it greatly contributes to high-speed and high-precision device design.

〔実施例〕〔Example〕

以下、本発明の詳細を以下の実施例によつて説明す
る。
Hereinafter, the present invention will be described in detail with reference to the following examples.

第1図は本発明の一実施例であるデバイス特性の設計
支援システムのフローチヤートを示す。まず実デバイス
から測定装置1(容量測定装置)から容量値等の測定デ
ータを得て、素子プロフアイル算出手段2により数値解
析的に、素子プロフアイルを得る。素子プロフアイルは
素子プロフアイル記憶手段3に保存しておき必要な時に
入力データ読み取り手段5に読み取らせることが出来
る。他に必要な補足データは素子構造入力手段4で入力
出来る。また人工的なプロフアイルあるいはプロセスシ
ミユレータの結果やSIMS等の分析結果を素子構造入力手
段4でユーザが入力出来る。5で読み取られたデータ
を、量子効果取り込みのためのデータ抽出手段6に転送
し、酸化膜厚、フラツトバンド電圧,バイアス条件,不
純物分布を選び出す。5では上記を含めた多くのデータ
が格納されており、6では本発明のために必要なデータ
が指定されており5のデータから選びだす。繰り込みパ
ラメータテーブル7を参照し、酸化膜厚,フラツトバン
ド電圧繰り込み手段8において、酸化膜厚,フラツトバ
ンド電圧に繰り込みパラメータを繰り込む。繰り込みパ
ラメータテーブル7は1次元的な量子的計算と古典的計
算との間の反転層の平均深さの差をバイアス条件,不純
物分布の関数としてテーブル化されており、これを読み
取ることにより繰り込みを行う。
FIG. 1 is a flowchart of a device characteristic design support system according to an embodiment of the present invention. First, measurement data such as a capacitance value is obtained from a measuring device 1 (capacitance measuring device) from an actual device, and an element profile is numerically analyzed by an element profile calculating means 2 to obtain an element profile. The element profile can be stored in the element profile storage means 3 and read by the input data reading means 5 when necessary. Other necessary supplementary data can be input by the element structure input means 4. Further, the user can input the result of the artificial profile or process simulator or the analysis result such as SIMS by the element structure input means 4. The data read in step 5 is transferred to data extracting means 6 for taking in the quantum effect, and the oxide film thickness, flat band voltage, bias condition, and impurity distribution are selected. In 5, a lot of data including the above is stored. In 6, data necessary for the present invention is specified, and data is selected from the 5 data. Referring to the renormalization parameter table 7, the renormalization parameters are recalculated in the oxide film thickness and the flat band voltage by the oxide film thickness and flat band voltage rewriting means 8. The renormalization parameter table 7 is a table in which the difference in the average depth of the inversion layer between one-dimensional quantum calculation and classical calculation is tabled as a function of the bias condition and the impurity distribution. Do.

ここで用いる反転層の平均深さは1次元的計算による
もので計算量は十分少なく2−3次元でのデバイスを解
析する場合計算時間の大きな節約となる。
The average depth of the inversion layer used here is based on one-dimensional calculation, the amount of calculation is sufficiently small, and when analyzing a device in 2-3 dimensions, the calculation time is greatly saved.

この結果である修正された酸化膜厚とフラツトバンド
電圧を用いて、電流電圧特性解析手段9で解析し、解析
結果出力手段10で出力する。本実施例によれキヤリアの
挙動を体として取扱いながら量子的計算と同様な結果を
得る高速なデバイス特性の設計支援システムを得ること
が出来る。
Using the corrected oxide film thickness and the flat band voltage, which are the results, the current-voltage characteristic analyzing means 9 analyzes the result, and outputs the result by the analysis result output means 10. According to the present embodiment, it is possible to obtain a high-speed device characteristic design support system that can obtain the same result as the quantum calculation while treating the behavior of the carrier as a body.

繰り込みは具体的には、酸化膜厚には反転層の平均深
さの差に半導体と酸化膜の誘電率の比を掛けたものを足
し、フラツトバンド電圧も反転層の平均深さの差に応じ
てテーブルに従つて変化させるものである。すなわち、
第2図に示したように反転層は実際には量子的計算によ
る解のように表面付近で0に近づいているものを表面で
最も大きくなる古典的計算による解の形に近似する。同
時に反転層の総量が変わらないように半導体と酸化膜の
界面をずらしてやる。その場合誘電率の違いからポテン
シヤルのずれが生じるのでずらした界面に比例した量だ
けフラツトバンド電圧を変える。
Specifically, the renormalization is obtained by adding the difference between the average depth of the inversion layer to the oxide film thickness multiplied by the ratio of the dielectric constant between the semiconductor and the oxide film, and the flat band voltage also depends on the difference in the average depth of the inversion layer. In accordance with the table. That is,
As shown in FIG. 2, the inversion layer approximates a solution approaching zero near the surface, such as a solution based on a quantum calculation, to a form of a solution based on a classical calculation which is the largest on the surface. At the same time, the interface between the semiconductor and the oxide film is shifted so that the total amount of the inversion layer does not change. In this case, a potential shift occurs due to a difference in dielectric constant, so the flat band voltage is changed by an amount proportional to the shifted interface.

〔発明の効果〕〔The invention's effect〕

本発明によりデバイススミユレーシヨンに量子効果が
繰り込まれるので精度が飛躍的に上昇する。第4図に反
転層電荷密度を量子力学的に計算したもの(QM),古典
的に計算したもの(CL),本発明により酸化膜厚,フラ
ツトバンド電圧を修正したもの(MD)及び実験値の比較
結果を示す。本発明は量子力学的に計算したもの及び実
験値とよく一致する。
According to the present invention, the quantum effect is incorporated into the device simulation, so that the accuracy is dramatically increased. Fig. 4 shows the results of quantum mechanical calculation (QM), the classical calculation (CL), the oxide film thickness and the flat band voltage corrected by the present invention (MD), and the experimental values. The comparison result is shown. The present invention agrees well with quantum mechanically calculated and experimental values.

【図面の簡単な説明】[Brief description of the drawings]

第1図は本発明の一実施例に係わるフローチヤート。第
2図は一実施例に係わる量子解を古典解に繰り込む方
法。第3図は反転層密度のゲート電圧依存性の古典的方
法と量子的方法での比較。第4図に反転層電荷密度を量
子力学的に計算したもの(QM),古典的に計算したもの
(CL),本発明により酸化膜厚,フラツトバンド電圧を
修正したもの(MD)及び実験値の比較結果を示す。第5
図は反転層の平均深さのゲート電圧依存性の一例。量子
的方法と古典的方法の平均深さの差を縦軸に示した。
FIG. 1 is a flow chart according to one embodiment of the present invention. FIG. 2 shows a method of incorporating a quantum solution according to one embodiment into a classical solution. FIG. 3 shows a comparison of the dependence of the inversion layer density on the gate voltage between the classical method and the quantum method. Fig. 4 shows the results of quantum mechanical calculation (QM), the classical calculation (CL), the oxide film thickness and the flat band voltage corrected by the present invention (MD), and the experimental values. The comparison result is shown. Fifth
The figure shows an example of the gate voltage dependence of the average depth of the inversion layer. The difference between the average depth of the quantum method and the classical method is shown on the vertical axis.

Claims (3)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】半導体と絶縁膜との界面に電荷が局在する
ため量子力学的挙動を示すMIS型半導体素子の電流電圧
特性を解析するデバイスシミュレーション方法であっ
て、 前記界面における反転層電荷密度の平均深さに関する量
子的計算結果と古典的計算結果との差に対応した値を前
記絶縁膜の厚さ及びフラットバンド電圧に加えることを
特徴とする半導体素子のデバイスシミュレーション方
法。
1. A device simulation method for analyzing current-voltage characteristics of an MIS type semiconductor device exhibiting quantum mechanical behavior due to localization of charges at an interface between a semiconductor and an insulating film, comprising: an inversion layer charge density at the interface. Adding a value corresponding to a difference between a quantum calculation result and a classical calculation result regarding the average depth of the insulating film to the thickness of the insulating film and the flat band voltage.
【請求項2】前記加える処理は、前記平均深さの差と前
記半導体及び絶縁膜それぞれの誘電率の比との積を前記
絶縁膜の厚さに加える処理と、前記平均深さの差と該深
さ方向の電界の強さを表す定数との積を前記フラットバ
ンド電圧に加える処理とからなる請求項1記載の半導体
素子のデバイスシミュレーション方法。
2. The method according to claim 1, further comprising: adding a product of a difference between the average depth and a ratio of a dielectric constant between the semiconductor and the insulating film to a thickness of the insulating film. 2. The device simulation method for a semiconductor device according to claim 1, further comprising a step of adding a product of the electric field in the depth direction and a constant representing the intensity of the electric field in the depth direction to the flat band voltage.
【請求項3】前記平均深さの差と該深さ方向の電界の強
さを表す定数との積は、該平均深さの差をバイアス条件
と不純物分布の関数としてテーブル化されている請求項
2記載の半導体素子のデバイスシミュレーション方法。
3. The product of the average depth difference and a constant representing the electric field strength in the depth direction is tabulated as a function of the average depth difference as a function of bias conditions and impurity distribution. Item 3. A device simulation method for a semiconductor device according to Item 2.
JP6094890A 1990-03-14 1990-03-14 Device simulation method for semiconductor device Expired - Fee Related JP2960465B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
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Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6094890A JP2960465B2 (en) 1990-03-14 1990-03-14 Device simulation method for semiconductor device

Publications (2)

Publication Number Publication Date
JPH03263851A JPH03263851A (en) 1991-11-25
JP2960465B2 true JP2960465B2 (en) 1999-10-06

Family

ID=13157126

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
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Also Published As

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