JP2957870B2 - Video tape recorder - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video tape recorder, and more particularly to, for example, first and second switches which are shifted by a length L in a longitudinal direction with respect to a preceding track by a helical scan system and for each track. The same track of the video tape on which the track pattern is formed at the azimuth angle is formed by opposing the first head at the first azimuth angle and the second head at the second azimuth angle, and the third head and the first azimuth angle at the second azimuth angle Is traced N times at a speed V by any one of the first to fourth heads of the cylinders disposed in the vicinity of the first and second heads. To play a video tape recorder.

[0002]

2. Description of the Related Art An example of this kind of video tape recorder is disclosed in Japanese Patent Application No. 5-589 filed on Mar. 18, 1993.
No. 59 (G11B 5/91). This technique uses a delay circuit to correct the periodic fluctuation of the vertical synchronizing signal caused by a small interval existing between adjacent heads of a double azimuth four-head cylinder, thereby causing vertical play of a reproduced screen. It is to try to prevent.

[0003]

However, even such a conventional video tape recorder is shown in FIGS. 8B, 8C and 8D or FIGS. 8E, 8F and 8A. When the head traces a track having the same azimuth as described above, the traced position is slightly shifted with respect to the longitudinal direction, so that the period of the reproduced vertical synchronization signal is not constant, and the vertical direction of the image reproduced on the screen is It is not possible to completely eliminate the rattling that occurs.

[0004] Therefore, a main object of the present invention is to provide a video tape recorder in which the reproduced image on the screen does not rattle in the vertical direction.

[0005]

According to the present invention, a track pattern is shifted by a predetermined length in a longitudinal direction with respect to a preceding track by a helical scan system and at a first and second azimuth angles which are switched for each track. In the same track of the formed video tape, the first head having the first azimuth angle and the second head having the second azimuth angle are arranged to face each other, and the third head having the second azimuth angle and the fourth head having the first azimuth angle face each other. Then, by being traced N times at a predetermined speed by any of the first to fourth heads of the cylinder arranged near the first and second heads, the first
In a video tape recorder for reproducing the Nth video signal, the first to (N-1) th video signals are output after being delayed by a predetermined time determined by a predetermined length and a predetermined speed, and the Nth video signal is left as it is. Characterized in that it is output
It is a video tape recorder.

[0006]

The length L of the preceding track in the longitudinal direction is
If the same track of the track pattern formed so as to be shifted by only the amount shown in FIG. 4 is traced, for example, three times by the video reproducing head tracing the track at the speed V, the video signal reproduced first will be a delay circuit. , And is output with a delay of 2 L / 3 V, the second reproduced video signal is output with a delay of L / 3 V, and
The video signal reproduced first is output without delay.

[0007]

According to the present invention, since the video signal is delayed by the delay means so that the period of the vertical synchronizing signal is constant, it is possible to prevent the image reproduced on the screen from rattling in the vertical direction. Can be prevented. The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description of embodiments with reference to the drawings.

[0008]

Referring to FIG. 1, a video tape recorder 10 of this embodiment includes a head 12 on which cylinders A + and B + having an azimuth angle of + and heads A- and B- having an azimuth angle of-are mounted. Including. The heads A + and A-
Are mounted at an angle of 180 ° to each other, and head A +
The head B- is located at a position further away by the length D, and the head A-
The head B + is mounted at a position further apart by the length D.
By rotating the cylinder 12 in the direction of the arrow,
A video signal is recorded on the tape 14, and a video signal is reproduced from the tape 14.

In recording, a video signal is input to a gate 18 via a recording amplifier 16 as shown in FIG. Further, a vertical synchronizing signal is separated from the video signal by the synchronizing separation circuit 20, and the vertical synchronizing signal is input to the gate control circuit 22 and the drive circuit 24. As a result, the drive circuit 24 rotates the cylinder 12 at a constant speed using the vertical synchronization signal as a reference signal, and the gate control circuit 22 creates a gate control signal based on the vertical synchronization signal. The gate control signal is a signal that is at a high level for one field period every three fields as shown in FIG. 3D, and the gate circuit 18 outputs a video signal only during a period when the gate control signal is at a high level. . Therefore, the gate circuit 1
8 from among the video signals shown in FIG.
And V7 are output. These video signals are recorded on the tape 14 by the heads A + and A- according to the switching timing shown in FIG.

As described above, by controlling the output of the video signal to be recorded, the video signal is recorded on the tape 14 as shown in FIG. That is, the track pattern T1 of the video signal V1 is formed, and then the track pattern T4 of the video signal V4 is formed adjacent to the track T1 without forming the track patterns T2 and T3 of the video signals V2 and V3. . Thereafter, a track pattern is formed such that two tracks are skipped every time one track is formed, such as video tracks T7, T10, and T13. Note that the azimuth angles of the formed track patterns are alternately switched as can be seen from the switching timing shown in FIG. Also, tape 1
4 is set to 1/3 of the EP mode, and the deviation L from the adjacent track in the longitudinal direction of the track is 0.5.
H. Then, the track pattern coordinate diagram becomes a pattern as shown in FIG. In the figure, the vertical axis represents the tape travel,
Time is plotted on the horizontal axis, and + and-symbols indicate patterns recorded with the + azimuth head and the -azimuth head.

The video tape recorder 10 further includes a control head 26, by which a control signal CTL shown in FIG. 6A is recorded. The control signal CTL is a rectangular wave that rises when a video signal is recorded on the tape 14 by the head A +. When a video track is formed once every three times as in this embodiment, the period is 1/10. Seconds.

At the time of reproduction, the tape 14 runs at the same speed as that at the time of recording, and the video signals of the video signal and the control signal CTL recorded on the tape 14 are the heads A- and B.
Reproduced by +, A + and B-. Then, the respective video signals are amplified by the reproduction amplifiers 28a, 28b, 28c and 28d. The amplified video signal is input to the video signal processing circuit 34 via the switch circuits 30 and 32, and after being subjected to predetermined processing by the circuit 34, is output. When the switch circuit 36 is connected to the terminal 36a, the output video signal is output to the 2H delay circuit 3
After passing through the switch circuit 36 after the delay processing at 8,
When the switch circuit 36 is connected to the terminal 36b, the signal passes through the switch circuit 36 without any processing. Thereafter, when switch circuit 40 is connected to terminal 40a, the video signal is delayed and output by 0.167H delay circuits 42 and 44, and switch phase comparators 40 and 46 are connected to terminals 40b and 46a. when,
The signal is output through the delay circuit 44. When switch circuits 40 and 46 are connected to terminals 40b and 46b,
Output without any processing.

The control signal CTL recorded on the tape 14 is detected by the control head 26 and the control signal detection circuit 48, and is input to the control signal generation circuit 50 as a differential signal as shown in FIG. Then, in the control signal creation circuit 50,
A control signal CTL is generated as shown in FIG. 7A, which rises in synchronization with the rise of the differential signal and falls in synchronization with the fall of the differential signal. The control signal CTL is input to the monomulti 52a, and a pulse that rises during the period T1 is output from the monomulti 52a as shown in FIG. 7B.

Further, a PG detecting circuit 56 based on an output of a PG detecting coil 54 for detecting a rotation state of the cylinder 12 is provided.
Outputs a PG signal. The PG detection coil 54
When the head A + traces the video track at the position shown in FIG. 8A described later (the head A + traces also at the position shown in FIGS. 8C and 8E), the PG detection circuit 5
6 is arranged to output a PG signal. The PG signal is then input to a switching pulse generation circuit 58, which generates a switching pulse (FIG. 7C) with a duty of 50% with one rotation time of the cylinder 12 as one cycle in synchronization with the rising edge of the PG signal. Is done. This switching pulse is input to the switch circuit 30, the mono-multi 52b, and the doubling circuit 46.

From the mono-multi 52b, a pulse as shown in FIG. 7 (D) which becomes high level only for a period T2 in synchronization with the rise of the switching pulse is output. This pulse is AND-processed with the output pulse of the mono-multi 52a by the AND circuit 60, and the output of the AND circuit 60 (FIG. 7)
(E)) is input to the counters 64a and 64b as a reset pulse. A pulse in which the cycle of the switching pulse is halved is output from the doubling circuit 62, and is input to the counters 64a and 64b as a clock.
Therefore, the counters 64a and 64b are incremented in synchronization with the rising edge and the falling edge of the switching pulse, and reset by the reset pulse. In the switch circuit 30, when the switching pulse goes high, the switch 30
a and 30b are connected to terminals 30d and 30f, respectively, and switches 30a and 30b are connected to terminals 30c and 30e, respectively, when the switching pulse goes low.

The control circuit 66a takes in the count value of the counter 64a, and when the count value is 0, that is, when the reset pulse rises, as shown in FIG. When the value becomes 1, the level is set to the high level. Thereafter, the high level is maintained. When the count value becomes 3, the level is set to the low level, and when the count value becomes 4, the level is set to the high level again. After that, the high level is maintained until the count value becomes 0 by the reset pulse. When the count value becomes 0, the same operation is repeated. The switch circuits 32 and 36 are controlled by this control signal. That is, when the control signal is at the low level, the switch 3
2 and 36 are connected to terminals 32a and 36a, and switches 32 and 36 are connected to terminals 32b and 36b when the control signal is at a high level. As a result, the video signal reproduced by the head shown in FIG. 7G is input to the video signal processing circuit 34, and the vertical synchronizing signal becomes as shown in FIG. 7H when the control signal (F) is at a low level. Delayed by 2H as shown.

The control circuit 66b takes in the count value of the counter 64b and outputs control signals shown in FIGS. 7 (I) and (J). Here, the control signal (I) is a signal which becomes high level when the count value is 2 and 5, and becomes a low level otherwise. The control signal (J) is a low level signal when the count value is 1 and 4. The signal becomes a high level at other times. The switch circuit 40 is controlled by the control signal (I), and the switch circuit 46 is controlled by the control signal (J). That is, when control signals (I) and (J) are at high level, switch circuits 40 and 46 are connected to terminals 40a and 46a, respectively, and when control signals (I) and (J) are at low level, switch circuits 40 and 46 are connected. Are connected to terminals 40b and 46b, respectively.

In operation, when the heads A + and B- trace the track as shown in FIG. 8A, after the video signal reproduced by the head A + is processed by the video signal processing circuit 34, no delay processing is performed. Is output. Next, when the heads A- and B + trace the track as shown in FIG. 8 (B), the video signal reproduced by the head A- is processed by the video signal processing circuit 34, and then the delay signals 42 and 44 cause the video signals to become 0. The delay processing is performed by 2/3 of .5H, that is, 0.334H, and the result is output. When the heads A + and B− trace as shown in FIG. 8C, the video signal reproduced by the head B− is processed by the video signal processing circuit 34. Thereafter, the delay circuit 38 performs a delay process by 2H, and the delay circuit 44 delays 1 / 0.5H.
3, that is, delayed by 0.167H and output.

When the heads A- and B + trace the track as shown in FIG.
4 receives a video signal reproduced by the head A-. Thereafter, the processed video signal is output without delay processing. When the heads A + and B- trace the track as shown in FIG. 8E, the video signal reproduced by the head A + is input to the video signal processing circuit 34. Then, the processed video signal is delayed by 0.334H by delay circuits 42 and 44 and output. When the heads A− and B + trace the track as shown in FIG. 8F, the video signal processing circuit 34
The reproduced video signal is input and subjected to signal processing. After that, the processed video signal is output by the delay circuit 38 for 2H.
, And further delayed by 0.167H by the delay circuit 44 and output.

According to this embodiment, the adjacent head A +
The fluctuation of the vertical synchronizing signal period caused by the interval D between the heads A and B + and the interval D between the adjacent heads A- and B + is eliminated by the delay circuit 38, and the trace in the longitudinal direction of the track as shown in FIG. Variations in the vertical synchronization signal period caused by the displacement are eliminated by the delay circuits 42 and 44, so that the image reproduced on the screen does not rattle in the vertical direction.

In this embodiment, the delay circuits 38, 42
And 44 are arranged after the video signal processing circuit 34. However, the delay circuits 38, 42 and 44 are all arranged before the video signal processing circuit 34, or are separately arranged before and after the video signal processing circuit 34. Needless to say, the same effect can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a block diagram showing a part of the embodiment in FIG. 1;

FIG. 3A is a waveform diagram showing a video signal, and FIG.
FIG. 4 is a waveform diagram showing a vertical synchronization signal, FIG. 4 (C) is an illustrative view showing switching timing, and FIG. 4 (D) is a waveform diagram showing a gate control signal.

FIG. 4 is an illustrative view showing a part of the embodiment in FIG. 1;

FIG. 5 is an illustrative view showing a part of the embodiment in FIG. 1;

6A is a waveform diagram showing a recorded control signal CTL, and FIG. 6B is a waveform diagram showing a reproduced control signal CTL.

7A is a waveform diagram showing a control signal CTL, FIG. 7B is a waveform diagram showing an output of the mono multi 38a, FIG. 7C is a waveform diagram showing a switching pulse, and FIG. Is a waveform diagram showing an output of the mono-multi 38b, (E) is a waveform diagram showing a reset pulse,
(F) is a waveform diagram showing a control signal, (G) is an illustrative view showing a reproducing head, (H) is a waveform diagram showing a vertical synchronizing signal, and (I) and (J) are control signals. FIG.

FIG. 8 is an illustrative view showing one portion of an operation of the embodiment in FIG. 1;

[Explanation of symbols]

 10 Video tape recorder 26 Control head 28a, 28b, 28c, 28d Reproduction amplifier 30, 32, 36, 40, 46 Switch circuit 38, 42, 44 Delay circuit 52a, 52b Mono-multi 64a, 64b Counter 66a, 66b ... control circuit

Claims (1)

(57) [Claims] 1. A helical scan system which shifts a preceding track by a predetermined length in a longitudinal direction and
The same track of the video tape on which the track pattern is formed at the first and second azimuth angles that are switched for each track is placed on the second azimuth with the first head having the first azimuth angle and the second head having the second azimuth angle. A third head having a first corner and a fourth head having a first azimuth angle are traced N times at a predetermined speed by any one of the first to fourth heads of a cylinder disposed near the first and second heads. A first to (N-1) th video signal, wherein the first to (N-1) th video signals are output after being delayed by a predetermined time determined by the predetermined length and the predetermined speed. A video tape recorder characterized in that the N-th video signal is output as it is.