JP2951186B2 - Data processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to, for example, a CD-ROM
More specifically, the present invention relates to a data processing device such as a drive device. More specifically, storage of input data, processing of the data, and storage of the processed data are performed by a single storage unit. The present invention relates to a data processing apparatus capable of ensuring the maximum storage capacity of processed data while preventing overwriting of data in a storage unit.

[0002]

2. Description of the Related Art FIG. 4 is a block diagram of a CD-ROM drive device, and FIG. 3 is a diagram showing a logical format (mode 1) of CD-ROM data.

[0003] The error correction process of the CD-ROM drive device is performed in units of logical blocks each having 2352 bytes as one block. CD-ROM signal processing unit 5 '
Sends a sync detection signal S to the controller 11 'upon detecting a sync (synchronization) pattern SYN from the input data D. The controller 11 'generally controls the CD-ROM signal processing unit 5' according to the signal S.

To perform error correction, the CD signal processing unit 4
, The input data D input to the CD-ROM signal processing unit 5 'is once written into the error correction RAM 6', and thereafter, the error correction is executed in the CD-ROM signal processing unit 5 '. CD-ROM signal processing unit 5 '
, The process of writing the input data D to the error correction RAM 6 'and the process of error correction are always performed in parallel with a time difference of one block unit.

At this time, the error correction RAM 6 'has
There is always an area in which the input data D is written, an area in error correction, and an area in which error correction has been performed. The error-corrected data is transferred from the error correction RAM 6 'to the storage-only RAM 7 so that the input data D does not overwrite the error-corrected area.

Due to demands for miniaturization and economy, there are also CD-ROM drive devices that do not have the storage-dedicated RAM 7, and in this case, error-corrected RAM 6 'cannot store error-corrected data. . At this time, when the continuity of the input data D is interrupted for some reason or when there are many errors in the input data D, the CD-ROM
The correct sync detection signal S may not be sent from the signal processing unit 5 'to the controller 11', and the controller 11 'may not be able to control normally. At this time, the CD-ROM signal processing unit 5 ′
If the input data D is being written to M6 ', the error-corrected area may be overwritten.
For example, when data is being written to the error correction RAM 6 ′, when the input sync detector 51 is enabled, when the pickup 1 flies due to vibration or the like, the sync pattern SYN is detected at an abnormal position, and the CD-ROM is detected. The ROM signal processing unit 5 'is synchronized. At this time, when the controller 11 'shifts from the sync detection signal waiting process to the data reliability determination process, the error correction RAM 6'
Is not necessarily one block. If the amount of written data is larger than the capacity allocated as the writing area, there is a possibility that the error-corrected area that is being accumulated is overwritten.

Therefore, conventionally, in a CD-ROM drive device which does not have the storage-dedicated RAM 7, even in the case of such an abnormality, the error-corrected data is stored in order to avoid overwriting the area being stored by overwriting. The storage capacity of the input data D is set to be smaller than the capacity that can be actually stored, and a sufficient write area for the input data D is provided (2 to 5 blocks are prepared). He was taking the margin.

[0008]

However, the above-described method of obtaining a margin in time requires a storage area for obtaining the margin and a memory having a large storage capacity.

The present invention has been made in view of such circumstances, and accumulates input data, processes the data, and accumulates the processed data in a single storage unit. It is an object of the present invention to provide a data processing device that can ensure the maximum storage capacity of processed data while preventing overwriting of data in storage means. Thus, the configuration of the RAM (random access memory) in the CD-ROM signal processing unit 5 'can be changed to the error correction RA without providing a separate storage RAM.
In a CD-ROM drive device having a configuration in which error-corrected data can also be stored in the error-correcting RAM using only M6 ', the storage capacity of the error-corrected data in the error-correcting RAM is maximized. CD-
A ROM drive device can be realized.

[0010]

SUMMARY OF THE INVENTION An optical reproducing apparatus according to the present invention is a data reproducing apparatus which stores input data, processes the data, and stores the processed data in a single storage means. In the processing device, a data reading unit that reads the recording data from a recording medium that stores data including a synchronization signal, a storage unit that receives the read data, and stores data after error correction, After taking out the input data from the storage means and performing error correction processing on the data, the data processing means for storing the data after the error correction processing in the storage means, and detecting a synchronization signal from the input data A sync detection means for outputting a first synchronization detection signal, and counting the amount of input data which is synchronized by the first synchronization detection signal and thereafter stored, and Interpolating sync counter means for outputting an interpolation detection signal for outputting a second synchronization detection signal for each event, and receiving the first synchronization detection signal and the second synchronization detection signal, After receiving the signal,
Is stored in the storage means according to the number of times the synchronization detection signal is input.
The number of stored input data is calculated, the input data number
If the specified number is reached, the specified number of input
Newly process data until the data processing means is finished
Control to prohibit storage of input data in storage means
By a data processing device comprising a control unit, by comprising a performed is obtained by solving the above problems. Further, the optical reproducing apparatus of the present invention stores input data,
After performing the processing on the data, in a data processing device that stores the processed data in one storage means, from a recording medium in which data including a synchronization signal is stored,
Data reading means for reading the recorded data, storage means for receiving the read data and storing error-corrected data, extracting the input data from the storage means, and performing error correction processing on the data After performing the above, the data processing means for storing the data after the error correction processing in the storage means, a sync detection means for detecting a synchronization signal from the input data and outputting a first synchronization detection signal, An interpolating sync counter means for counting the amount of input data which is synchronized by the first synchronization detection signal and thereafter accumulating, and outputting an interpolation detection signal for outputting a second synchronization detection signal every predetermined count; When the first synchronization detection signal and the second synchronization detection signal are input and the first synchronization detection signal is received, the second synchronization detection signal is input thereafter.
The number of input data stored in the storage means is determined by the number of times.
Calculation, and when the number of input data reaches a predetermined number,
Processing of a predetermined number of input data input to the
Input data is newly stored in the storage means until the processing is completed.
By the data processing apparatus characterized by comprising a control means for controlling to prohibit the one in which the above-mentioned problems are eliminated.

[0011]

According to the data processing apparatus of the present invention, when the control means receives the first synchronization detection signal from the sync detection means, thereafter, the control means validates the second synchronization detection signal from the interpolation sync counter means. Since it is received as a signal and controls the storage means and the data processing means, it is possible to control while accurately grasping the amount of data written in the storage means.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the data processing apparatus of the present invention will be described.
This will be described below by taking a CD-ROM drive as an example.
The CD-ROM drive device of the present embodiment is a CD-ROM drive device shown in FIG.
The ROM drive device has the same configuration except that the storage RAM 7 is not provided, and the same portions are denoted by the same reference numerals and description thereof will be omitted.

FIG. 1 is a block diagram of the CD-ROM signal processing section 5 of the CD-ROM drive device of the present embodiment.
The CD-ROM signal processing unit 5 performs processing in units of 2352 bytes as one block. The signal that notifies the controller 11 of the delimitation of the one block is the sync detection signal S. The controller 11 controls the CD-ROM every time the sync detection signal S is received.
This is performed for the signal processing unit 5. Sync detection signal S
Is generated when the input sync detector 51 detects the sync pattern SYN from the input data D. The sync detection signal S is input to the controller 11 via the controller I / F53. The sync detection signal S is also input to the interpolation sync counter section 52, whereby the interpolation sync counter section 52 is synchronized with the sync pattern SYN.
A sync detection signal S is generated every time 2 bytes are input,
The signal S is input to the controller 11 via the controller I / F 53. The interpolation sync counter 52 counts the input word clock C,
The number of input data D is detected and a sync detection signal S is output.

The sync detection signal S passed to the controller 11 via the controller I / F 53 includes a signal generated by the input sync detection unit 51 and an interpolation sync counter unit 52.
Are ORed (ORed) of the signals that generate.

The input sync detector 51 and the interpolation sync counter 52 can be individually enabled / disabled by the controller 11.

The error correction section 55 performs an error correction process on the input data D taken out of the error correction RAM 6 via the RAM I / F 54, and outputs the processed data via the RAM I / F 54 for error correction. Output to RAM6. Further, the error correction unit 55 determines the reliability of the input data D, and outputs the determination result to the controller I / O.
Output to the controller 11 via F53.

In the CD-ROM signal processing unit 5, as a method of notifying the controller 11 that the sync pattern SYN has been detected, there are a method of detecting from the input data D and a method of counting the number of input data 9 by 2352. , The controller 11 sends an error correction RA to the CD-ROM signal processing unit 5 having the counting unit.
While the input data D is being written to M6, a control method is performed in which the sync pattern SYN detected from the input data D is invalidated and only the signal by the interpolation sync counter unit 52 is valid.

By doing so, the controller 11
Is always stable (2353) from the CD-ROM signal processing unit 5.
It is possible to receive the sync detection signal S (for each byte) and control while accurately grasping the number of data written in the error correction RAM 6.

FIG. 2 is a flow chart for the sync detection and RAM management by the controller 11.

The CD-ROM signal processing unit 5 converts the input data D
First, the input sync detection unit 51 is enabled (step 1 (S1)), and the process proceeds to a wait for a sync detection signal S (step 2). When the sync pattern SYN is detected by the sync detection unit 51 and the sync detection signal S is input to the controller, the process proceeds to a data reliability determination (step 3) process. If it is determined that the input data is not reliable, the error correction RAM 6
Is stopped (step 8), and the process shifts to the process of permitting the input sync detection unit 51 again (step 1).
If it is determined that the data is reliable, it is determined whether the data is being written to the error correction RAM 6 (step 4).
Move to In this determination process, when it is determined that writing is not being performed, the process proceeds to a process of prohibiting the output of the sync detection signal S of the input sync detection unit 51 (step 5), and the interpolation sync counter unit 52 is enabled in step 5. Then, the write address of the error correction RAM 6 is set, and the writing of the error correction RAM 6 is permitted.

When the prohibition process (step 5) of the input sync detector 51 is performed, the process returns to the sync detection signal waiting process (step 2). After that, the controller 11
Will proceed according to the sync detection signal S generated by the interpolation sync counter unit 52.

If it is determined in the RAM writing process (step 4) that writing is being performed, 1 is added to the counter of the number of blocks stored in the error correction RAM 6 and the next error correction is performed. The controller 11 performs processing (step 6) for holding the address to be written in the RAM 6 for use. Step 6: RA for error correction
Holding the address to be written in M6 is performed after the RAM write stop process (step 8) when it is determined that there is no reliability in the data reliability determination process (step 3), and then the error correction is performed. This is because, when writing to the RAM 6 is restarted, this data is discarded, and writing is started again from the address where the data is written. When it is determined that there is no reliability, the write address of the next error correction RAM 6 is not updated.
When writing to the error correction RAM 6 is started again (step 5), writing is started from the same address.

By doing so, it is possible to pack only reliable data without gaps without accumulating extra data, thereby facilitating the management of the RAM.

When the process of holding the address to be written to the RAM next time (step 6) is completed, the process proceeds to a process of comparing the number of stored blocks with the number of blocks that can be actually stored (step 7). If it is determined in this process that the capacity is full, the process of stopping writing to the error correction RAM 6 (step 8) is performed, and the process returns to the process of permitting the input sync detector (step 1). If there is enough capacity, the process returns to the sync detection signal waiting process (step 2) and repeats this process.

As described above, according to the data processing apparatus of this embodiment, while data is being written into the error correction RAM 6, the data is controlled only by the sync detection signal S generated by the interpolation sync counter 52. From the controller 11 waits for the sync detection signal (step 2).
When the process proceeds to the data reliability determination process (step 3), it can be determined that one block of data (2352 bytes) has always been written. Therefore, if a write area of one block + α is secured as a write area, stable control of the RAM can be performed even if the rest is allotted to the storage area.

Here, + α means that the controller 11
From the sync detection signal waiting process (step 2), when comparing the number of accumulated blocks with the number of blocks that can be actually accumulated (step 7), it is determined that the RAM capacity is full, and the RAM write stop process (step 7). This is the capacity to be written before step 8). If a write area of one block + α is secured as a write area, stable control of the RAM can be performed even if the rest is allocated to the storage area.

The configuration of the CD-ROM signal processing unit 5 is only the error correction RAM 6 and can also store error-corrected data. Further, the writing area can be minimized, and the amount of data that can be stored increases accordingly. This is advantageous in terms of cost and mounting area, and is very effective for a device having a small RAM capacity.

[0028]

As described above, according to the data processing apparatus of the present invention, storage of input data, processing of the data, and storage of the processed data are performed in one storage unit. In the data processing device, a second synchronization detection signal
Input data stored in the storage means according to the number of times
Calculate the number of data, if the input number data reaches a predetermined number
Processing of a predetermined number of input data previously input
Stores new input data until data processing means is completed.
By performing control to prohibit accumulation in a stage, it is possible to provide a data processing device capable of preventing the overwriting of data in the storage unit and maximizing the storage capacity of processed data.

[Brief description of the drawings]

FIG. 1 is a block diagram of a CD-ROM signal processing unit 5 of a CD-ROM drive device.

FIG. 2 is a flowchart of sync detection and RAM management by a controller 11;

FIG. 3 is a diagram showing a logical format (mode 1) of CD-ROM data.

FIG. 4 is a block diagram of a CD-ROM drive device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Optical pick-up (reading means) 2 Rotation drive motor 3 Servo processing part 4 CD signal processing part 5 CD-ROM signal processing part 6 Error correction RAM (storage means) 7 Storage RAM 8 Host interface part 9 CD-ROM disk 11 controller (control means) SYN sync pattern (synchronous signal) 51 input sync detection section (sink detection means) 52 interpolation sync counter section (interpolation sync counter means) 53 controller I / F section 54 RAM I / F section 55 error Correction section (data processing section) D input data S sync detection signal (synchronization detection signal) O output data

Claims (2)

(57) [Claims] 1. A data processing apparatus for accumulating input data, processing the data, and accumulating the processed data in one storage means, wherein the input data is retrieved from the storage means. A data processing unit that performs processing on the input data, stores the processed data in the storage unit, a sync detection unit that detects a synchronization signal from the input data, and outputs a first synchronization detection signal, The input data amount synchronized with the first synchronization detection signal and thereafter stored is counted, and the second data amount is counted every predetermined count.
Interpolating sync counter means for outputting a synchronization detection signal, and receiving the first synchronization detection signal and the first synchronization detection signal, and thereafter receiving the first synchronization detection signal, Is stored in the storage means according to the number of times
Has been to calculate the number of input data, the input data number is predetermined
When the number has been reached, a predetermined number of input data
Input new data until the data processing means is finished
The data processing apparatus is characterized in that anda <br/> control means for controlling to prohibit the storing of data into the storage means. 2. A data processing device for accumulating input data, performing processing on the data, and accumulating the processed data by a single storage means, wherein data including a synchronization signal is stored. Data reading means for reading the recording data from a recording medium; storage means for receiving the read data and storing data after error correction; extracting the input data from the storage means; Data processing means for storing the data after the error correction processing in the storage means after performing the error correction processing, and a sync detection means for detecting a synchronization signal from the input data and outputting a first synchronization detection signal. Counts the amount of input data which is synchronized by the first synchronization detection signal and thereafter accumulated,
An interpolation sync counter unit that outputs an interpolation detection signal that outputs a synchronization detection signal of the following. When the first synchronization detection signal and the second synchronization detection signal are input and the first synchronization detection signal is received, Thereafter, the data is stored in the storage means according to the number of times the second synchronization detection signal is input.
Has been to calculate the number of input data, the input data number is predetermined
When the number has been reached, a predetermined number of input data
Input new data until the data processing means is finished
The data processing apparatus is characterized in that anda <br/> control means for controlling to prohibit the storing of data into the storage means.