JP2944467B2 - Bidirectional relay circuit - Google Patents
Bidirectional relay circuitInfo
- Publication number
- JP2944467B2 JP2944467B2 JP16047495A JP16047495A JP2944467B2 JP 2944467 B2 JP2944467 B2 JP 2944467B2 JP 16047495 A JP16047495 A JP 16047495A JP 16047495 A JP16047495 A JP 16047495A JP 2944467 B2 JP2944467 B2 JP 2944467B2
- Authority
- JP
- Japan
- Prior art keywords
- signal
- voltage
- signal line
- line
- logic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
- Bidirectional Digital Transmission (AREA)
- Dc Digital Transmission (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は双方向中継回路に関し、
特にオープンコレクタのワイアードオアの２つの信号線
をインタフェース規定Ｖ１１の４線式伝送路で接続した
非較的長距離伝送の双方向中継回路に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bidirectional relay circuit,
In particular, the present invention relates to a bidirectional relay circuit for comparatively long-distance transmission in which two wired or open-collector signal lines are connected by a four-wire transmission line of interface specification V11.
【０００２】[0002]
【従来の技術】従来この種の双方向中継回路は図２に示
す構成である。即ち図２において、ワイアードオア接続
の双方向の信号線６と距離的に離れた同様なワイアード
オア接続の双方向の信号線８とをインタフェース回路
８，９を介しＶ１１伝送路３で接続中継するものであ
る。信号線６，７にはそれぞれ複数の回路１ａ，５ａが
接続されており、回路１ａ，５ａはそれぞれオープンコ
レクタ出力端１１，５１とハイインピーダンスの入力端
１２，５２とを備え、信号線に対しワイヤードオアで接
続され相互に信号を送受信している。2. Description of the Related Art Conventionally, this type of bidirectional relay circuit has a configuration shown in FIG. That is, in FIG. 2, a wired or connected bidirectional signal line 6 and a similar wired or connected bidirectional signal line 8 distant from each other are connected and relayed on the V11 transmission line 3 via the interface circuits 8 and 9. Things. A plurality of circuits 1a and 5a are connected to the signal lines 6 and 7, respectively. The circuits 1a and 5a have open collector output terminals 11 and 51 and high impedance input terminals 12 and 52, respectively. They are connected by wired OR and send and receive signals to and from each other.
【０００３】信号線６が論理０すなわちアクティブにな
ると、インタフェース回路８のインバータ８１とアンド
ゲート８２とを通してＶ１１伝送路３のＶ１１ドライバ
３１をドライブしてこの信号を伝送路に送出する。長距
離伝送された信号は受信側のＶ１１レシーバ３３で受信
され、インタフェース回路９のオープンコレクタ９１を
通して信号線７を論理０すなわちアクティブとする。When the signal line 6 becomes logic 0, that is, becomes active, the V11 driver 31 of the V11 transmission line 3 is driven through the inverter 81 and the AND gate 82 of the interface circuit 8 to transmit this signal to the transmission line. The signal transmitted over a long distance is received by the V11 receiver 33 on the receiving side, and the signal line 7 is set to logic 0, that is, active through the open collector 91 of the interface circuit 9.
【０００４】信号線７がアクティブとなることによりイ
ンバータ９３を通して逆方向に信号が伝送されようとす
るが、インバータ９２を通してアンドゲート９４に論理
０が与えられているため逆方向の伝送は阻止される。When the signal line 7 becomes active, a signal is to be transmitted in the reverse direction through the inverter 93. However, since the logic 0 is given to the AND gate 94 through the inverter 92, the transmission in the reverse direction is prevented. .
【０００５】また、信号線７が先に論理０になった場合
は、以上の動作と同様にインバータ９３、アンドゲート
９４、Ｖ１１ドライバ３４、Ｖ１１レシーバ３２及びオ
ープンコレクタ８４を通して信号が伝送され、信号線６
を論理０とする。When the signal line 7 becomes logic 0 first, a signal is transmitted through the inverter 93, the AND gate 94, the V11 driver 34, the V11 receiver 32, and the open collector 84, as in the above operation. Line 6
Is logical 0.
【０００６】信号線６が論理０になったことにより逆方
向に信号が伝送されようとするが、同様にアンドゲート
８２にはインバータ８３を通して論理０が与えられてい
るため逆方向の伝送は阻止される。When the signal line 6 becomes logical 0, a signal is transmitted in the reverse direction. Similarly, since the logical 0 is given to the AND gate 82 through the inverter 83, the transmission in the reverse direction is prevented. Is done.
【０００７】[0007]
【発明が解決しようとする課題】このように従来の双方
向中継回路では、信号線６と信号線７において、先に論
理０になったことにより伝送方向を決定しているため、
信号線６と信号線７が同時に論理０になった時は、伝送
方向の決定ができなくなる。各素子には遅延があるため
信号線６の信号は信号線７に、信号線６は信号線７にそ
れぞれ遅れて到着し、それぞれ送信の信号を断とする
が、相手側ではこの断を遅れて検出し、また送信を始
め、相互の遅延差によりこれを繰り返すようになり発振
状態となる。即ち略信号線６，７が同時に論理０となっ
た時は発振状態となり、信号伝送が不可能となる問題が
ある。As described above, in the conventional bidirectional relay circuit, the signal line 6 and the signal line 7 determine the transmission direction by first becoming logic 0,
When the signal line 6 and the signal line 7 simultaneously become logical 0, the transmission direction cannot be determined. Since each element has a delay, the signal on the signal line 6 arrives at the signal line 7 and the signal line 6 arrives at the signal line 7 with a delay, and the transmission signal is cut off. , And transmission is started, and this is repeated due to the mutual delay difference, and an oscillation state is established. In other words, when the signal lines 6 and 7 have the logic 0 at the same time, they are in the oscillation state, and there is a problem that signal transmission becomes impossible.
【０００８】[0008]
【課題を解決するための手段】本発明の双方向中継回路
は、複数のオープンコレクタ出力回路および入力回路を
ワイアードオアで接続する２線式双方向性の距離的に隔
った２つの信号線をインタフェース規定Ｖ．１１で接続
する４線式双方向性のＶ．１１伝送路の双方向中継回路
において、前記信号線の入力回路で信号の論理０を判定
する最高電圧をＶ１とし、前記オープンコレクタ出力回
路の論理０の電圧をＶ２とし、前記信号線と前記Ｖ．１
１伝送路とのインタフェース点で前記Ｖ．１１伝送路の
送信側が信号の論理０を判定する最高電圧Ｖ３とし、前
記Ｖ．１１伝送路の受信側が前記信号線に送出する信号
の論理０の電圧Ｖ４とした時、それぞれＶ２＜Ｖ３＜Ｖ
４＜Ｖ１の関係を満足させる電圧とし、前記Ｖ．１１伝
送路の受信側の信号が送信側に廻り込まないようにして
いる。SUMMARY OF THE INVENTION A bidirectional relay circuit according to the present invention is a two-wire bidirectional two-line signal line for connecting a plurality of open-collector output circuits and input circuits by wired OR. To the interface definition V. 11 connected by 4-wire bidirectional V.11 In the bidirectional relay circuit of the eleventh transmission line, the maximum voltage for determining the logic 0 of the signal in the input circuit of the signal line is V1, the voltage of the logic 0 of the open collector output circuit is V2, and the signal line and the V . 1
1 at the interface point with the transmission line. 11 is the highest voltage V3 at which the transmission side of the transmission line determines the logic 0 of the signal. 11 when the receiving side of the transmission line sets the voltage V4 of the logic 0 of the signal transmitted to the signal line to V2 <V3 <V
4 <V1. The signal on the receiving side of the eleven transmission lines is prevented from sneaking into the transmitting side.
【０００９】例えば前記信号線に接続される各前記オー
プンコレクタ出力回路および入力回路はそれぞれの接続
点に出力電圧が前記Ｖ２および論理０を判定する閾値が
前記Ｖ１のＣ−ＭＯＳゲートを使用し、前記信号線と前
記Ｖ１１伝送路の送信側とのインタフェースに第１の入
力側を前記信号線に第２の入力側を順方向電圧が前記Ｖ
３のダイオードを用いた基準電圧源にまた出力側を前記
Ｖ１１伝送路側にそれぞれ接続するコンパレータを用
い、前記信号線と前記Ｖ１１伝送路の受信側とのインタ
フェースに入力側を前記Ｖ１１伝送路の受信側に出力側
をツュナー電圧が前記Ｖ４の定電圧ダイオードを介し前
記信号線にそれぞれ接続するオープンコレクタのバッフ
ァ回路を用いるようにすれば良い。[0009] For example, each of the above
Open collector output circuit and input circuit are connected separately
The point at which the output voltage is V2 and the threshold for determining logic 0 is
The V1 C-MOS gate is used, and the signal line and the
The first input is provided to the interface with the transmitting side of the V11 transmission line.
The input side is the signal line, the second input side is the forward voltage V
The output side is also connected to the reference voltage source using the diode of No. 3.
Use comparators connected to the V11 transmission line
And an interface between the signal line and the receiving side of the V11 transmission line.
Input side to the face and output side to the receiving side of the V11 transmission line
Before the tuner voltage passes through the V4 constant voltage diode.
Open collector buffers connected to the signal lines
A circuit may be used .
【００１０】[0010]
【実施例】次に本発明の一実施例について図面を参照し
て説明する。図１は本実施例の構成を示すブロック図で
ある。ワイアードオア接続の双方向の信号線６と距離的
に離れた同様なワイアードオア接続の双方向の信号線８
とをインタフェース回路２，４を介しＶ．１１伝送路３
で接続中継している。Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of this embodiment. A similar wired-or-connected bidirectional signal line 8 spaced apart from a wired-or-connected bidirectional signal line 6
Through the interface circuits 2 and 4. 11 transmission line 3
Is connected and relayed.
【００１１】信号線６，７にはそれぞれ複数の回路１
ａ，５ａが接続されており、回路１ａ，５ａはそれぞれ
オープンコレクタ出力端１１，５１とハイインピーダン
スの入力端１２，５２とを備え、信号線に対しワイヤー
ドオアで接続され相互に信号を送受信している。Each of the signal lines 6 and 7 has a plurality of circuits 1
a and 5a are connected, and the circuits 1a and 5a have open collector output terminals 11 and 51 and high impedance input terminals 12 and 52, respectively, and are connected to signal lines by wired OR to transmit and receive signals to and from each other. ing.
【００１２】即ち信号線６にて１つの回路１ａのコレク
タ出力端１１がオンとなれば、その信号は信号線６及び
信号線７のすべての回路１ａ，５ａの入力端１２，５２
で検出される。また、信号線６と信号線７の距離は通常
１０ｍほどあるために信号線をそのまま延長するとノイ
ズ等の影響があるので、信号のインタフェース条件をＣ
Ｃ１ＴＴ勧告のＶ．１１に変換して４線式双方向の伝送
路で接続している。That is, when the collector output terminal 11 of one circuit 1a is turned on on the signal line 6, the signal is sent to the input terminals 12, 52 of all the circuits 1a, 5a of the signal line 6 and the signal line 7.
Is detected by Further, since the distance between the signal line 6 and the signal line 7 is usually about 10 m, if the signal line is extended as it is, there is an influence of noise or the like.
V1 of the C1TT recommendation. 11 and connected via a 4-wire bidirectional transmission path.
【００１３】信号線６に接続された何れかのオープンコ
レクタ出力端がオンとなり信号線６が論理０となると、
この信号はインタフェース２のコンパレータ２１にて電
圧検出される。しかしこの論理０の電圧はダイオード２
２の順方向電圧より低いので、論理０すなわちアクティ
ブと判定されＶ．１１伝送路３のドライバ３１を駆動し
相手方に伝送される。When any of the open collector output terminals connected to the signal line 6 is turned on and the signal line 6 becomes logic 0,
This signal is detected by the comparator 21 of the interface 2. However, this logic 0 voltage is
2 is lower than the forward voltage of V.2. The driver 31 of the transmission line 3 is driven and transmitted to the other party.
【００１４】レシーバ３３にてこの信号が受信され、イ
ンタフェース回路４のインバータ４１を通しオープンコ
レクタ４２を駆動する。オープンコレクタ４２の出力は
論理０となるが、ダイオード４３の順方向電圧だけ高い
電圧が信号線７に与えられる。This signal is received by the receiver 33, and drives the open collector 42 through the inverter 41 of the interface circuit 4. The output of the open collector 42 becomes logic 0, but a voltage higher by the forward voltage of the diode 43 is applied to the signal line 7.
【００１５】信号線７がこの論理０の電圧となり、各回
路５ａの入力端５２は論理０を判定する基準電圧がこれ
より高いのでこれを検出する。またコンパレータ４４も
これを検出しようとするが、基準電圧、即ちダイオード
４５の順方向電圧より信号線７の論理０の電圧（ダイオ
ード４３の順方向電圧に配線などの降下電圧が加わる）
の方がわずかに高いために検出されず、逆方向に信号が
戻ることを阻止している。The signal line 7 has the logic 0 voltage, and the input terminal 52 of each circuit 5a detects the reference voltage for judging the logic 0 since it is higher than this. The comparator 44 also tries to detect this. However, the voltage of logic 0 of the signal line 7 is higher than the reference voltage, that is, the forward voltage of the diode 45 (a voltage drop such as wiring is added to the forward voltage of the diode 43).
Is not detected because it is slightly higher, preventing the signal from returning in the opposite direction.
【００１６】一方、信号線７に接続された何れかのオー
プンコレクタ出力端５１がオンとなると、コンパレータ
４４がこの論理０の信号を検出し、ドライバ３４を駆動
し、Ｖ．１１伝送路３に送出する。On the other hand, when any of the open collector output terminals 51 connected to the signal line 7 is turned on, the comparator 44 detects the logic 0 signal, drives the driver 34, and drives the V.V. 11 to the transmission path 3.
【００１７】伝送された信号はレシーバ３２にて受信さ
れインバータ２５を通してオープンコレクタ２４を駆動
する。オープンコレクタ２４の出力は論理０となるがダ
イオード２３の順方向電圧だけ高い電圧が信号線６に与
えられる。信号線６がこの論理０の電圧になったことに
より、各受信回路にはこれを検出する。またコンパレー
タ２１でも検出しようとするがダイオード２２の順方向
電圧より信号線６の電圧の方がわずかに高いために検出
されず逆方向に信号が戻るのを阻止する。The transmitted signal is received by the receiver 32 and drives the open collector 24 through the inverter 25. The output of the open collector 24 becomes logic 0, but a voltage higher by the forward voltage of the diode 23 is applied to the signal line 6. When the signal line 6 becomes the voltage of the logic 0, each receiving circuit detects this. The comparator 21 also tries to detect the signal, but the signal on the signal line 6 is slightly higher than the forward voltage of the diode 22, so that the signal is not detected and the signal is prevented from returning in the reverse direction.
【００１８】信号線６，７に接続された各回路１ａ，５
ａはＣ−ＭＯＳゲートを使用しているので、オープンコ
レクタ１１，５１出力端のオン即ち論理０の出力電圧は
０．４Ｖ以下であり、また入力端１２，５２が論理０を
検出する最高電圧は１．５Ｖ程度である。またダイオー
ド２２，２３，４３，４５はシリコンダイオードを使用
しているので順方向電圧は０．６Ｖ程度である。またイ
ンタフェース回路より受信する信号線の論理０の電圧は
ダイオード２３，４３の順方向電圧に配線による降下電
圧が加わるので１Ｖ程度である。Each circuit 1a, 5 connected to signal lines 6, 7
Since a uses a C-MOS gate, the output terminals of the open collectors 11 and 51 are turned on, that is, the output voltage of logic 0 is 0.4 V or less, and the maximum voltage at which the input terminals 12 and 52 detect logic 0 is detected. Is about 1.5V. Since the diodes 22, 23, 43 and 45 use silicon diodes, the forward voltage is about 0.6V. The logic 0 voltage of the signal line received from the interface circuit is about 1 V because a voltage drop due to wiring is added to the forward voltage of the diodes 23 and 43.
【００１９】尚、ダイオード２３，４３は配線降下電圧
が小さい場合、ツェナー電圧１Ｖ程度の定電圧ダイオー
ドなどを使用しても良い。When the wiring drop voltage is small, a constant voltage diode having a Zener voltage of about 1 V may be used as the diodes 23 and 43.
【００２０】[0020]
【発明の効果】以上説明したように本発明の双方向中継
回路は、Ｖ１１インタフェースはワイアードオアの双方
向信号線を点において受信側の論理０の電圧と送信側で
検出する論理０の電圧との間で電圧差を設けて受信信号
が送信側に廻り込むのを阻止しているので、２つの信号
線が略同時に論理０となり送信した場合、その送信タイ
ミングにより廻り込みを阻止する場合に比べて、信号の
タイミングに依存してないので、発振状態になることが
なく常に安定に動作するという効果がある。As described above, in the bidirectional relay circuit according to the present invention, the V11 interface has a logic 0 voltage on the receiving side and a logic 0 voltage detected on the transmitting side at the point of the wired-or bidirectional signal line. A voltage difference is provided between the signal lines to prevent the reception signal from sneaking into the transmission side. Therefore, when two signal lines become logic 0 almost at the same time and are transmitted, compared with the case where the sneaking is prevented by the transmission timing. In addition, since it does not depend on the timing of the signal, there is an effect that the operation is always stable without the oscillation state.
【図１】本発明の一実施例の構成を示すブロック図であ
る。FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.
【図２】従来例の構成を示すブロック図である。FIG. 2 is a block diagram showing a configuration of a conventional example.
１ａ，５ａ 回路 ２，４ インタフェース回路 ３ Ｖ１１伝送路 １１，５１ オープンコレクタ出力端 １２，５２ 入力端 ２１，４４ コンパレータ ２２，２３，４３，４５ ダイオード ２４，４２ オープンコレクタ ３１，３４ ドライバ ３２，３３ レシーバ 1a, 5a circuit 2, 4 interface circuit 3 V11 transmission line 11, 51 open collector output terminal 12, 52 input terminal 21, 44 comparator 22, 23, 43, 45 diode 24, 42 open collector 31, 34 driver 32, 33 receiver
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平７−307725（ＪＰ，Ａ) 特開 昭48−43815（ＪＰ，Ａ) 特開 昭63−74237（ＪＰ，Ａ) 特開 昭56−120241（ＪＰ，Ａ) 実開 平６−31247（ＪＰ，Ｕ) (58)調査した分野(Int.Cl.6，ＤＢ名) H04L 25/00 - 25/66 H04B 3/36 H04L 5/16 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-7-307725 (JP, A) JP-A-48-43815 (JP, A) JP-A-63-74237 (JP, A) 120241 (JP, A) Japanese Utility Model Hei 6-31247 (JP, U) (58) Field surveyed (Int. Cl. 6 , DB name) H04L 25/00-25/66 H04B 3/36 H04L 5/16
Claims (2)
入力回路をワイアードオアで接続する２線式双方向性の
距離的に隔った２つの信号線をインタフェース規定Ｖ．
１１で接続する４線式双方向性のＶ．１１伝送路の双方
向中継回路において、前記信号線の入力回路で信号の論
理０を判定する最高電圧をＶ１とし、前記オープンコレ
クタ出力回路の論理０の電圧をＶ２とし、前記信号線と
前記Ｖ．１１伝送路とのインタフェース点で前記Ｖ．１
１伝送路の送信側が信号の論理０を判定する最高電圧Ｖ
３とし、前記Ｖ．１１伝送路の受信側が前記信号線に送
出する信号の論理０の電圧Ｖ４とした時、それぞれＶ２
＜Ｖ３＜Ｖ４＜Ｖ１の関係を満足させる電圧であること
を特徴とする双方向中継回路。A two-wire bidirectional two-line signal line connecting a plurality of open-collector output circuits and input circuits by wired OR is defined by an interface specification V.
11 connected by 4-wire bidirectional V.11 In the bidirectional relay circuit of the eleventh transmission line, the maximum voltage for determining the logic 0 of the signal in the input circuit of the signal line is V1, the voltage of the logic 0 of the open collector output circuit is V2, and the signal line and the V . 11 at the interface point with the transmission line. 1
The highest voltage V at which the transmission side of one transmission path determines the logic 0 of the signal
3; When the receiving side of the transmission line 11 sets the signal to be sent to the signal line to the logic 0 voltage V4,
A bidirectional relay circuit, wherein the voltage satisfies the relationship of <V3 <V4 <V1.
コレクタ出力回路および入力回路はそれぞれの接続点に
出力電圧が前記Ｖ２および論理０を判定する閾値が前記
Ｖ１のＣ−ＭＯＳゲートを使用し、前記信号線と前記Ｖ
１１伝送路の送信側とのインタフェースに第１の入力側
を前記信号線に第２の入力側を順方向電圧が前記Ｖ３の
ダイオードを用いた基準電圧源にまた出力側を前記Ｖ１
１伝送路側にそれぞれ接続するコンパレータを用い、前
記信号線と前記Ｖ１１伝送路の受信側とのインタフェー
スに入力側を前記Ｖ１１伝送路の受信側に出力側をツュ
ナー電圧が前記Ｖ４の定電圧ダイオードを介し前記信号
線にそれぞれ接続するオープンコレクタのバッファ回路
を用いることを特徴とする請求項１記載の双方向中継回
路。2. An open collector output circuit and an input circuit connected to the signal line use a C-MOS gate whose output voltage is V2 and whose threshold for judging logic 0 is V1 at each connection point. , The signal line and the V
An interface with the transmission side of the transmission line 11 has a first input side as the signal line, a second input side as a reference voltage source using a diode whose forward voltage is V3, and an output side as V1.
One comparator is connected to each transmission line side, and the input side is connected to the interface between the signal line and the reception side of the V11 transmission line, and the output side is connected to the reception side of the V11 transmission line. 2. The bidirectional relay circuit according to claim 1, wherein an open-collector buffer circuit connected to each of said signal lines is used.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16047495A JP2944467B2 (en) | 1995-06-27 | 1995-06-27 | Bidirectional relay circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16047495A JP2944467B2 (en) | 1995-06-27 | 1995-06-27 | Bidirectional relay circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0918524A JPH0918524A (en) | 1997-01-17 |
| JP2944467B2 true JP2944467B2 (en) | 1999-09-06 |
Family
ID=15715741
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16047495A Expired - Fee Related JP2944467B2 (en) | 1995-06-27 | 1995-06-27 | Bidirectional relay circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2944467B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7130745B2 (en) | 2005-02-10 | 2006-10-31 | Toyota Technical Center Usa, Inc. | Vehicle collision warning system |
| JP2013219641A (en) * | 2012-04-11 | 2013-10-24 | Mitsubishi Electric Corp | Data transmission device |
| JP6952493B2 (en) * | 2017-05-19 | 2021-10-20 | 三菱電機株式会社 | Communication system and relay device |
-
1995
- 1995-06-27 JP JP16047495A patent/JP2944467B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0918524A (en) | 1997-01-17 |
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|---|---|---|---|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
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| LAPS | Cancellation because of no payment of annual fees |