JP2941843B2 - Apparatus and method for reducing image signal - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image signal forming apparatus and method for forming a reduced image signal representing a reduced image of an original image by reducing an image signal representing the original image. Things.

[Conventional technology]

In a facsimile device that is a typical example of a conventional still image communication device, an image is scanned sequentially,
An encoding transmission method is used. In this method, it is necessary to transmit all of the image data in order to grasp the entire image of the image, so it takes a long transmission time, and it is necessary to quickly determine the image using an image database service, video tex, etc. However, it has been difficult to apply the technology to the image communication service. Unlike the method used by facsimile to realize this service, when transmitting a single image, rough image information is sent first,
After that, additional information is transmitted and detailed image data is generated. The sequential reproduction coding method (Endo, Yamazaki, “Sequential reproduction coding method of facsimile signal suitable for conversational image communication”,
Methods such as IEICE (B), J67-B.12, pp1462-1469 (1984)) have been proposed.

[Problems to be Solved by the Invention] However, in the above-described conventional example, rough image information to be transmitted first generates a reduced image by thinning out pixels at specific intervals from the original image. Will not be able to transmit valid image information in the first place,
For example, there is a problem that a straight line having a width of one pixel disappears.

[Means for solving the problem]

The present invention has been made in view of the above points, and provides an image that outputs a reduced image signal representing a reduced image obtained by reducing the original image by half in the main scanning and sub-scanning directions from an image signal representing the original image. In a signal reduction device, input means for inputting an image signal representing an original image to be reduced, and reducing the image signal input by the input means by half in each of the main scanning and sub-scanning directions Forming means for forming and outputting a reduced image signal, wherein the forming means comprises: (a) an image signal of a plurality of pixels defined by the following (a) to (c): The image signal of the target pixel X (i, j) in the original image to be reduced, (b) the target pixel X (i, j,
j) eight pixels X (i-1, j-1), X (i-1, j), X
(I−1, i + 1), X (i, j−1), X (i, j + 1), X (i +
1, j-1), X (i + 1, j), X (i + 1, j + 1) image signals, and (c) the forming means halves the image signals in the main scanning direction and the sub-scanning direction, respectively. A reduction process using a predetermined filtering coefficient is performed on each of the reduced image signals of a plurality of reduced pixels in the vicinity of the pixel of interest X (i, j) formed by the reduction process. , j), forming and outputting a reduced image signal corresponding to (a) to (c).
When the pattern of the image signal of a plurality of pixels defined by the above is not suitable for the reduction processing using the predetermined filtering coefficient, it is different from the reduced image signal formed by the reduction processing using the predetermined filtering coefficient. It is an object of the present invention to provide an image signal reducing device that outputs a reduced image signal having a value.

Also, the present invention reduces the image signal representing the original image by half in each of the main scanning and sub-scanning directions, thereby reducing the original image by half in each of the main scanning and sub-scanning directions.
This is a method of reducing an image signal for outputting a reduced image signal representing a reduced image reduced to a plurality of pixels, the image signal having a plurality of pixels defined by the following (a) to (c): An image signal of the pixel of interest X (i, j) in the image; (b) eight pixels X around the pixel of interest X (i, j) in the original image
(I−1, j−1), X (i−1, i), X (i−1, j + 1), X
(I, j-1), X (i, j + 1), X (i + 1, j-1), X (i +
(J), X (i + 1, j + 1) image signals and (c) an image signal formed by reducing the image signal representing the original image by half in the main scanning direction and the sub-scanning direction, respectively. By performing a reduction process using a predetermined filtering coefficient on each of the reduced image signals of the plurality of reduced pixels near the pixel X (i, j), a reduced image signal corresponding to the target pixel X (i, j) is obtained. When the pattern of the image signal of a plurality of pixels defined in the above (a) to (c) is incompatible with the reduction processing using the predetermined filtering coefficient, the predetermined filtering coefficient The present invention provides a method for reducing an image signal that outputs a reduced image signal having a value different from that of a reduced image signal formed by a reduction process using the image processing.

Embodiment 1 FIG. 1 is a drawing showing a configuration of a reduction circuit to which the present invention is applied. First, binary original image data indicating whether each pixel is white or black is stored in the frame memory 1 for each screen. The data in the frame memory 1 is stored in the filtering circuit 2, the first
, The second correction circuit 6b, the third correction circuit 6c, and the image attribute detection means 5.

In the filtering circuit 2, low-pass filtering is performed on the input data, and the output is relatively input to 3. In this embodiment, a low-pass filter is used as a filter. However, the present invention is not limited to this, and a high-pass filter or a recursive filter may be used. The comparator 3 compares the value output from the filtering circuit 2 with a threshold value T (here, T = 8), and outputs "1" if the value is larger than the threshold value and "0" if it is smaller than the threshold value. You. In the sub-sampling circuit 4, the signal output from the comparator 3 is
The process of thinning out to 1/2 is performed.

The image attribute detection circuit 5 determines the attribute of the image based on the signal read from the frame memory 1 and switches the output of the selector 7 based on the determination.

Each of the correction circuits 6a-6c is constituted by a ROM (Read Only Memory), and its input section receives a signal (original image data) from the frame memory 1 and a signal from a frame memory 9 (reduced image data) to be described later. A signal is input.
The first correction circuit 6a stores correction values emphasizing positive images such as characters and line drawings. The second correction circuit 6b stores correction values focusing on negative images such as characters and line drawings, and the third correction circuit 6c focuses on halftone images subjected to dither processing or the like. Is stored.

The selector 7 selects one of the outputs of the correction circuits 6a-6c based on the output from the image attribute detection circuit 5, and outputs the selected one.
The output value is input to the selector 8 and serves as a switching signal for selecting either the signal output from the sub-sampling unit or its inverted signal. The output signal from the selector 8 is stored in the frame memory 9.

As described above, the optimum reduced image can be obtained by detecting the attributes of the image, selecting a correction process suitable for the characteristics of the image according to the detection output, and performing the correction process on the sub-sampled image. Can be.

 Hereinafter, the details of each unit in FIG. 1 will be described.

FIG. 2 is a circuit diagram of a filter 3 used in the filtering circuit 2.
A filter coefficient of a low-pass filter having a size of 3 pixels is shown, and a weight coefficient of a center pixel is C (here, C = 4).
The center pixel is given a weighting factor of 2 for the nearest 4 pixels, and 1 for the next closest pixel.

Thus the value of the center pixel _{D i, j (i = 1~M} , j =
1 to N: M and N are horizontal and vertical pixel sizes)
The average density W is: W = (D _{i−1, j−i} + 2D _{i, j−1} + D _{i + 1, j−1} + 2D _{i−1, j} + CD _{i, j} + 2D _{i + 1, j} + D _{i−1, j + 1)} + 2D _{i, j + 1} + D _{i + 1, j + 1} ). This average density W becomes the output of the filtering circuit 2, To binarize.

The corresponding relationship is given.

FIG. 3 is a block diagram of a low-pass filter. The input signals are held in the latches 11a, 11b, 11c with a delay of one pixel clock. The line memories 10-a and 10-b hold input signals delayed by one line, respectively, and latches 11d and 11d.
In e, f or the latches 11g, h, i, signals corresponding to the latches a, b, c and the pixel positions are obtained. As a result, data of nine pixels shown in FIG. 2 is obtained. Latch 11a, c,
The output signals from g and i are summed by an adder 12a,
An operation of a constant multiple (× 1) is performed in 13a.

The output signals from the latches 11b, d, f, and h are summed by an adder 12b and multiplied by a constant (× 2) by a multiplier 13b. The output signal from the latch 11e, which is the median, is
Multiplied by a constant (× C) by 3c. The value of C can be set from outside.

The output signals of the multipliers 13a, 13b and 13c are summed by the adder 14 (= average density W) and output. This signal is compared with the threshold value T by the comparator 3 in FIG. 1, and a signal of 1 is obtained when the sum is larger than the threshold value T, and a signal of 0 is obtained when the sum is smaller than the threshold value T. This threshold value T can be set from the outside, but T = (12
+ C) / 2.

FIG. 4 is an explanatory diagram of the operation of the sub-sampling circuit 4. By taking out pixel data indicated by oblique lines in the figure at every other timing in the main scanning and sub-scanning directions,
A sub-sampled image of 1/2 size (1/4 in area) is formed. This can be easily realized by adjusting the latch timing of the image data.

Next, the image attribute detection circuit 5 will be described. The image attributes referred to here include, for example, characters and line drawings (positive images),
Alternatively, it is a distinction such as a negative image or a dither image.

By the way, the easiest way to know the attributes of an image is to read the attributes of the image at the same time as reading the original image into the frame memory. For example, when the input is an image database or the like, the main attribute is often included as header information, so the information may be read from there.
If there is no header information, enter it from outside or
Detection is performed as follows as in the present embodiment.

That is, as a method of detecting the attribute of an image in a local region of the image, 5 × 5 pixels centering on the pixel being processed are considered. This is shown in FIG.

Here, X (i, j) indicates a target pixel. When the sum of the densities of the 5 × 5 pixel area is S, Can be expressed as

Here, the image data input to the frame memory 1 is a binary image in which white is 0 and black is 1, so S ≧ TN (here,
If TN = 18), it is determined that the image is a negative image having many black pixels as a whole. Although the threshold value TN, which is used as a criterion for determining whether the image is a positive or negative image, is set at 18, here, this value may be increased to further increase the accuracy, and is not limited to this value.

Next, in the dither image, the property that black pixels appear every other pixel is used, and in order to distinguish the dither image, the pixel inversion rate H is defined as follows.

In the case of a dither image, the value of H is larger than that of a character or a line drawing. Therefore, if H ≧ TD (TD = 30 in this case),
Judge as a dither image. Here, the threshold value TD is not limited to 30, and may be another value.

The image attribute detection circuit 5 outputs a 2-bit signal "11" to the selector 7 as an output signal if it is determined that the image is a dither image based on the above calculation result. If it is not a dither image and it is determined to be positive,
A 2-bit signal "00" is output, and if it is determined that the image is not a dither image and a negative image, a 2-bit signal "01" is output to the selector 7.

The selector 7 selects the output from the first correction circuit 6a if the signal input from the image attribute detection circuit 5 is "00", and selects the output from the second correction circuit 6b if the input signal is "01".
And if the input signal is "11", the output from the third correction circuit 6c is selected and output to the selector 8. That is, the selector switching signal suitable for the image attribute is selected by the selector 7.

In the selector 8, if the switching signal input from the selector 9 is "0", the signal output from the sub-sampling circuit 4 is directly output to the frame memory 9, and if "1", the signal output from the sub-sampling circuit 4 is output. Is output to the frame memory 9. That is, when the sub-sampled pixel does not match the image attribute, the selector 8 performs an operation of inverting the value and matching the image attribute with the image attribute.

FIG. 6 shows the positions of the image signals input to the correction circuits 6a-6c. Up to a-i are the planes of the original image, and j- are the planes of the reduced image. That is, a switching signal suitable for each image attribute is output using the nine pixels including the pixel of interest to be subsampled and the result of the previously subsampled. That is, e represents the target pixel e. Or, corresponding to the pixel of the reduced screen obtained by sub-sampling the pixel of interest, j is the pixel immediately above the pixel b, and k is the pixel of the reduced screen obtained by sub-sampling the pixel to the left of the pixel d. Yes, it is.

The input from the frame memory 1 is the value of nine pixels from a to i, and the input from the frame memory 9 is the value of two pixels j and k. Each of the first to third correction circuits 6a to 6c has a correction table which is addressed by these pixels and outputs a switching signal.

Next, a method of creating a correction table will be described with reference to FIGS. 7 to 9 indicate black pixels. In the case of the pattern as shown in FIG.
Is "1" (black). Now, if it is a positive image of a character or a line drawing, the reduced image is preferably black. Therefore, the first signal is output so that the output from the sub-sampling circuit 4 is output as it is.
The correction circuit 6a needs to be configured to output "0" as a switching signal. However, in the case of a negative image, the white information in a black background is important, and the reduced image is desirably white in order to save the white information. Therefore, the output from the sub-sampling circuit 4 is inverted and output. Second correction circuit 6b
Therefore, it is necessary to configure so as to output “1” as the switching signal.

In both the patterns shown in FIGS. 8A and 8B, the reduced image obtained by sub-sampling the pixel of interest e is black if it is a positive image as in the pattern of FIG. In the case of a negative image, it is desirable that the reduced image be white. Therefore, the second correction circuit 6b is configured to output "1" as a switching signal.

In the case of the pattern as shown in FIG. 9, the output of the sub-sampling circuit 4 is "0", and if the image is a normal image (an image that is not a dither image), the reduced image should be white. However, in the case of a dither image, the dots constituting the dither pattern should be expressed by making the reduced image black. Therefore, the third correction circuit 6c is configured to output "1" as a switching signal. Thus, the correction circuit 6a
In −6c, a correction table for outputting a correction value corresponding to each attribute is stored.

As described above, the image attribute detecting circuit 5 for detecting the attribute of the image and the plurality of correction circuits 6a to 6
6c, one of a plurality of correction circuits 6a to 6c is selected according to a signal from the image attribute detection circuit 5, and the output value from the sub-sampling circuit 4 is corrected using the selected one.
It is possible to prevent the loss of the image to be stored according to the image attribute, and to obtain a reduced image with good image quality.

[Embodiment 2] FIG. 10 is a block diagram when the reduction circuit shown in FIG. 1 is applied to hierarchical coding.

Reference numerals 15, 17, and 19 denote frame memories, reference numerals 16 and 18 denote reduction circuits having the configuration shown in FIG. 1, reference numerals 20, 22, and 24 denote reference pixel determination circuits, and reference numerals 21, 23, and 25 denote encoders.

First, the original image data I of the binary image signal is stored in the frame memory 15. Next, the image data is reduced by the reduction circuit 16 and stored in the frame memory 17. The signal stored at this time is reduced to half of the original image. Similarly, the signal read from the frame memory 17 is reduced to a quarter of the original image by the reduction circuit 18 and stored in the frame memory 19.

Reference pixel determination circuits 20, 22, and 24 are frame memories, respectively.
The size (number of pixels) of the image data stored in 19, 17, and 15 is detected, and the optimal number of reference pixels and the reference pixel position at the time of encoding are set.

The encoder 21 encodes the signal stored in the frame memory 19 using the reference pixel set by the reference pixel determination circuit 20, and outputs the encoded signal as a first-stage signal 107. Similarly, the encoders 23 and 25 use the reference pixels set by the reference pixel determination circuits 22 and 24, respectively, to
The signals stored in 7 and 15 are encoded and output as a second-stage signal 108 and a third-stage signal 109, respectively.

By encoding and transmitting the image data from the first stage to the third stage in order from the image data having the lower resolution in this way, the entire image of the image can be identified quickly, and if the data is unnecessary, Can be stopped. This enables an efficient image communication service.

Also. Although we have only described here up to the third stage,
It goes without saying that it can be easily extended to any stage.

The encoding operation in the encoders 21, 23, 25 will be described. In this embodiment, encoding using an arithmetic code is performed.

The arithmetic code predicts the value of the pixel of interest from neighboring pixels, and sets the symbol when the prediction matches to the superior symbol (1), the symbol when the prediction is out of order to the inferior symbol (0), or the probability of occurrence of the inferior symbol to P. , And performs encoding based on this information. (Fukibuki, "Signal Processing of Images for FAX and OA," Nikkan Kogyo) Binary arithmetic code C (S) for code sequence S, auxiliary amount A
(S) The encoding is advanced by the arithmetic operation of.

By approximating P (S) = 2- ^{Q (S)} , the arithmetic can be performed only by the binary shift. Q is called a skew value, and an arithmetic code can be dynamically used by changing this parameter.

In decoding, the binary signal sequence S = S'xS ", C (S) is compared with C (S ') + A (S'0) when restored to S', and C (S)> C (S ' ) + A (S'0), 1 is decoded, otherwise 0 is decoded.

FIG. 11 is a block diagram of a circuit for predicting a pixel of interest in the reference pixel determination circuits 20, 22, and 24.

The frame memory 26 is a memory that stores image data to be encoded. Further, the frame memory 27 stores image data which is sub-sampled by 1/2 with the image sent one stage before. Each memory is composed of a two-dimensional memory. The clock of the x address is φ ₁ , y
When the clock of the address and phi _2, the frame memory A
, Φ ₁ , φ ₂ , and フ レ ー ム
₁ , 1 / 2φ ₂ is given, and one pixel of the frame memory A corresponds to four 2 × 2 pixels for one pixel of the frame memory B.

Each data is delayed by one line in the line memories 28 and 29, and is input to the latches 30 and 31. In this latch, data delayed one pixel at a time is held. When the output of each latch corresponds to the pixel position in FIG. 12, the pixel of interest (*) is the latch 30d.
12, No. 1 is the output of the latch 30e, No. 2 is the output of the latch 30b, and similarly, No. 3 is the output of the latch 30a, and No. 4 is the output of the latch 30c.

The pixel positions in FIG. 13 are as follows: No. 5: Latch 31b, No. 6: Latch 31a, No. 7: Latch 31d, No. 8: Latch 31c, No. 9
Is the output of the latch 31e.

Note that the No. 5 pixel in FIG. 13 is a pixel including the target pixel, and is a 2-bit signal for identifying which position of the target pixel is No. 5 (upper left, upper right, lower left, lower right). The counter 32
Generated from φ ₁ and φ ₂ . 33a to 33k are AND elements. Here, signals 201 to 211 set by controllers (not shown) and latches 30a to c, e and latches 31a to 31a are shown.
e, AND operation with the output of the counter 32 is performed, and the predicted state signal 300 of the target pixel is output. The operation of this part is described below.

In general, when encoding is performed dynamically, a pixel of interest is predicted from the state of surrounding pixels, and the Skew Value is updated while calculating a hit probability of the prediction. Therefore, in order to reflect the statistical property of the symbol sequence to be encoded in the skew value, a considerable number of symbols are required in each state to grasp the statistical property of each symbol sequence. For example, if the total number of symbols is 65536, the number of states is 2 ¹¹
If the number of symbols is taken, the average number of symbols allocated per state becomes 32, and it is difficult to grasp the statistical properties of the symbol sequence in each state.

Therefore, the controller (not shown) controls the number of states of prediction according to the number of symbols to be coded.
More specifically, in hierarchical coding, the number of symbols to be coded is the smallest in the first stage because the size is reduced for each layer, and the number of symbols increases as the number increases in the second and third stages. . Therefore, when the number of symbols is small, to reduce the number of states, if 203, 209, 211 of the signals 201 to 211 are set to "1" and the rest are set to "0", three bits (8 states) can be obtained as the number of states. Signal as the number of symbols increases
The number of states can be increased by increasing the value of "1" set in 201 to 211.

FIG. 20 shows an example of the values of the signals 201 to 211 in this embodiment. This is merely an example, and the state setting and the signal to be set are not limited to this.

FIG. 14 is a diagram illustrating dynamically the skew value Q and the inferior symbol in the encoders 21, 23, and 25 that perform the encoding operation based on the state signal G300 output from the reference pixel determination circuits 20, 22, and 24 and the target pixel D301. FIG. 4 is a block diagram of a circuit for changing the circuit.
The state signal G300 and the target pixel D301 are input to the state occurrence frequency counter 40 and the energizing symbol counter 41, respectively. The number of the counters is equal to the number of states, and is switched by the state signal G.

The occurrence frequency counter 40 counts how many times the state has occurred, and outputs an update signal 303 when it exceeds a set value S. The number _C 304 of inferior symbols generated during this time is counted by the counter 41. That is, out of the states of S, _C is the inferior symbol. In the following description, the state of S = 16 will be described as a representative.

In the LUT 42, the following coding parameters Q _G 305 and inverted signal 306 of mps (dominant symbol) and zero count (CT) 307 are generated in response to the occurrence of _C inferior symbols.
Is stored in advance.

The zero cant is a value indicating the number of times in the past that the inferior symbol _C is 0 in the S key. That is, in principle, if CT = 0 is initially set, CT is updated to 1 when the state of _C in S is 0, and then CT = 2, CT = 3 if it is repeated twice and three times thereafter. It will be updated.

 FIG. 21 shows an example in the LUT.

In the initial state, CT = 0 is set, and a new Q _G and a next CT value are obtained from the values of _C , respectively.

For example, when CT = 0 and _C = 0, Q _G = 4 and CT = 1. Next, when an update signal 303 comes, when CT = 1 and _C = 0, Q _G = 5 and CT = 2.

Also when _C = 1 in CT = 0 is updated to _{Q G = 4, CT = 1} . The formula to create this table is However, when _C = 0, calculation is performed assuming that _C = 1.

Here, N [x] represents the closest integer value.

Equation (2) uses Q _{G as} the exponent when the occurrence probability of the inferior symbol that occurs when the S state continues for (CT + 1) times is approximated by a power of two.

In the equation (3), CT assumes that the occurrence of inferior symbols is 1/2 ^QG, and recalculates the number of S = 0 pairs of _C = 0. Since 2 ^QG −1 is the number of dominant symbols, a value obtained by dividing this by S is CT. And if CT = 0 Is treated as a special case, and an operation of inverting the value which has been used as the conventional inferior symbol (summer 01) is performed. After that, CT = 0, In other cases, the encoding process is performed normally with the inferior symbol changed.

In FIG. 14, the latch 43 holds the previous Q _G 305, mps inverted signal 306, and CT 307, and is updated to a new state by the update signal 303.

The count signal _{C of the} inferior symbol and the previous CT value 307 are input to the input of the LUT 42, and the Q value updated according to FIG.
_G , the dominant symbol used at the time of converting the mps inverted signal is retained, and this state is updated by the mps inverted signal.

The mps / ▲ ▼ signal indicating the gravity of the cage 44 is sent to the inferior symbol counter.

Here determined the Q _G and mps / ▲ ▼ the coding is to be performed.

FIG. 15, Q _G and mps at the encoder 21, 23, 25 / ▲
FIG. 3 is a block diagram of an arithmetic encoder for performing an arithmetic code by ▼. If the skew value is Q _G 305, Q _G and map / ▲
By giving signal 308, the arithmetic operation shown in equation (1) is performed by the encoder, and encoded data 401 is obtained.

FIG. 16 is a block diagram of the encoder. A prediction circuit similar to the encoder (shown in FIG. 11) and a dynamic adaptation circuit are prepared on the decoding side, and the skew value on the decoder side is set to Q _D
LPS _D 322 with inferior symbol from 321 and LUT and received data 3
The decoding operation is performed in the decoder 46 by 23, and the decoded data 40
Get two.

 FIG. 17 shows an embodiment of the decoder.

The first stage signal 107 is decoded by the decoder 47 and recorded in the frame memory 50. This signal is converted into high-resolution data by a quadruple interpolation process by an interpolator 53, and is then recorded in a video memory 56 by switching a selector 55 by a controller 59. The video memory 56 is composed of a two-port memory. Therefore, the image obtained on the receiving side is displayed on the monitor 57 at any time. The second stage signal 108 is
The data is decoded by the decoder 48 while referring to the data in the frame memory 50, and is recorded in the frame memory 51. This data is interpolated twice by the interpolator 54.
The data is recorded in the video memory 56 by switching the selector 55.

Similarly, after the signal 109 at the third stage is decoded, it is displayed on the monitor 57.

On the other hand, a frame memory which is a decoded image signal of the third stage
The signal at 52 is output to a printer 58 to obtain a hard copy.

Embodiment 3 In the above embodiment, a method of adjusting the smoothing degree by the weighting coefficient of the median of the coefficients of the low-pass filter of 3 × 3 size in the filtering circuit 2 before sub-sampling was adopted. As an example of sampling,
As shown in FIG. 18, when the conversion data W is determined from the original image data D _A , D _B , D _C , D _D , W = α ₁ D _A + α ₂ D _B + α ₂ D _C + α ₂ D _D Α ₁ and α _{2 when}
It is possible to adjust the degree of smoothing and the coding efficiency by changing the coefficient value of.

1 is set when W ≧ T, and 0 when W <T.

When α _{1 "α 2} increases the proportion be determined by D _A, the coding efficiency is improved.

When α ₁ = α _2, the smoothing effect on the image is improved.

Another method of determining the content of Example 4 Figure 21 is seeking _C / S than the number of inferior symbol _C in S pixels, also a system for determining a new Q _G from Figure 22. The initial value is Q _G = 1,
Q _G is updated with the value of _C / S. The second and subsequent continue to determine the sequence Q _G to use the Q _G and _C / S that has been updated. The updated value Q _G ′ is Calculation is performed using a calculation formula such as that described above and stored in a table.

When Q = 1, _C / S> 1/2 (50 in FIG. 20)
0) reverses the superior / inferior symbol.

In the embodiment of FIG. 19 in this case, will determine the Q _G to update inputs the Q _G signal 305 to the LUT 42.

Embodiment 5 In the second embodiment, the number of states that can be taken at each stage is controlled. However, the number of states can be controlled at the same stage according to the size of an image to be encoded. For example, the third
2 ⁷ state when step image size is 1024 × 1024 pixels, 30
The 72 × 4096 when the pixel, it is possible to control so that 2 ¹¹ state. It is also possible to further subdivide and change the reference pixel position and the number of reference pixels for each image size.

When the type of data (for example, a character image or halftone) is known in advance, a reference pixel position suitable for the type can be set and encoded.

It is also possible to hold the output from the image attribute detection circuit 5 shown in FIG. 1 and set the number of reference images and the reference pixel position based on the output.

Embodiment 6 The low-pass filter in the filtering circuit 2 in FIG. 1 may be changed to, for example, a recursive filter.
FIG. 23 shows an example of the coefficient of the recursive filter. In this example, 4 is given to the coefficient of the target pixel, 2 is given to the nearest 4 pixels, and 1 is given to the other. Further, a coefficient of -3 is given to the upper side and the left side of the reduced image. However, the pixels marked with * in the figure have a positional relationship corresponding to the pixel of interest.

Even in such a recursive filter, a high-quality reduced image can be obtained by providing correction means for a character / line image, a dither image, and a negative image.

Seventh Embodiment In the above-described first embodiment, the reduced image is corrected by outputting the binary output of the sub-sampling circuit 4 as it is or by inverting the binary output. In the seventh embodiment, a filtering circuit is used. The reduced image is corrected by performing increase / decrease processing on the output of No. 2 according to the attribute of the image.

For this purpose, the selector 8 shown in FIG.
Instead of the third correction circuits 6a to 6c and the selector 7, first to first
The third correction circuits 61a to 61c, the selector 62, and the adder 63 are provided. The other configuration is the same as that of FIG.

Then, values for increasing or decreasing the output value of the filtering circuit 2 instead of “1” or “0” are used as the correction tables in the first to third correction circuits 61a to 61c as image attributes. Write it in accordingly.

The first to third correction circuits 61a to 61c output correction data according to the data read from the frame memories 1 and 9, as in the embodiment of FIG.

The image attribute detecting circuit 5 detects the attribute of the image and outputs a selection signal to the selector 62, as in the embodiment of FIG.

As a result, the corrected sharp data that matches the attribute of the image is selected by the selector 62 and applied to the adder 63.

Therefore, the output of the filtering circuit 2 is
Are added or subtracted, and then input to the comparator 3. For example, in the case of T to 8, the output of the comparator 3 can be forcibly set to "1" by adding a value of 8 or more to the output of the filtering circuit 2, and conversely, 8 or more. Is subtracted, the output of the comparator 3 can be forcibly set to "0".

As described above, similarly to the embodiment shown in FIG. 1, it is possible to prevent the loss of the image to be stored according to the image attribute, and to obtain a reduced image with good image quality.

Eighth Embodiment In the seventh embodiment, the reduced image is corrected by increasing or decreasing the output of the filtering circuit 2. However, the threshold T for binarizing the output of the filtering circuit 2 is increased or decreased. Can perform the same correction.

That is, as shown in FIG. 25, the first to third correction circuits 64a to 64c
The threshold value to be applied to the comparator 66 is written as a correction table in place of “1” or “0” described above according to each attribute.

Then, the selector 65 is operated according to the output of the image attribute detecting circuit 5 in the same manner as in the embodiment of FIGS. 1 and 25, and a threshold value matching the attribute of the image is applied to the comparator 66.

Therefore, the output of the filtering circuit 2 is binarized by the threshold value from the selector 65. For example, if the maximum value or a value close to the maximum value of the filtering circuit 2 is applied as the threshold value, the output of the comparator 66 can be forcibly set to “0”. If a value or a value close to the minimum value is applied, the output of the comparator 66 can be forcibly set to “1”.

As described above, similarly to the embodiment shown in FIGS. 1 and 24, it is possible to prevent the loss of the image to be stored according to the attribute of the image, and to obtain a reduced value with good image quality.

[Effects of the Invention] As described above, according to the present invention, a reduced image signal representing a reduced image obtained by reducing the original image by half in the main scanning and sub-scanning directions from the image signal representing the original image is output. At this time, the image signal of the pixel of interest in the original image to be reduced and the eight pixels surrounding the pixel of interest, and the image signal representing the original image are reduced by half in each of the main scanning and sub-scanning directions. By performing reduction processing using a predetermined filtering coefficient on each reduced image signal of a plurality of reduced pixels in the vicinity of the formed target pixel, the target pixel X
Since the reduced image signal corresponding to (i, j) is formed and output, the reduced image signal reflects the state of the other reduced pixels in the reduced image. It is possible to satisfactorily prevent the loss of the image information, and furthermore, the image signal of the pixel of interest and its surrounding eight pixels and the reduced image signals of a plurality of reduced pixels in the vicinity of the pixel of interest are further reduced. If the pattern does not conform to the reduction processing using the predetermined filtering coefficient, a reduced image signal having a value different from the reduced image signal formed by the reduction processing using the predetermined filtering coefficient is output. It is possible to satisfactorily obtain a reduced image that reflects the contents of the original image even for an image in which the contents of the original image are not reflected in the reduced image using the filtering coefficient of The ability.

[Brief description of the drawings]

FIG. 1 is a block diagram of a reduction circuit to which the present invention is applied, FIG. 2 is a diagram showing coefficients of a low-pass filter, FIG. 3 is a block diagram of an embodiment of the low-pass filter, FIG. FIG. 5 is an explanatory diagram of an image attribute detecting circuit, FIG. 6 is a diagram for explaining an image signal input to a compulsory circuit, and FIGS. 7, 8, and 9 explain the contents of a correction table. FIG. 10 is a block diagram when a reduction circuit is applied to hierarchical coding, FIG. 11 is a block diagram of a reference pixel determination circuit, FIG. 12 is an explanatory diagram of reference pixels on a code plane, and FIG. FIG. 13 is an explanatory diagram of a reference pixel of an image one stage before, FIG. 14 is a block diagram of a circuit for dynamically changing Sekw Value Q, FIG. 15 is a diagram showing an encoder of an arithmetic code, and FIG. FIG. 17 is a diagram showing a decoder for calculating codes, FIG. 17 is a block diagram of the decoder, and FIG. FIG. 19 is a diagram showing another embodiment for dynamically changing Q, and FIG. 20 is an example of reference pixels at each stage in hierarchical coding. FIG. 21, FIG. 21 shows an example of a table for determining arithmetic code parameters, FIG. 22 shows an example of a table used in the third embodiment, and FIG. 23 shows an example of a filter used in a reduction circuit. FIGS. 24 and 25 are block diagrams showing another example of the structure of the reduction circuit. 2... Filtering circuit, 3... Comparator, 4... Sub-sampling circuit, 5. Detection circuits, 6a to 6c... Correction circuits, 7, 8.

──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Tadashi Yoshida 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. (56) References JP-A-64-57880 (JP, A) (58) Survey Field (Int.Cl. ⁶ , DB name) H04N 1/393 G06T 3/40

Claims (2)

(57) [Claims] An image signal reducing device for outputting a reduced image signal representing a reduced image obtained by reducing an original image by half in each of a main scanning direction and a sub-scanning direction from an image signal representing the original image is to be reduced. Input means for inputting an image signal representing an original image; and reducing and forming the reduced image signal by reducing the image signal input by the input means by half in each of the main scanning and sub-scanning directions. Forming means, the forming means comprising: a plurality of pixel image signals defined by the following (a) to (c): (a) an image signal in the original image to be reduced input by the input means; The image signal of the pixel of interest X (i, j); (b) the pixel of interest X (i, j,
j) eight pixels X (i-1, j-1), X (i-1, j), X
(I−1, i + 1), X (i, j−1), X (i, j + 1), X (i +
1, j-1), X (i + 1, j), X (i + 1, j + 1) image signals, and (c) the forming means halves the image signals in the main scanning direction and the sub-scanning direction, respectively. By performing a reduction process using a predetermined filtering coefficient on each of the reduced image signals of a plurality of reduced pixels near the target pixel X (i, j) formed by the reduction process, the target pixel X (i, j) is obtained. j) forming and outputting a reduced image signal corresponding to (j), wherein the pattern of the image signal of a plurality of pixels defined in (a) to (c) is incompatible with the reduction processing using the predetermined filtering coefficient. In this case, the image signal reduction device outputs a reduced image signal having a value different from a reduced image signal formed by the reduction process using the predetermined filtering coefficient. 2. A reduced image obtained by reducing an image signal representing an original image by half in each of the main scanning and sub-scanning directions, thereby reducing the original image by half in each of the main scanning and sub-scanning directions. And a method for reducing an image signal that outputs a reduced image signal representing: (a) an image signal of a plurality of pixels defined by the following (a) to (c): (a) a pixel of interest in an original image to be reduced X (i, j) image signal, (b) 8 pixels X around target pixel X (i, j) in original image
(I−1, j−1), X (i−1, i), X (i−1, j + 1), X
(I, j-1), X (i, j + 1), X (i + 1, j-1), X (i +
(J), X (i + 1, j + 1) image signals and (c) an image signal formed by reducing the image signal representing the original image by half in the main scanning direction and the sub-scanning direction, respectively. By performing a reduction process using a predetermined filtering coefficient on each of the reduced image signals of the plurality of reduced pixels near the pixel X (i, j), a reduced image signal corresponding to the target pixel X (i, j) is obtained. When the pattern of the image signal of a plurality of pixels defined in the above (a) to (c) is incompatible with the reduction processing using the predetermined filtering coefficient, the predetermined filtering coefficient And outputting a reduced image signal having a value different from the reduced image signal formed by the reduction process using the image signal.