JP2938152B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial application field) The present invention is configured using a semiconductor wafer which requires first and second semiconductor layers joined via an insulating film. The present invention relates to a semiconductor device in which an element is formed on at least one semiconductor layer and a method for manufacturing the same.

(Prior Art) In a normal semiconductor device using a silicon wafer, an electrical connection with the outside is taken on one plane. On the contrary,
It may be necessary to take out the electrodes from the back surface of the element mainly due to mounting requirements. For example, using a so-called bonded silicon wafer composed of first and second silicon layers joined via an insulating film, a diffusion layer of an element formed on the first silicon layer side is used as a second silicon layer. It may be taken out through a penetrating connection hole. One example is a chemical sensor (see Japanese Patent Application No. 63-78715). In this structure, a contact hole is formed in the second silicon layer, and the element diffusion layer of the first silicon layer is exposed at the bottom of the contact hole to form a contact portion. For this purpose, the element diffusion layer of the first silicon layer is exposed at the bottom of the connection hole formed in the second silicon layer, and the side wall of the connection hole formed in the first silicon layer is insulated. It is necessary to cover with a membrane.

However, when the second silicon layer is thick, it is not easy to adopt such an electrode extraction structure. That is, in order to open a contact hole in the second silicon layer, expose the contact portion at the bottom of the contact hole, and selectively cover the side wall of the contact hole with the insulating film, it is necessary to form the contact hole around the contact hole having an extremely large step. Need PEP. In the usual spin coating of a photoresist, it is difficult to avoid disconnection at a step portion, which causes a decrease in reliability such as poor insulation at an edge portion of a contact hole. To avoid this, it is conceivable to round the corners of the connection holes or increase the inclination of the connection holes. However, this method is not preferable because the opening area of the connection hole is unnecessarily large.

(Problems to be Solved by the Invention) As described above, an electrode is provided to a diffusion layer of an element formed in one silicon layer using a bonded wafer through a connection hole formed in the other silicon layer. In this case, there is a problem that it is difficult to take out the electrode with a small connection hole area with high reliability.

An object of the present invention is to provide a semiconductor device which solves such a problem and a method for manufacturing the same.

[Structure of the Invention] (Means for Solving the Problems) In a semiconductor device according to the present invention, a semiconductor wafer in which first and second semiconductor layers are joined with an insulating film interposed therebetween is used. And an element including an enlarged layer formed in the first semiconductor layer, and connected to an element diffusion layer on the first semiconductor layer side through a connection hole provided through the second semiconductor layer. And a contact portion of the electrode to the element diffusion layer is opened in self-alignment with the connection hole, and an inner wall of the connection hole is covered with an anodic oxide film.

The present invention also relates to a method for manufacturing such a semiconductor device, comprising: a diffusion layer on at least a first semiconductor layer side of a semiconductor wafer in which first and second semiconductor layers are joined via an insulating film therebetween. Forming an element including: a step of penetrating the second semiconductor layer and forming a connection hole for the element diffusion layer on the first semiconductor layer side; and forming all of the insulating film at the bottom of the connection hole. Forming a contact portion to the element diffusion layer of the first semiconductor layer in a state of being self-aligned with the connection hole by etching and removing the contact portion by anodizing an exposed portion of the first semiconductor layer; Covering the inner wall of the connection hole with an oxide film while exposing the element diffusion layer, and arranging an electrode connected to the element diffusion layer on the first semiconductor layer side via the connection hole. It is characterized by having.

(Action) According to the present invention, by utilizing anodic oxidation,
Without using the PEP process, the side wall of the connection hole is covered with an insulating film, and a state where the contact portion at the bottom of the connection hole is exposed can be obtained. In addition, since PEP is not required on the side wall and bottom of the connection hole, the side wall of the connection hole may be substantially vertical. Therefore, the electrode can be taken out from the back surface with a small area which has not existed conventionally and without insulation failure.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 shows a field-effect type chemical sensor according to one embodiment,
2 (a) to 2 (f) are manufacturing process diagrams. This will be described in accordance with a manufacturing process. A wafer is prepared in which a first silicon layer 1 and a second silicon layer 2 are joined via an oxide film 3 (FIG. 2A). For example, two mirror-polished silicon substrates are brought into contact with each other in a state where an oxide film of about 500 nm is formed on their surfaces, and directly bonded by heat treatment at 1100 ° C. for 2 hours in a nitrogen atmosphere. can get. In this embodiment, the first silicon layer 1 is a sensor FET.
The p ^- type silicon layer in the formation region is adjusted to have a thickness of, for example, about 10 μm after bonding. Thereafter, the first silicon layer 1 is removed by etching while leaving the element region in an island shape. In the second silicon layer 2, connection holes 4 (4 ₁ , 4 ₂ ) for source and drain diffusion layers formed later in the first silicon layer 1 are formed by anisotropic etching (FIG. 2 ( b)). The etching of the connection hole 4 is performed until the connection hole 4 is automatically stopped at the oxide film 3 at the interface. The size of the connection hole 4 is, for example, about 100 μm square at the bottom contact portion. The size of the contact portion can be reduced as much as possible within the range of the contact resistance allowed for the element.

Subsequently, after an oxide film 5 is formed on the entire exposed surfaces of the first and second silicon layers 1 and 2, the oxide films 3 and 5 on the second silicon layer 2 side are formed.
And the source of the oxide film 5 on the first silicon layer 1 side,
The portion of the drain formation region is removed by etching. Thereby, the side wall and the bottom of the connection hole 4 are exposed. In this state, the n-type diffusion layers 7 (7 ₁ , 7 ₂ ) serving as a source and a drain are formed in the first silicon layer 1 by impurity diffusion from both surfaces.
Is formed (FIG. 1 (c)). Note that n through the connection hole 4
The n-type diffusion layer 8 is also formed in the second silicon layer 2 by the type impurity diffusion. Thereafter, an oxide film 5 is formed again on the entire exposed surfaces of the first and second silicon layers 1 and 2. Then, at least on the first silicon layer 1 side, a silicon nitride film 6 is formed as an ion-sensitive film. Thereafter, the oxide films 3, 5 on the second silicon layer 2 side are removed by etching using ammonium fluoride or the like (FIG. 2 (d)). As described above, the sensor FET is configured on the first silicon layer 1 side.

Thereafter, the surface of the second silicon layer 2 is anodized and covered with an oxide film 9 (FIG. 2E). In the anodic oxidation step, for example, an electrode is formed on a part of the second silicon layer 2 or conduction is simply established by using a conductive clip or the like, and electrolysis is performed using a platinum electrode as a counter electrode. The electrolyte is NMA
(N-methyl-acetamide), THF (tetrahydrofluoroalcohol), ethylene glycol to which KNO ₃ is added, or the like is used. By this anodic oxidation, as shown in FIG. 2E, the oxide film 9 is selectively formed only on the second silicon layer 2 side.
Is formed, that is, the side wall of the contact hole 4 is covered with the oxide film 9 and the surface of the n-type diffusion layer 7 in the contact portion is exposed, automatically without using PEP. In the anodic oxidation step, the n-type diffusion layer 8 formed on the surface of the second silicon layer 2 works effectively in lowering the electrode resistance.

Thereafter, electrodes 10 (10 ₁ , 10 ₂ ) connected to the source / drain diffusion layers 7 are formed by depositing and patterning the Au / Ti film against the connection holes 4 (FIG. 2 (f)). Electrode 10
May be another metal or a polycrystalline silicon film.

Thus, according to this embodiment, the source and drain electrodes from the back surface of the sensor FET can be formed with the minimum area required for low contact resistance and with sufficient insulation for the second silicon layer. .

By the way, the electrode which contacts the source diffusion layer of the FET is usually simultaneously contacted with the substrate region. An embodiment of a chemical sensor having such a contact structure will be described below.

3 (a) to 3 (c) are manufacturing process diagrams. Parts corresponding to those in the previous embodiment are denoted by the same reference numerals, and detailed description is omitted. As shown in FIG. 3A, an island-shaped patterned first silicon layer 1 is formed on a bonded silicon wafer, a connection hole 4 is formed in a second silicon layer 2, and impurities from both sides are formed. A diffusion layer 7 is formed in the first silicon layer 1 by diffusion. Up to this point, it is basically the same as the previous embodiment. Thereafter, the second silicon layer 2 is electrolytically etched to retreat the inner wall of the connection hole 4 (FIG. 3B). At this time, as shown in the figure, by performing electrolytic etching while leaving the mask 11 used for forming the connection hole 4, the wall surface of the connection hole 4 is receded without reducing the thickness of the second silicon layer 2. Can be done. In particular, even if a diffusion mask is not provided on the second silicon layer 2 side and the entire surface is diffused, the reduction in substrate thickness due to electrolytic etching is several tens of degrees.
It is only about μm, and there is no practical problem. In this manner, a new region of the first silicon layer 1 is exposed at the bottom of the connection hole 4, and the p-type diffusion layer 12 is formed there. At this time, by making the surface concentration of the p-type diffusion layer 12 lower than that of the n-type diffusion layer 7, the p-type diffusion layer 12 can be formed so as to surround the n-type diffusion layer 7. Thereafter, a gate insulating film is formed on the first silicon layer 1 side in the same manner as in the previous embodiment, and an oxide film 9 is selectively formed on the surface of the second silicon layer 2 by anodic oxidation. 7 and an electrode 10 which contacts the p-type diffusion layer 12 are formed (FIG. 3C).

The p-type diffusion layer 12 does not need to be provided if a sufficient contact can be obtained without the p-type diffusion layer 12, or may be formed in advance, for example, before bonding, instead of diffusion through an enlarged connection hole.

FIG. 4 shows the structure of still another embodiment. In this embodiment, the connection holes 4 formed in the first silicon layer 2 are formed with substantially vertical side walls. Others are the same as the previous embodiment. The present invention enables selective insulation of the inner wall even with such a connection hole having a vertical side wall. Thereby, the area of the connection portion can be further reduced.
The electrode 10 does not necessarily have to be along the inner wall of the connection hole as in the previous embodiment, but may be embedded in the connection hole 4 as in this embodiment.

The present invention is not limited to the above embodiment. For example, in the embodiment, the chemical sensor having the FET structure is described. However, the present invention can be similarly applied to a case where another element is formed on the first silicon layer and an electrode is taken out from the second silicon layer side. . An element may also be provided on the second silicon layer side.
Furthermore, it is also possible to use pin grid array connection terminals as connection electrodes.

[Effects of the Invention] As described above, according to the present invention, when a connection hole is opened from the back surface and an electrode is taken out using a wafer having a laminated structure, the entire bottom surface of the connection hole is used as a contact portion. It is possible to provide a semiconductor device in which a highly reliable electrode is taken out with a small area.

[Brief description of the drawings]

FIG. 1 is a diagram showing an FET type chemical sensor according to one embodiment of the present invention, FIGS. 2 (a) to (f) are diagrams showing the manufacturing steps, and FIGS. 3 (a) to (c) are other diagrams. FIG. 4 is a view showing a manufacturing process of the chemical sensor of the embodiment. FIG. 4 is a view showing a FET type chemical sensor of still another embodiment. 1... First silicon layer, 2... Second silicon layer, 3
... oxide film, 4 ... connection hole, 5 ... oxide film, 6 ... silicon nitride film, 7 ... source / drain n-type diffusion layer, 8 ...
... n-type diffusion layer, 9 ... anodized film, 10 ... electrodes.

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int.Cl. ⁶ , DB name) H01L 21/28

Claims (2)

(57) [Claims] A semiconductor wafer having first and second semiconductor layers joined to each other with an insulating film interposed therebetween, and an element including an enlarged layer formed on at least the first semiconductor layer of the semiconductor wafer; An electrode connected to an element diffusion layer on the first semiconductor layer side through a connection hole provided through the second semiconductor layer; and a contact portion of the electrode with respect to the element diffusion layer is provided. The semiconductor device according to claim 1, wherein the opening is self-aligned with the connection hole, and an inner wall of the connection hole is covered with an anodic oxide film. A step of forming an element including a diffusion layer on at least a first semiconductor layer side of a semiconductor wafer in which the first and second semiconductor layers are joined via an insulating film therebetween; Forming a connection hole for the element diffusion layer on the side of the first semiconductor layer through the semiconductor layer; and removing all the insulating film at the bottom of the connection hole by etching to be self-aligned with the connection hole. Forming a contact portion for the device diffusion layer of the first semiconductor layer at the step of: anodizing an exposed portion of the first semiconductor layer to expose the device diffusion layer of the contact portion; And a step of disposing an electrode connected to the element diffusion layer on the first semiconductor layer side via the connection hole.