JP2937943B2 - Logic synthesis system and logic synthesis method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic synthesis system and a logic synthesis method for generating a circuit from a language-based circuit description, and more particularly to the optimization of the logic synthesis process and the utilization of the optimization result. Regarding improvement.

[0002]

2. Description of the Related Art FIG. 6 is a block diagram of a conventional logic synthesis system, which comprises a Boolean expression extraction unit 1, an optimization processing unit 2, and an optimization database 3. Conventionally, the Boolean expression extraction unit 1 has a circuit to be synthesized (for example, RTL (register-transisto)
r logic)) is read, and a Boolean expression composed of AND / OR is extracted. The optimization processing unit 2 accepts the design conditions as constraints 5 in order to generate a circuit that meets the design conditions such as the semiconductor device to be used, the area desired by the designer, and the operation timing, and performs extraction under the constraints. Optimization processing such as logical compression or logical expansion is performed on the Boolean expression thus generated, and a circuit is generated in the form of a netlist 6 output.

[0003]

However, conventionally, the logic designed in the past is held on a drawing basis,
Although there were systems that could use it, even if it was logically equivalent, the retained logic could not be used if the design target (LSI, board, etc.) was different.

It is also desirable to make the design data into a database so that the results of past optimization can be used more versatilely.

The present invention has been made to solve the above problems, and an object of the present invention is to improve the efficiency of optimization processing during logic synthesis by improving the usability of accumulated optimization results. It is an object of the present invention to provide a logic synthesis system and a logic synthesis method.

[0006]

In order to achieve the above object, a logic synthesis system according to a first aspect of the present invention performs optimization based on a circuit description for generating a circuit to be synthesized. In a logic synthesis system for generating a circuit, a Boolean expression extracting means for extracting a Boolean expression from the circuit description, and analyzing constraint information on an entire synthesis target such as an operation timing and an area in a logic synthesis optimization process, and analyzing the entire synthesis target Constraint information classifying means for classifying into total constraint information extending to a specific portion of a circuit and individual constraint information extending only to a specific portion of a circuit; Optimization processing means, and individual optimization for optimizing the output after performing the optimization by the overall optimization processing means based on the individual constraint information And an optimization database that holds the result of the optimization performed by the overall optimization processing means in the form of a Boolean expression. The overall optimization processing means includes a Boolean expression extracted by the Boolean expression extraction means. If the optimization result corresponding to the expression exists in the optimization database, the optimization result is used.

In a logic synthesis system according to a second aspect, in the first aspect, the overall optimization processing means optimizes when there is no optimization result corresponding to the Boolean expression extracted by the Boolean expression extraction means. And stores the result of the optimization in the optimization database.

[0008] In a logic synthesis system according to a third invention, in the first invention, the overall optimization processing means includes a one-bit Boolean expression when the Boolean expression extracted by the Boolean expression extraction means is vectorized. A Boolean expression conversion unit for converting into an expression, and a Boolean expression restoring unit for returning the output after the optimization performed by the overall optimization processing unit to the original bit width and sending it to the individual optimization processing unit. .

A logic synthesis system according to a fourth invention is the logic synthesis system according to the first invention, wherein the optimization database is a shared database.

[0010] A logic synthesis system according to a fifth invention is the logic synthesis system according to the first or fourth invention, wherein the optimized database can be accessed via a network.

A logic synthesis method according to a sixth aspect of the present invention is a logic synthesis method for generating a circuit by optimizing based on a circuit description for generating a circuit to be synthesized, wherein a Boolean expression is extracted from the circuit description. Boolean expression extraction step and analysis of constraint information for the entire synthesis target such as operation timing and area in the logic synthesis optimization process, and total constraint information for the entire synthesis target and individual constraint information for only a specific part of the circuit Constraint information classifying step, optimizing the Boolean expression extracted by the Boolean expression extracting step based on the overall constraint information, and performing the overall optimizing step based on the individual constraint information. Individual optimization step of optimizing the subsequent output.

According to a seventh aspect of the present invention, in the logic synthesis method according to the sixth aspect, the overall optimizing step holds the result of the new optimization in the form of a Boolean expression and performs the optimization processing performed thereafter. The retained optimization result is diverted.

[0013]

Preferred embodiments of the present invention will be described below with reference to the drawings.

Embodiment 1 FIG. 1 is a block diagram showing a first embodiment of a logic synthesis system according to the present invention. The Boolean expression extraction unit 11 is a Boolean expression extraction unit that extracts a Boolean expression from a circuit description. In the present embodiment, a Boolean expression is extracted based on the RTL circuit description 12, but the function processing of the Boolean expression extraction unit 11 may be the same as in the related art. When the Boolean expression extracted by the Boolean expression extraction unit 11 is vectorized, the Boolean expression conversion unit 13 converts the Boolean expression into a 1-bit Boolean expression. The constraint information classifying unit 14 is a constraint information classifying unit that analyzes designated constraint information and classifies the analyzed constraint information into total constraint information covering the entire synthesis target and individual constraint information covering only a specific portion of the circuit. The constraint information includes a constraint condition 15 on the entire synthesis target, such as an operation timing and an area in the logic synthesis optimization process. In the present embodiment, the entire constraint information and the individual constraint information are output to files 16 and 17, respectively. The overall optimization processing unit 18 optimizes the Boolean expression extracted by the Boolean expression extraction unit 11 based on the overall constraint information. In the present embodiment, optimization is performed on the data converted to the 1-bit Boolean expression by the Boolean expression conversion unit 13. Further, the overall optimization processing unit 18 accumulates the optimization result in the form of a Boolean expression in the optimization database 19 as necessary, and stores the optimization result corresponding to the Boolean expression to be subjected to logic synthesis in the optimization database. If it exists in 19, it is used for optimization. The Boolean expression restoring unit 20 is a Boolean expression restoring unit that returns the output after the optimization performed by the overall optimization processing unit 18 to the original bit width. In the present embodiment, the Boolean expression conversion unit 13, the overall optimization processing unit 18, and the Boolean expression restoration unit 20 constitute an overall optimization processing unit. The individual optimization processing unit 21 is an individual optimization processing unit that optimizes the output after the optimization performed by the overall optimization processing unit 18 based on the individual constraint information. In the present embodiment, the Boolean expression restored by the Boolean expression restoring unit 20 is optimized.

Next, the operation of this embodiment will be described with reference to the flowcharts shown in FIGS.

The Boolean expression extraction unit 11 reads the RTL circuit description 12, and extracts a Boolean expression constituting a combinational circuit surrounded by registers and input / output ports (step 101). FIG. 4A shows an example of an extracted Boolean expression (Boolean expression) in which the Boolean expression is a vector expression. When the Boolean expression is vectorized as in the example of FIG. 4A (Step 102), the Boolean expression conversion unit 13 converts the Boolean expression into a 1-bit Boolean expression (Step 103). FIG. 4 shows an example of a 1-bit Boolean expression after conversion.
(B). As described above, according to the present embodiment, the Boolean expression conversion unit 13 is provided to convert the Boolean expression to the 1-bit Boolean expression before performing the optimization. Even in a different case, general-purpose optimization independent of the bit width can be performed.

On the other hand, the constraint information classifying unit 14
5 is read and whether the constraint condition is a constraint that covers the entire circuit,
Analyze the constraints on a specific part of the circuit, such as speeding up a specific path.Constraints for the entire circuit are used as overall constraint information, and constraints for only a specific part of the circuit are Overall constraint information file 16 or individual constraint information file 17 as individual constraint information
(Step 100).

Next, the overall optimization processing unit 18 converts the Boolean expression extracted by the Boolean expression extraction unit 11 based on the overall constraint information classified by the constraint information classifying unit 14 (or a 1-bit Boolean expression by the Boolean expression conversion unit 13). The conversion is performed by the Boolean expression extraction unit 11 and the constraint information classification unit 14 can be executed in parallel, and both processes are performed by the overall optimization processing unit. It is sufficient that the processing is completed before the optimization processing by. The optimization process (overall optimization process) of step 104 performed by the overall optimization processing unit 18 will be described with reference to the flowchart shown in FIG.

Upon receiving the Boolean expression extracted by the Boolean expression extraction unit 11 through the Boolean expression conversion unit 13 (step 201), the overall optimization processing unit 18 determines the area, operation timing, and technology used for the entire circuit. The optimization database 19 is searched to check whether the same optimization has been performed in the past with respect to the Boolean expression to be synthesized by using the key as a key (step 202). As a result of the search, if there is a corresponding optimization, that is, an optimized circuit, the optimization circuit is diverted, and the circuit in the Boolean expression received by the optimization circuit is replaced (steps 203 and 204). That is, the optimization circuit is a result of the overall optimization process. On the other hand, if there is no optimization circuit, optimization is performed as usual (step 205).
The result is registered in the optimization database 19 (step 206).

As described above, according to the present embodiment, by diverting the results of the optimization performed in the past, it is possible to omit the execution of the optimization requiring a long time, and to shorten the optimization processing. Can be planned. In addition, the fact that the results of optimization performed in the past cannot be used means that this combinational circuit is new, and by registering and accumulating the results of the new optimization, future optimization will be performed. Efficiency can be improved.

When the Boolean expression converting unit 13 converts the Boolean expression into a 1-bit Boolean expression,
Bit expansion is performed to restore the original Boolean expression (steps 105 and 106).

Then, the individual optimization processing unit 21 outputs the output after optimization performed by the overall optimization processing unit 18 (or the original Boolean expression restored by the Boolean expression restoration unit 20) based on the individual constraint information. Then, optimization is performed (step 107). As a result, the net list 22 is output.

As described above, in the present embodiment,
The constraint conditions 15 relating to logic synthesis are classified into total constraint information covering the entire circuit and individual constraint information covering only a specific location.
Two phases of optimization are performed for each of them. Of the two phases, the overall optimization processing based on the overall constraint information is performed first, thereby giving priority to versatility. In particular, in the present embodiment, the optimization database 19 used in this overall optimization process
Since the optimization circuit is registered in the form of a Boolean expression, the optimization database 19 can be used irrespective of the logic synthesis target such as an LSI or a board. Further, as described above, in the present embodiment, when the Boolean expression is vectorized, it is converted to a 1-bit Boolean expression, so that the operation function is the same but the bit width of the bus differs depending on the model. Even in such cases, general-purpose optimization can be performed regardless of the model. Also, the optimization database 19 is converted into a 1-bit Boolean expression.
, Only one optimization circuit needs to be registered for a common function of the circuits.
As a result, it is possible to reduce the used capacity of the optimization database 19.

Embodiment 2 FIG. In the first embodiment, the optimization processing is realized in a closed environment. However, the present embodiment is characterized in that the optimization database 19 is a shared database. As a result, even if optimization is performed for the first time on a circuit description, if another person has performed optimization on the same circuit description in the past,
Since the results of past optimization stored in the shared optimization database 19 can be used, efficient optimization processing can be performed.

FIG. 5 is an overall configuration diagram showing a second embodiment of the logic synthesis system according to the present invention. Each of the workstations 23 and 24 has a configuration other than the optimization database 19 in the logic synthesis system shown in FIG. The database server 25 is equipped with an optimization database 19 constructed to be sharable by a plurality of users. The network 26 connects the workstations 23 and 24 to the database server 25.

In the above configuration, by accessing the optimization database 19 via the network 26 from each of the workstations 23 and 24, not only the same processing as in the first embodiment can be performed, but also By performing the optimization described above, the accumulated optimization circuit can be used. The operation according to the present embodiment includes a search process of the optimization database 19 shown in FIG. 3 (step 202), a process of reading the optimization circuit from the optimization database 19 (step 204), and a process of reading the optimization database 19. Registration of optimization results (step 2
Embodiment 1 except that (06) is access to the database server 25 via the network 26.
Therefore, detailed description is omitted.

As described above, in the present embodiment, the same effects as those of the first embodiment can be obtained even through the network 26. In addition, by sharing the optimization database 19, even when logic synthesis (optimization) is performed for the circuit description 12 for the first time, the result of optimization performed by another person can be diverted. Implementation time can be reduced. Of course, it is possible to share the optimization database 19 without using a network, and such a system configuration is also within the scope of the present invention.

[0028]

According to the present invention, it is possible to reduce the time required for the optimization process by omitting the execution of the time-consuming optimization by diverting the results of the optimization performed in the past. it can.

Further, when optimization is performed, the results of the optimization are registered and accumulated, so that the efficiency of future optimization can be improved.

Also, since a Boolean expression conversion means is provided to convert the data to a 1-bit Boolean expression before performing the optimization, even if the operation function is the same but the bit width of the bus differs depending on the model, the model can be converted to the model. It is possible to perform independent general-purpose optimization. Of course, since the Boolean expression restoring means is provided to restore the original 1-bit Boolean expression, there is no problem in the subsequent processing.

Further, by sharing the optimization database, even if the optimization is performed for the first time on the circuit description, if another person performs the optimization on the same circuit description as the circuit description, the optimization is shared. Since the results of optimization performed by others stored in the optimized database can be used, efficient optimization processing can be performed.

Further, even when the optimization database is accessed via a network, the same effects as described above can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a logic synthesis system according to the present invention.

FIG. 2 is a flowchart showing an operation in the first embodiment.

FIG. 3 is a flowchart showing overall optimization processing according to the first embodiment.

FIG. 4A is a diagram illustrating an example of a Boolean expression extracted in the first embodiment, and FIG. 4B is a diagram illustrating an example of a Boolean expression after conversion to a 1-bit Boolean expression.

FIG. 5 is an overall configuration diagram showing a second embodiment of the logic synthesis system according to the present invention.

FIG. 6 is a block diagram of a conventional logic synthesis system.

[Explanation of symbols]

11 Boolean expression extraction unit, 12 circuit description, 13 Boolean expression conversion unit, 14 constraint information classification unit, 15 constraint condition,
16 overall constraint information file, 17 individual constraint information file, 18 overall optimization processing section, 19 optimization database, 20 Boolean expression restoring section, 21 individual optimization processing section, 22 netlist, 23, 24 workstation, 25 database server , 26 networks.

Claims (7)

(57) [Claims] 1. A logic synthesis system that generates a circuit by optimizing based on a circuit description for generating a circuit to be synthesized, comprising: a Boolean expression extraction unit that extracts a Boolean expression from the circuit description; Constraint information classifying means for analyzing constraint information for the entire synthesis target such as operation timing and area in the optimization process of the optimization process and classifying the constraint information into the entire constraint information covering the entire synthesis target and the individual constraint information covering only a specific portion of the circuit; An overall optimization processing unit that optimizes the Boolean expression extracted by the Boolean expression extraction unit based on the overall constraint information; and an output after the optimization performed by the overall optimization processing unit based on the individual constraint information. Individual optimization processing means for optimizing the data, and the result after the optimization performed by the overall optimization processing means is stored in the form of a Boolean expression. The overall optimization processing means, if an optimization result corresponding to the Boolean expression extracted by the Boolean expression extraction means exists in the optimization database, the optimization result A logic synthesis system characterized by being diverted. 2. The overall optimization processing means performs optimization when there is no optimization result corresponding to the Boolean expression extracted by the Boolean expression extraction means, and accumulates the optimization result in the optimization database. The logic synthesis system according to claim 1, wherein the logic synthesis is performed. 3. The global optimization processing unit: a Boolean expression conversion unit that converts a Boolean expression extracted by the Boolean expression extraction unit into a 1-bit Boolean expression when the Boolean expression is vectorized; 2. The logic synthesis system according to claim 1, further comprising: a Boolean expression restoring unit that returns an output after optimization performed by the unit to an original Boolean expression of a bit width and sends the Boolean expression to the individual optimization processing unit. 4. The logic synthesis system according to claim 1, wherein said optimization database is a shared database. 5. The logic synthesis system according to claim 1, wherein access to the optimization database via a network is enabled. 6. A logic synthesis method for generating a circuit by optimizing based on a circuit description for generating a circuit to be synthesized, comprising: a Boolean expression extraction step of extracting a Boolean expression from the circuit description; A constraint information classifying step of analyzing constraint information for the entire synthesis target such as operation timing and area in the optimization processing of the optimization process and classifying the constraint information into the entire constraint information covering the entire synthesis target and the individual constraint information covering only a specific portion of the circuit; An overall optimization step of optimizing the Boolean expression extracted by the Boolean expression extraction step based on the overall constraint information, and optimizing an output after performing the overall optimization step based on the individual constraint information. And a separate optimization step to be performed. 7. The overall optimization step is characterized in that a result of a new optimization is held in the form of a Boolean expression, and the held result of the optimization is used in a subsequent optimization process. The logic synthesis method according to claim 6.