JP2935286B2 - Packaging case - Google Patents

Packaging case

Info

Publication number
JP2935286B2
JP2935286B2 JP10297591A JP10297591A JP2935286B2 JP 2935286 B2 JP2935286 B2 JP 2935286B2 JP 10297591 A JP10297591 A JP 10297591A JP 10297591 A JP10297591 A JP 10297591A JP 2935286 B2 JP2935286 B2 JP 2935286B2
Authority
JP
Japan
Prior art keywords
chip
carrier
element chip
receiving element
protection space
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP10297591A
Other languages
Japanese (ja)
Other versions
JPH04334038A (en
Inventor
信子 小松
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP10297591A priority Critical patent/JP2935286B2/en
Publication of JPH04334038A publication Critical patent/JPH04334038A/en
Application granted granted Critical
Publication of JP2935286B2 publication Critical patent/JP2935286B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Wire Bonding (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は光半導体素子チップオン
キャリアの包装ケースに関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an optical semiconductor device chip-on-carrier packaging case.

【0002】[0002]

【従来の技術】従来の包装ケースは、図3に示すよう
に、受け皿1(図3(a))と、受け皿1に着脱自在の
包装蓋4(図3(b))とから成る。受け皿1は、その
底部に、四角い窪みで成る受光素子チップオンキャリア
収納スペース2がマトリクス状に形成されている。包装
蓋4には、受光素子チップオンキャリア収納スペースに
対応する位置にチップ保護スペース6と、ボンディング
ワイヤ保護スペース5が形成されている。
2. Description of the Related Art As shown in FIG. 3, a conventional packaging case includes a tray 1 (FIG. 3A) and a packaging lid 4 (FIG. 3B) which is detachable from the tray 1. The receiving tray 1 has a light receiving element chip-on-carrier storage space 2 formed of a square depression formed in a matrix at the bottom. A chip protection space 6 and a bonding wire protection space 5 are formed in the packaging lid 4 at positions corresponding to the light receiving element chip on carrier storage space.

【0003】[0003]

【発明が解決しようとする課題】この従来の包装ケース
では、図3(b)に示すように、ボンディングワイヤの
保護スペース(溝)5がチップ保護スペース6の片側に
しかとられていないため、図4に示すように、受光素子
チップオンキャリア7を上下逆さに収納(図4の左側が
正しい収納、右側が誤った収納)してしまうと、受光素
子チップに接続したボンディングワイヤ9をつぶしてし
まったり、または切断してしまうという問題点があっ
た。
In this conventional packaging case, as shown in FIG. 3 (b), a bonding wire protection space (groove) 5 is provided only on one side of the chip protection space 6. As shown in FIG. 4, if the light-receiving element chip-on carrier 7 is stored upside down (the left side in FIG. 4 is correctly stored, and the right side is wrongly stored), the bonding wire 9 connected to the light-receiving element chip is crushed. There was a problem that it was rolled or cut.

【0004】[0004]

【課題を解決するための手段】本発明の包装ケースは、
ボンディングワイヤの保護スペースをチップ保護スペー
スの両側に延ばして設けた包装蓋(縦の溝を設けた蓋)
を有している。このためチップオンキャリアを上下逆さ
に収納してしまってもボンディングワイヤをつぶした
り、切断してしまうおそれがない。
The packaging case of the present invention comprises:
Packaging lid with bonding wire protection space extending on both sides of chip protection space (lid with vertical groove)
have. Therefore, even if the chip-on-carrier is stored upside down, there is no possibility that the bonding wire will be crushed or cut.

【0005】[0005]

【実施例】本発明の一実施例について図面を参照して説
明する。
An embodiment of the present invention will be described with reference to the drawings.

【0006】図1(a),(b)に一実施例の包装ケー
スの平面図を示す。包装ケースは、図示の如く、受光素
子チップオンキャリア受け皿1(図1(a))と、受け
皿1に着脱自在な包装蓋4(図1(b))とから成る。
受け皿1は従来例と同じく、底部に受光素子チップオン
キャリアと相似形の窪みで成る受光素子チップオンキャ
リア収納スペースがマトリックス状に多数形成されてい
る。包装蓋4には、蓋の内側で受光素子チップオンキャ
リア収納スペースに対応する位置に、溝が縦横に形成さ
れている。この溝のうち、図中横に延びる溝がチップ保
護スペース6となり、この溝に直交して図中縦に延びる
溝がボンディングワイヤ保護スペース5となる。
FIGS. 1A and 1B are plan views of a packaging case according to an embodiment. As shown, the packaging case includes a light receiving element chip-on-carrier tray 1 (FIG. 1 (a)) and a packaging lid 4 (FIG. 1 (b)) which is detachable from the tray 1.
As in the prior art, the receiving tray 1 has a large number of light receiving element chip-on-carrier storage spaces formed in the bottom thereof in the form of a matrix, each having a recess similar to the light-receiving element chip-on-carrier. Grooves are formed in the packaging lid 4 vertically and horizontally at positions corresponding to the light receiving element chip-on-carrier storage space inside the lid. Of these grooves, a groove extending horizontally in the figure becomes a chip protection space 6, and a groove extending perpendicularly to the groove and extending vertically in the figure becomes a bonding wire protection space 5.

【0007】図2に示すように、受け皿1に、普及型の
受光素子チップオンキャリア7を収納する。この時、受
け皿1の収納スペースは四角い窪みとなっており、直方
体の受光素子チップオンキャリア7は、どちら向きに収
納してもかまわない。この受け皿に包装蓋4をかぶせ
る。この時はこの実施例にあるように左上の切り込み3
を合わせ、静かに蓋をするだけでよい。図1(b)、図
2に示すとおり、ボンディングワイヤの保護スペース5
はチップ保護スペースの両側に(縦の溝状に)設けてあ
るので受光素子チップオンキャリア7を向きを逆に入れ
たとしても受光素子チップ8に接続したボンディングワ
イヤ9をつぶしたり、切断したりしてしまうことはな
い。
[0007] As shown in FIG. 2, a popular light-receiving element chip-on-carrier 7 is stored in a tray 1. At this time, the receiving space of the receiving tray 1 is a square depression, and the rectangular parallelepiped light receiving element chip-on-carrier 7 may be stored in any direction. The packaging lid 4 is put on the tray. At this time, as shown in this embodiment, the upper left cut 3
All you have to do is just cover it gently. As shown in FIGS. 1B and 2, the bonding wire protection space 5
Are provided on both sides of the chip protection space (in the form of a vertical groove), so that even if the light receiving element chip on carrier 7 is inserted in the opposite direction, the bonding wire 9 connected to the light receiving element chip 8 is crushed or cut. You won't.

【0008】[0008]

【発明の効果】以上説明したように本発明は、ボンディ
ングワイヤ保護スペースを半導体素子チップオンキャリ
アの収納スペースの両側に設けてあるため、チップオン
キャリアを逆さに収納しても蓋でボンディングワイヤが
つぶされないという効果を有する。
As described above, according to the present invention, since the bonding wire protection space is provided on both sides of the storage space for the semiconductor element chip-on-carrier, even if the chip-on-carrier is stored upside down, the bonding wire can be held by the lid. It has the effect of not being crushed.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施例の平面図、(a)は受光素子
チップオンキャリアの受け皿の平面図、(b)は包装蓋
の平面図。
FIG. 1 is a plan view of an embodiment of the present invention, FIG. 1 (a) is a plan view of a tray of a light receiving element chip-on-carrier, and FIG. 1 (b) is a plan view of a packaging lid.

【図2】受光素子チップオンキャリアを包装ケースに収
納した例を示す拡大図。
FIG. 2 is an enlarged view showing an example in which a light-receiving element chip-on-carrier is housed in a packaging case.

【図3】従来の包装ケースの平面図。FIG. 3 is a plan view of a conventional packaging case.

【図4】従来の包装ケースに受光素子チップオンキャリ
アを収納した図。
FIG. 4 is a diagram in which a light-receiving element chip-on-carrier is housed in a conventional packaging case.

【符号の説明】[Explanation of symbols]

1 受光素子チップオンキャリア受け皿 2 受光素子チップオンキャリア受け皿 3 (蓋と皿との)目合せ用切込み 4 受光素子チップオンキャリアの包装蓋 5 ボンディングワイヤ保護スペース 6 チップの保護スペース 7 受光素子チップオンキャリア 8 受光素子チップ 9 ボンディングワイヤ DESCRIPTION OF SYMBOLS 1 Receiving element chip-on carrier tray 2 Receiving element chip-on carrier tray 3 Alignment cut (with lid and plate) 4 Receiving element chip-on carrier packaging lid 5 Bonding wire protection space 6 Chip protection space 7 Light receiving element chip on Carrier 8 Light receiving element chip 9 Bonding wire

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 底部に四角い窪みで成る半導体素子チッ
プオンキャリア収納スペースがマトリクス状に多数形成
された受け皿と、前記半導体素子チップオンキャリア収
納スペースに対応する位置にチップ保護スペースとボン
ディングワイヤ保護スペースが形成され、前記受け皿に
着脱自在の包装蓋とから成る包装ケースにおいて、直交
する多数の溝を包装蓋内面に設け、前記溝のうち、一方
向に延びる溝を前記チップ保護スペースとし、チップ保
護スペースを構成する溝に直交する溝を前記ボンディン
グワイヤ保護スペースとしたことを特徴とする包装ケー
ス。
1. A receiving tray in which a large number of semiconductor element chip-on-carrier storage spaces each having a square recess at the bottom are formed in a matrix, and a chip protection space and a bonding wire protection space at positions corresponding to the semiconductor element chip-on-carrier storage space. In a packaging case comprising a packaging lid detachably mounted on the tray, a number of orthogonal grooves are provided on the inner surface of the packaging lid, and among the grooves, a groove extending in one direction is used as the chip protection space, and a chip protection space is provided. A packaging case, wherein a groove orthogonal to a groove constituting the space is used as the bonding wire protection space.
JP10297591A 1991-05-09 1991-05-09 Packaging case Expired - Fee Related JP2935286B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10297591A JP2935286B2 (en) 1991-05-09 1991-05-09 Packaging case

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10297591A JP2935286B2 (en) 1991-05-09 1991-05-09 Packaging case

Publications (2)

Publication Number Publication Date
JPH04334038A JPH04334038A (en) 1992-11-20
JP2935286B2 true JP2935286B2 (en) 1999-08-16

Family

ID=14341749

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10297591A Expired - Fee Related JP2935286B2 (en) 1991-05-09 1991-05-09 Packaging case

Country Status (1)

Country Link
JP (1) JP2935286B2 (en)

Also Published As

Publication number Publication date
JPH04334038A (en) 1992-11-20

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Legal Events

Date Code Title Description
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 19990506

LAPS Cancellation because of no payment of annual fees