JP2933444B2 - CMOS gate test circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CMOS gate test circuit and, more particularly, to a test circuit for eliminating a defect of a decoder section of a memory of a CMOS LSI.

[0002]

2. Description of the Related Art A NOR gate or a NAND gate is used as a decoder circuit of a memory IC. This NO
The R gate or the NAND gate is composed of complete CMOS.

FIG. 2 shows addresses A0, A1,.
A decoder composed of an input NOR gate (address A
0 / A0 (inverted value), A1 / A1 (inverted value), A2 / A
2 (inverted value), combination of A3 / A3 (inverted value) 2 ⁴ = 1
I-th NO (consisting of six NOR gates)
The R gate is shown.

Conventionally, test patterns for mask ROMs and EPROMs have been mainly address scan patterns. However, in this test, when the n-channel transistor 13 in the circuit of FIG. Even if the input addresses A0, A1, A2, and A3 are scanned from (1100) to (0010), the output O1 only changes from 0 (low level) to the output high impedance, so that the data 0 (low) at the previous address is output. Level), this type of failure cannot be detected. 4Mbit CM
The OS mask ROM has a defect of about 0 to 0.5% (although it depends on the circuit configuration and the manufacturing process).

For this detection, the address (000)
By skipping from (0) to (0010), a defect can be detected by maintaining the output 0 as it is. Therefore, the test pattern removes this kind of defect by testing the combination of the selected address and the non-selected address. However, in the case of random gate and microcomputer products, it has been difficult to substantially eliminate such defects.

[0006]

A decoder circuit is constituted by a NOR gate or a NAND gate like a CMOS IC memory. However, when a NOR gate or a NAND gate of a complete CMOS is used, one of the transistors connected in parallel becomes one of the transistors. In the event that a failure occurs at the source, drain or gate input during the manufacturing process, even if an input signal to turn on this transistor is input (other parallel transistors are turned off, each signal is input) Case), the output goes into a high impedance state.

Therefore, the NOR (or NA)
ND) After selecting the gate, by changing only the gate signal of the faulty transistor, the expected output changes from selection to non-selection, but the output becomes high impedance, the previous output data is retained, and the fault is detected. it can. As described above, it is necessary to consider the combination of the previous address and the next address. When all the combinations are performed, a test pattern of 2 × 16 × (16 −) = 480 is obtained in the example of FIG. And there were problems such as an increase in cost and a decrease in production capacity.

It is an object of the present invention to provide a CMOS gate test circuit which solves the above-mentioned problems and can reduce the test time.

[0009]

SUMMARY OF THE INVENTION A CMOS gate test circuit according to the present invention has at least two inputs, and includes a parallel body of a plurality of first channel type field effect transistors and a plurality of second type field effect transistors. A series body, and a common connection point between the parallel body and the series body is an output terminal.
In the test circuit of a CMOS gate to test OR gate or an AND gate, the multiple between the output terminal and the power supply potential to pull up the potential of said output terminal
The number of first channel type field effect transistors and the plurality of
Resistance of each of the second type field effect transistors
A load having a conduction resistance value that is at least one digit larger than that of a load is further connected.

[0010]

FIG. 1 shows a CMOS gate test circuit according to a first embodiment of the present invention. In FIG. 1, this embodiment is an example of a 4NOR gate constituting a decoder. P-channel transistor 2 between output and VCC power supply
9, the gate input signal T is a control signal from the test terminal, and becomes a low level input at the time of testing to turn on the transistor 29, and the signal T becomes high level (V
CC) and become non-conductive. At the time of the test, the conduction resistance of the transistor 29 is at least 10 times higher than the conduction resistance of the transistors 21 to 24, and the output low level operates as a logic circuit at a sufficiently low level. When the conduction resistance of the transistor 29 is smaller than that of the transistors 21 to 24, the transistor 29 functions as a test circuit by adding a clock signal pulse to the T signal.

Therefore, even if a failure occurs in the manufacturing process of the transistors 21 to 24 shown in FIG. 1 and a non-conductive product is produced, the test transistor 29 does not hold the previous data with a high output impedance and the VCC. The output becomes high level due to the voltage of the power supply and differs from the expected value, so that it can be determined that the output is defective (see FIG. 5).

FIG. 5 shows waveforms at various points in FIG. Control signal T, addresses A0, A1, A2, A
3. There are three waveforms of the output O1, of which the output O1 is a solid line of the waveform W1 at the time of the open failure of the transistor 23,
The expected value waveform W2 is shown by a dotted line.

FIG. 3 is a circuit diagram showing a CMOS gate test circuit according to a second embodiment of the present invention. In FIG.
In the second embodiment, the control signal T from the test terminal is not required. In this embodiment, a resistor 39 having a high resistance value is provided between an output and a VCC power supply. Here, the resistor 39
Is a resistance value that is 10 times or more the conduction resistance of the transistors 31 to 34.

FIG. 4 is a circuit diagram showing a CMOS gate test circuit according to a third embodiment of the present invention. In FIG.
The third embodiment differs from FIG. 3 in that a control signal T from a test terminal is input instead of the VCC power supply of the load resistor 49. During the test, the signal T is at a high level (VC
C voltage) and set to the GND level during actual use, the power consumption can be reduced to 1/15 with a 4NOR decoder circuit.

The resistance value of the load resistor 49 is at least 10 times the series resistance of the transistors 45 to 48. High resistance polysilicon or the like is used as the resistance.

In the first embodiment shown in FIG.
In one or more NOR gates or AND gates, a type 1 MOS transistor 2 receiving a signal controlled by a control signal from a test input terminal is arranged in parallel with a type 1 MOS transistor arranged in series,
It is characterized in that it functions as a load resistance transistor for a two-type MOS transistor arranged in parallel with a gate.

The second embodiment shown in FIG. 3 is characterized in that a high resistance (polysilicon) is used instead of the load resistance transistor. In particular, the power supply side of the load resistor is connected to the control signal.

In the third embodiment shown in FIG.
A transistor is used as a clock gate. As described above, according to the present invention, the multi-input NOR
In the gate or NAND CMOS gate, among the defects that occur in the manufacturing process, particularly, the output is prevented from becoming high impedance, and a load resistance transistor or the like is provided. To detect a defect.

[0019]

As described above, according to the present invention, the NOR
There is an effect that an open defect of a transistor arranged in parallel with a gate or an AND gate can be easily removed by inspection by adding a load transistor or a resistor. Particularly, in a mask ROM or EPROM, sequential address scanning is performed. Can be detected,
It is not necessary to consider the combination of the address numbers, so that the test pattern can be minimized and the test time can be greatly reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a decoder circuit composed of a 4NOR logic gate with a test load transistor according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a conventional decoder circuit composed of 4NOR logic gates.

FIG. 3 shows 4N with a load resistor according to a second embodiment of the present invention.
FIG. 3 is a circuit diagram showing a decoder circuit formed by OR logic gates.

FIG. 4 shows a 4N with a load resistor according to a third embodiment of the present invention.
FIG. 3 is a circuit diagram showing a decoder circuit formed by OR logic gates.

FIG. 5 is a timing chart of an input signal waveform and an output waveform of the decoder circuit of FIG. 1;

[Explanation of symbols]

A0 / A0 (inversion value), A1 / A1 (inversion value), A2 /
A2 (inverted value), A3 / A3 (inverted value) Address 11, 12, 13, 14, 21, 22, 23, 24, 3
1,32,33,34,41,42,43,44 n
Channel type MOS transistors 15, 16, 17, 18, 25, 26, 27, 28, 2
9, 35, 36, 37, 38, 45, 46, 47, 48
p-channel MOS transistor 39, 49 Resistance T test signal

Claims (5)

(57) [Claims] 1. A semiconductor device having at least two inputs, comprising a parallel body of a plurality of first channel type field effect transistors and a series body of a plurality of second type field effect transistors, wherein the parallel body and the series body are common. In a CMOS gate test circuit for testing a NOR gate or an AND gate having a connection point as an output terminal, the plurality of first gates are connected between the output terminal and a power supply potential so as to pull up the potential of the output terminal .
Channel type field effect transistor and the plurality of second
Is greater than the conduction resistance of each of the field-effect transistors.
A test circuit for a CMOS gate, further comprising a load having a conduction resistance value greater than an order of magnitude . 2. The CMOS gate test circuit according to claim 1, wherein the load is a second type field effect transistor having a gate input of a control signal from the test input. 3. The CMOS gate test circuit according to claim 2, wherein the control signal is a clock pulse. 4. The CMOS gate test circuit according to claim 1, wherein the load is a high resistance made of polysilicon. 5. The CMOS gate test circuit according to claim 4, wherein one end of the high resistance is connected to a control signal.