JP2928684B2 - VLIW type arithmetic processing unit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a VLIW (Very Lon) in a stored program digital computer.
g Instruction Word) type arithmetic processing device.

[0002]

2. Description of the Related Art The processing performance of a microprocessor depends on its operating frequency and the required number of cycles per instruction CPI (Cy).
les per Instruction) and the number of instructions required to execute the program.
That is, to increase the processing performance, it is necessary to increase the operating frequency, lower the CPI, and reduce the number of program execution instructions.

[0003] Of the above three factors, the operating frequency of the microprocessor chip has been increasing year by year due to the progress of the semiconductor manufacturing technology, but the operating frequency of the chip available at that time has an upper limit.

[0004] The microprocessor has CISC (C
omplexed Instruction Set
Computer and RISC (Reduced I)
There is an NStructure Set Computer (and a compromise between them), where a RISC chip can have a smaller CPI than a CISC chip, but still has a CPI of only one. The number of program execution instructions is the ability of the programmer (or the performance of the compiler)
However, there is a limit in reducing this.

[0005] Against this background, a VLIW architecture and a superscalar architecture have emerged. A processor employing these architectures finds an instruction that can be executed in parallel from a program and executes a plurality of processes in parallel. That is, it decodes multiple instructions simultaneously and sends them to the execution unit,
Processing is performed simultaneously. By such parallel processing, CP
I can be reduced to 1 or less.

The VLIW-type processor and the superscalar-type processor have a plurality of built-in pipelines, which are the same in that a plurality of processes can be executed simultaneously by the pipelines, but they are different in the following points. (1) Difference in instruction stream scheduling method

In superscalar, an instruction decoder of a processor finds an instruction that can be executed in parallel, and dynamically schedules the instruction at an instruction execution stage. Therefore, the parallelism can be detected only from the fetched instruction.

On the other hand, in VLIW, a program is scheduled at the time of compilation (or at the time of assembler coding). Therefore, the burden on the compiler (or programmer) is greater than that of a superscalar, but the hardware (instruction decoder) is simplified in VLIW. (2) Difference in instruction format

Generally, a superscalar is a conventional RISC.
It has the same 32-bit instruction format as the processor. The decoder selects an instruction that can be executed in parallel from the fetched instruction and inputs it to the pipeline. 32
A superscalar processor that supports a bit-length instruction format can use the instruction format of a conventional RISC processor as it is, and can maintain software compatibility with existing RISC at the object code level.

On the other hand, VLIW generally has an instruction format longer than 32 bits, and one instruction can specify a plurality of processes. For this reason, software compatibility with the existing RISC cannot be maintained, but higher performance can be obtained than with superscalar.

In the case of a processor having a pipeline structure, one instruction is executed in a plurality of stages. Since one stage is executed in principle with one clock, all instructions will be apparently executed in one clock if the pipeline operates smoothly. However, in reality, the pipeline is disturbed for various reasons, and the actual processing speed of the processor is reduced. These causes are called hazards. The mechanism that detects this hazard by hardware and automatically delays the pipeline is called an interlock.

The present invention is not a super scalar but a VL
The present invention relates to a parallel processing system based on the IW architecture. In particular, the present invention relates to a VLIW type arithmetic processing device in which the function of the interlock is improved and the delay of the pipeline is minimized and the processing speed is increased.

In general, a VLIW type arithmetic processing unit executes a fixed length instruction word capable of designating a plurality of operations.
A plurality of operations specified in one instruction word need to appear to be executed simultaneously from at least software (program).

The VLIW type arithmetic processing unit also supports a floating point operation and the like in order to improve the processing capability. This floating-point operation requires several cycles depending on the type (for example, in division).

However, in the conventional VLIW type arithmetic processing unit, a plurality of operations in one instruction designated to be executed at the same time must appear to software so as to be executed at the same time. Therefore, if some of the multiple operations specified at the same time take a long processing time, even if the other operations have been completed first, the operation will be completed until this long operation is completed. The operator did not perform the next arithmetic processing, but was allowed to play.

[0016]

As described above, since a plurality of operations in one instruction word designated to be executed at the same time must be executed at the same time in software, In the conventional VLIW type arithmetic processing device, the next instruction word is not executed until all the arithmetic operations included in the preceding instruction word are completed. For this reason, if some of the multiple operations specified at the same time take a long processing time, even if other operations have already been completed, the operation unit that has completed the operation will be On the other hand, the player is allowed to play while waiting without executing the next instruction. Then, the parallel operation time is long, and the parallel operation processing capability of the VLIW architecture cannot be fully utilized.

The present invention has been made in view of the above circumstances, and it is possible to guarantee the execution order of operations for software, and to execute even a time-consuming operation that has been activated earlier. VLI that enables subsequent instruction words to be executed in parallel as long as possible, thereby improving the operation rate of the processing unit for parallel processing and improving the overall processing capability of the processing unit.
It is an object to provide a W-type arithmetic processing device.

[0018]

According to the present invention, there is provided a VLIW type arithmetic processing unit comprising: an instruction buffer (201) for storing a VLIW including a plurality of instruction words;

An operation unit (203) having a pipeline composed of a plurality of fields corresponding to the number of instruction words included in the VLIW, and independently executing the instructions included in the VLIW in these pipelines; A hardware resource (200) referenced by an operand (Rj) of each instruction word executed by the unit;

A certain field (i =
1) a first operand (R4) for storing the execution result of the currently executing instruction (MUL), and an instruction (Add;) to be currently executed in each field (i = 0 to 3) of the arithmetic unit. comparing the second operand (R1 to R4) referred to by i = 0, 2), including the one (R4) in which the second operand (R1 to R4) matches the first operand (R4) A comparator (205) for providing a coincidence signal in the case; and a means (208) for generating an incomplete signal for each field when the instruction execution is not completed in each field (i) of the arithmetic unit;

The logical product of the coincidence signal from the comparator and the incomplete signal from the generating means is calculated for each field (i) of the arithmetic unit, and one of the fields (i) is added to the logical product. A logic circuit (209, 210) for outputting an instruction fetch inhibit signal when the result of the instruction is true, and outputting an instruction fetch signal when all the fields (i) produce a false result of the logical product;

When the logic circuit outputs the instruction fetch signal, one or more instruction words included in the VLIW are simultaneously transferred from the instruction buffer to the pipeline of the arithmetic unit, and the logic circuit fetches the instruction fetch signal. An instruction output controller (201A) for stopping the transfer of the VLIW instruction word from the instruction buffer to the arithmetic unit when outputting the inhibit signal is provided.

[0023]

In the VLIW type arithmetic processing unit according to the present invention, an instruction whose execution has been started prior to the instruction word to be executed at present is being executed, and a register number for storing an execution result of the instruction and a currently executed instruction number are stored. Compare with the register number read by the instruction about to be performed. If there is a matching register number and it is recognized that the contents of the register of the register number are still unusable, the instruction to be executed is made to wait. In other cases, even if an instruction that requires a plurality of cycles for processing is being executed, a subsequent instruction that does not refer to the execution result of the instruction is executed in parallel to speed up the processing of a plurality of instruction words.

[0024]

FIG. 1 shows an example of a 128-bit VLIW in which four 32-bit instruction words (load, operation, store, and jump) are arranged in fields 0 to 3, respectively. The operation instructions include addition (ADD), subtraction (SUB), multiplication (MUL), division (DIV), and no processing (NOP).

FIG. 2 shows V when the present invention is not applied.
An example of the LIW parallel operation processing will be described. In this example, while the division (R3 / R4) is performed in field 3 with 4 clocks, the execution units in fields 0 to 2 are idle for 3 clocks, and the multiplication (R1 * R2) is performed in field 1 for 2 clocks. During execution, the execution units in fields 0, 2, and 3 are idle for one clock. Due to this play, it takes eight clocks to complete the arithmetic processing illustrated in FIG.

FIG. 3 is a diagram when the present invention is applied .
2 shows an example of a VLIW parallel operation process corresponding to No. 2 . In this example, 4 clock division (R3 / R4) in field 3
Is performed, two clock multiplications (R1 * R
2) and twice performing one clock subtraction (R1-R2),
In field 0 and field 2, two one-clock additions (R1 + R2; R3 + R4) and one clock NOP for timing adjustment are executed once. Figure 3 (this departure
In the arithmetic processing exemplified in the case where the
During execution of the multiplication, the execution unit in the pipeline has a small playing (NOP execution) ratio, so the arithmetic processing equivalent to that in FIG. 2 (when the present invention is not applied) is completed with five clocks for convenience. FIG. 6 is a flowchart illustrating how the parallel operation processing illustrated in FIG. 3 proceeds in hardware.

First, for example, a diagram corresponding to the instruction word 1 in FIG.
Instruction 1 of 2 is hardware (parallel operation execution unit)
(ST100). By this fetch, ADD, SUB, ADD, and SUB of the instruction word 1 are collectively (synchronously) input to the four pipelines of the fields 0 to 3.

In each of the fields 0 to 3, the operand (address or data referred to by the instruction word of the input instruction (ADD, SUB, ADD, SUB). In this case, the register of the register file referred to by each pipeline) It is checked whether the numbers Rj; j are usable, for example, from 1 to 8) (ST110 to ST113). Now, the operation has just begun, and the input instructions (ADD,
SUB, ADD, SUB) require each field 0
All three operands (R1 to R4) can be used (ST114 to ST117, YES).

When all the operands of the fields 0 to 3 become usable (ST120, YES), each field 0
It is checked whether there are any hardware resources (registers currently available in the register file) necessary for the operations (1) to (3) (ST130 to ST133). Now, the operation has just begun, and all hardware resources can be used (ST134 to ST137, YES).

When all the hardware resources of the fields 0 to 3 become available (ST140, YES), the input instructions (ADD, SUB,
ADD, SUB) starts simultaneously (ST150).
To ST153). With the above processing, the processing for the instruction word 1 in FIG. 3 is completed in one clock.

Next, the instruction of FIG. 2 corresponding to the instruction word 2 of FIG.
Instruction 2 is fetched into hardware (parallel operation execution unit) (ST100). By this fetch, the AD pipeline of the instruction word 2 is stored in the four pipelines of the fields 0 to 3.
D, SUB, ADD, and DIV are input.

In each of the fields 0 to 3, it is checked whether or not the operand of the input instruction (ADD, SUB, ADD, DIV) is usable (ST110 to ST11).
3). Instruction word 1 has been completed simultaneously in one clock.
Since the operand (register R8) referenced by the instruction DIV in the field 3 is not yet used, the operands (R1 to R4, R8) of the fields 0 to 3 required by the input instruction (ADD, SUB, ADD, DIV) are required. Can be used (ST114 to ST117, YES).

When all the operands of the fields 0 to 3 become usable (ST120, Yes), each field 0
It is checked whether there are any hardware resources required for the operations of (1) to (3) (ST130 to ST133). Since none of the hardware resources requested by the input instructions (ADD, SUB, ADD, DIV) are being used by other instructions, they can all be used (ST134 to S134).
T137, yes).

When all the hardware resources of the fields 0 to 3 become available (ST140, YES), the input instructions (ADD, SUB,
ADD, DIV) start simultaneously (ST150).
To ST153). As described above, the instruction word 2 in FIG. 3 is processed.

Next, the instruction of FIG. 2 corresponding to the instruction word 3 of FIG.
Edict 3 is fetched into hardware (ST10
0). By this fetch, ADD, MUL, and ADD of the instruction word 3 are input to the three pipelines of the fields 0 to 2. ( Here, it is assumed that the compiler that has generated the processing program of FIG. 2 corresponding to FIG . 3 knows that the instruction DIV input to the field 3 with the instruction word 2 is a time-consuming processing . At this point, FIG.
No new instruction for performing a substantial process is input to the field 3 of , and NOP is inserted. N of this field 3
The OP part is ignored when executing the processing of FIG . )

In each of the fields 0 to 2, it is checked whether the operands of the input instructions (ADD, MUL, ADD) are usable (ST110 to ST113). Here, the field 3 is still processing the DIV of the instruction word 2, and the processing of the instruction DIV is performed by the two A
It is performed in the LU. Therefore, the operands (R3, R4, R8) of field 3 are not yet closed,
It can be used (ST117, Yes). Further, since the fields 0 to 2 of the instruction word 2 have been simultaneously processed in one clock, the input instruction (ADD, MUL, ADD)
Requires the operands of each of fields 0 to 2 (R1 to R2)
4) can also be used (ST114 to ST116,
Jesus).

When all the operands of the fields 0 to 3 become available (ST120, Yes), each of the fields 0 to 3 becomes available.
It is checked whether there are any hardware resources required for the operations of (1) to (3) (ST130 to ST133).

In this case, the instruction M being processed in field 1
The UL uses a resource (register R4), and since the instruction ADD of field 2 refers to this resource (register R4), there is no hardware resource required for the operation of field 2 (ST136, NO). Therefore,
Until this resource (register R4) becomes empty (that is, until the execution of the instruction MUL in field 1 is completed), field 2 waits for an instruction NOP that does nothing (ST13).
2, loop of ST136).

At this time, the instruction ADD in the field 2 is a resource (register R) used by the instruction ADD in the field 0.
See also 3). Therefore, the instruction M in the field 1
Until the execution of the UL is completed, the field 2 holds the instruction NOP (1
Clock), the field 0 also executes the instruction NOP (1 clock) and waits (ST130,
ST134 loop).

By placing the instruction NOP in the fields 0 and 2, all the hardware resources in the fields 0 to 3 can be used (ST140, Yes), and the input instructions (ADD, MUL, ADD) )
In addition, the parallel processing of the instruction (DIV) being executed proceeds simultaneously over two clocks (ST150 to ST153). As described above, the instruction word 3 in FIG. 3 is processed.

Next, the instruction of FIG. 2 corresponding to the instruction word 4 of FIG.
The edict 4 is fetched into the hardware (ST10).
0). By this fetch, ADD, SUB, and ADD of the instruction word 4 are input to the three pipelines of the fields 0 to 2. ( Here, it is assumed that the compiler that has generated the processing program of FIG. 2 corresponding to FIG . 3 knows that the instruction DIV input to the field 3 with the instruction word 2 is a time-consuming processing . Also in this case, a new instruction for performing substantial processing is not input to the field 3 of Fig. 2 and a NOP is inserted.
The part is ignored when the processing of FIG. 3 is executed. )

In each of the fields 0 to 2, it is checked whether the operands of the input instruction (ADD, SUB, ADD) are usable (ST110 to ST113). Since the fields 0 to 2 of the instruction word 3 have been simultaneously processed in two clocks, the input instruction (ADD, SUB, AD
D) requires the operands (R1
To R4) can all be used (ST114 to ST11).
6, yes). In addition, field 3 still has D of instruction word 2
The IV is being processed by the ALU in the field 3, and the operands (R3, R4, R8) for this instruction DIV can be used (ST117, YES).

When all of the operands in fields 0 to 3 become available (ST120, Yes), each
It is checked whether there are any hardware resources required for the operations of (1) to (3) (ST130 to ST133). Since the hardware resources required by the input instruction (ADD, SUB, ADD) and the instruction being executed (DIV) are not blocked, all of them can be used (ST134 to S134).
T137, yes).

When all the hardware resources in the fields 0 to 3 become available (ST140, Yes), the input instructions (ADD, SUB,
ADD) and the parallel processing of the instruction being executed (DIV) proceed simultaneously (ST150 to ST153). As described above, the instruction word 4 in FIG. 3 is processed.

FIG. 7 shows a VLI according to an embodiment of the present invention.
FIG. 2 is a block diagram illustrating a configuration of a W parallel processing device. This embodiment includes a register file 200, an instruction buffer unit 201, an operation unit 203, a register comparison circuit 205, an operation designation decoder 206, an OR circuit 207, an AND circuit 209, and an OR circuit 210. ing.

The instruction buffer unit 201 stores a VLIW composed of an instruction word group including a plurality of operations as shown in FIG. The instruction buffer unit 201 includes an instruction output controller 201A that outputs a VLIW in the instruction buffer 201B according to a signal 211 described later, and an instruction buffer 201B.
20 for storing the instruction to be executed next to the instruction in
1C.

VLI stored in instruction buffer unit 201
W is transferred to the arithmetic unit 203 via the signal line 202A. The arithmetic unit 203 receives the transferred VLIW
Are processed in parallel by four pipelines (fields 0 to 3) using the register file 200. For this processing, these pipelines each have a plurality of independent arithmetic units (ALUs) (for example, 2 units).
Table).

The register number Rj (j is, for example, 1 to 8) of the register file 200 in which the result of the operation currently being executed by the operation unit 203 is stored is indicated by a signal line 204.
It is given to the register comparison circuit 205 via i (i = 0, 1, 2, 3). The register comparison circuit 205 supplies, via the signal line 202B, the V
The register number referenced by the LIW is also provided.
The register comparison circuit 205 compares the former register number with the latter register number, and checks whether or not they match.

That is, the register comparison circuit 205 is composed of four comparison blocks 0 to 3, and these blocks 0 to 3 correspond to the fields 0 to 3 of the arithmetic unit 203, respectively. In each block i (i = 0 to 3), the register number Rj (j = 1 to 8) in which the result of the operation currently being executed is stored in the field i, and all the registers referenced by the next instruction word The match with the number is checked.

The instruction word to be executed next is supplied to the operation designation decoder 206 from the instruction buffer 202B via the signal line 202B. The decoder 206 detects a field i in which an operation other than NOP is specified, from a given instruction word. Such a field i
Is detected, the decoder 206 sets this field i
Signal 2 that causes the execution of the next instruction word to wait until the arithmetic unit becomes empty
06i is output.

The OR circuit 207 includes the register comparing circuit 20
The logical sum of the output 205i for each block i and the output 206i for each field i of the operation designation decoder 206 is calculated. The AND circuit 209 calculates the logical sum of the output 207i of each OR gate i of the OR circuit 207 and the signal 208i. The signal 208i is extracted from each field i of the arithmetic unit 203, and indicates that the operation currently being executed has not been completed for each field i.

The output 209 i of each AND gate i of the AND circuit 209 is input to the OR circuit 210. The output of the OR circuit 210 is sent to the command output controller 201A via the signal line 211.

Next, the operation of the VLIW type arithmetic processing unit having the above configuration will be described with reference to FIGS. (This operation is performed not by a microprogram but by hardware logic.)

The VLIW type arithmetic processing unit of this embodiment is
It has the following features. That is, parallel processing of a plurality of instruction words is permitted in principle, but reference is made by the register number (operand) of the register file 200 in which the operation result of the currently executed instruction word is stored and the instruction word to be executed next. The instruction buffer unit 201 waits for the instruction fetch from the instruction unit 203 when the register number (operand) to be matched matches and the operation for storing the result in the register with the matched register number has not been completed yet. It has features.

Therefore, one VLIW is transferred from the instruction buffer unit 201 to the arithmetic unit 203 via the signal line 202A.
(ST10) and the arithmetic processing is performed, the register number (Rj) in which the operation result currently being executed is stored in the field i of the arithmetic unit 203 is indicated by a signal line 204i.
And the register numbers referenced by all the instruction words included in the VLIW to be executed next are extracted from the signal line 202B of the instruction buffer 201B. The comparison circuit 205 checks whether or not the register numbers extracted from the signal lines 204i and 202B match.

Each of the four blocks 0 to 3 of the comparison circuit 205 corresponds to the fields 0 to 3 of the operation unit 203. In one block i, the register number in which the operation result currently being executed is stored in the field i is Next VLIW
Is checked for a match with all register numbers referred to by the instruction word in. If there is a match (ST14, yes)
The output 205i of the comparison circuit 205 becomes "1" (ST1
6) If they do not match (ST14, NO), output 205i
Becomes "0" (ST18).

The coincidence output 205i from the comparison circuit 205 is input to one of the OR gates 0 to 3 of the OR circuit 207. The output 206i from the operation designation decoder 206 is input to the other of the OR gates 0 to 3.

The operation designation decoder 206 detects the NOP and the field i in which the operation is designated in the next instruction word to be executed (ST20). When NOP is detected in the field i (ST22, YES), an output 206i of logic "0" is given to the OR gate corresponding to the field i (ST24). N
If the OP is not detected (ST22, No), the output 20
6i becomes "1" (ST26).

If either the output 205i or the output 206i is "1" (ST28, YES), the OR circuit 20
7, the output 207i of each of the OR gates 0 to 3 becomes "1" (ST30). The output 207i is "1" because "the instruction to be executed next uses the hardware resources for the field i" or "the instruction to be executed next is the current instruction in the field i. Refer to the result of the operation being executed. " This output 20
7i is applied to one input of a corresponding AND gate of AND circuit 209.

On the other hand, if the operation currently being executed in field i is not completed in the processing cycle (ST3)
2, yes), output 208i of unfinished field i
Becomes "1" (ST34). This output 208i is provided to the other input of the corresponding AND gate of AND circuit 209.

If the output 207i and the output 208i for the field i are both "1" (ST36, YES), the AND circuit 209 corresponding to the field i
Of the AND gate 209i becomes "1" (ST3).
8). The fact that the output 209i is "1" means "waiting for the currently executed operation to be completed in the field i".

If the output 209i of any of the AND gates 0 to 3 of the AND circuit 209 is true (logic "1") (ST40, YES), the output of the OR circuit 210 becomes true (logic "1"). (ST42). Then, signal line 2
11, a wait signal (logic “1”) is transmitted to the output controller 201A of the instruction buffer unit 201, and the instruction buffer unit 201 sends a VLIW signal to the arithmetic unit 203.
Stop batch transfer of.

When all the operations of the fields 0 to 3 are completed, the outputs 208i all become "0" (ST44, YES). Then, regardless of the output 207i of the OR circuit 207, all the outputs 209i of the AND circuit 209 become "0", so that the output of the signal line 211 also becomes "0" (ST46).
Then, the instruction transfer prohibition in the instruction output controller 201A is released, and the next VLIW in the buffer 201B is fetched by the arithmetic unit 203 (ST48).

In this way, assuming that the instruction words 1 to 4 as shown in FIG. 2 are stored in the instruction buffer unit 201 and these instruction words are to be executed sequentially, the VLIW type of the above embodiment is assumed. The following processing is realized in the arithmetic processing device.

That is, the instruction word 2, the instruction word 3, and the instruction word 4
Considering the reference relations of the arithmetic units at the compiler level, in the instruction word 2, two additions, one subtraction and one
Four operations of two divisions are performed, and the operation results are stored in registers R1, R3, R4, and R8. Of these, R1, R3, and R4 are read by instruction word 3,
R8 does not refer to instruction 3 or instruction 4. Since the contents of R8 are the result of the division, it takes four clocks for the processing, but the instruction words 3 and 4 do not necessarily have to wait for the completion of the division.

Instruction 3 executes a total of three operations of two additions and one multiplication, and stores the results in R1, R3, and R4. These R1, R3, and R4 are read out by the instruction word 4. In particular, R4 in which the result of the multiplication is stored is referred to by the instruction word 4. Therefore, the instruction word 4 is replaced with the instruction word 3
However, it is necessary to wait for completion of the multiplication of the instruction word 3.

Therefore, when the instruction words 1 to 4 shown in FIG. 2 are sequentially processed, as shown in FIG. 3, the instruction words 3 and 4 are executed while the division of the instruction word 2 is being executed. Can be performed. However, since the instruction 4 refers to the result of the multiplication of the instruction 3, the instruction 4 is executed after waiting for the result of the multiplication of the instruction 3. In this case, the execution time of the instruction word 3 and the execution time of the instruction word 4 are 3 clocks in total, but this is executed in parallel with the division of the instruction word 2, so that the completion of the instruction word 2 and the completion of the instruction word 4 are completed. Will be at the same time.

Thus, the instruction words 1 to 4 as shown in FIG.
Is executed, the processing content and time elapse as shown in FIG. That is, in FIG. 3, the total processing time (the required number of clocks) of each of the instruction words 1 to 4 is 5 clocks, which is 3 clocks smaller than 8 clocks in the case of FIG. 2.

When the instruction words 1 to 4 shown in FIG. 4 are sequentially processed, the processing contents and time elapse as shown in FIG. In the case of FIG. 2, the field 3 of the instruction word 4 is NOP
Whereas field 3 of instruction word 4 shown in FIG.
Specifies addition. In other respects, the contents of the instruction word in FIG. 2 and the contents of the instruction word in FIG. 4 are the same. How the difference in the content of the instruction word 3 in the field 3 affects the processing will be described below.

In the arithmetic unit 203, each field 0
In ~ 3, any one of addition, subtraction, multiplication, division, and NOP can be performed, but only one type of operation can be processed at the same time. If so, the instruction word 4 in FIG.
Cannot be executed until the division of the field 3 of the instruction word 2 is completed. Therefore, when a subsequent instruction intends to use a computing unit that is executing a preceding operation, it is necessary to control the subsequent operation to wait until the preceding operation is completed. That is, the execution of the instruction 4 in FIG. 4 should be started after the division of the instruction 2 is completed. When the instruction words 1 to 4 shown in FIG. 4 are sequentially processed based on such control, the result is as shown in FIG.
The total execution time up to is 6 clocks.

Note that if the configuration is such that different types of operations can be executed simultaneously in each of the fields 0 to 3 of the operation unit 203, the instruction 4 in FIG. 4 can be processed in parallel with the division of the instruction 2. 4 requires only five clocks.

As described above, according to the embodiment of the present invention, the case where the preceding instruction is trying to refer to a register whose content is undetermined because the preceding operation is being executed, and the case where the operation unit still executing the operation is When trying to use it, a control is introduced to wait for the execution of the subsequent instruction until the operation is completed and the result is determined. In other cases, however, the operation of the preceding instruction is being executed. Even if there is, in principle, the subsequent instruction word can be executed without waiting for the completion of the operation, thereby improving the parallel processing capability.

FIG. 10 shows a VL according to another embodiment of the present invention.
1 shows an IW parallel processing device. The embodiment of FIG.
In this embodiment, the configuration for detecting the NOP instruction from the next executed VLIW (the operation designation decoder 206) is omitted.

In the configuration shown in FIG. 10, the parallelism of the processing in the fields 0 to 3 is ensured by performing the following control in consideration of the reference relation of the operand by the VLIW at the compiler level.

That is, if the operation (for example, multiplication) which is to be started before the operation result is to be stored in the operand (register number) referred to by a certain instruction word is not completed, the operation waits for the completion. Otherwise, even if there is a preceding activation operation (for example, division) still in the process, control is performed so that the subsequent instruction can be executed in parallel with the operation in the middle of the process.

Thus, for example, in FIG. 3, other arithmetic processing can be executed in parallel in fields 0 to 2 during division processing in field 3. In other words, in the operand fetch stage of the VLIW, instructions are synchronously and collectively input to all fields, but in the execution stage of those instructions, independent processing is performed for each field so that the operation of each field is performed. Means (ALU, etc.)
The control for minimizing the play of the vehicle is performed.

[0077]

As described above, according to the present invention, when the register number for storing the operation result of the preceding instruction word is not referred to in the operation of the following instruction word (or used for the operation of the preceding instruction word). In the case where the middle arithmetic unit is not used by the subsequent instruction word operation), the subsequent instruction word is configured to be executed in parallel without waiting for the completion of the operation of the preceding instruction word, so that the parallel processing efficiency is high, and Higher speed can be achieved.

Further, in the above configuration, if a compiler is provided which generates a code such that the instruction word of another operation referring to the result of the operation requiring a long time for processing is as far as possible from the instruction word of the former operation, The throughput of the device of the invention can be further improved.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating an example of a VLIW instruction;

FIG. 2 shows a VLI when the present invention is not applied;
The figure explaining an example of W parallel operation processing.

FIG. 3 is a diagram illustrating a VLIW when the present invention is applied;
FIG. 9 illustrates an example of a parallel operation process.

FIG. 4 is a diagram showing a VLI when the present invention is not applied;
The figure explaining the other example of W parallel operation processing.

FIG. 5 is a diagram showing a VLIW when the present invention is applied;
The figure explaining the other example of a parallel operation process.

FIG. 6 is a flowchart illustrating the flow of a VLIW parallel operation process according to the present invention;

FIG. 7 is a block diagram illustrating a configuration of a VLIW parallel processing device according to an embodiment of the present invention.

FIG. 8 is a part of a flowchart for explaining the operation of the VLIW parallel operation processing by the apparatus of FIG. 7;

FIG. 9 is another part of the flowchart for explaining the operation of the VLIW parallel operation processing by the apparatus of FIG. 7;

FIG. 7 is a VLIW according to another embodiment of the present invention.
FIG. 2 is a block diagram illustrating a configuration of a parallel operation processing device.

[Explanation of symbols]

200: register file (hardware resource),
201: instruction buffer unit (storage means), 201A: instruction output controller (stop means), 201B, 201C ...
Instruction buffer, 203: arithmetic unit (execution means), 2
05: register comparison circuit (providing means), 206: operation designation decoder (execution means), 207: OR circuit, 208 ...
Signal lines (generation means), 209 AND circuit (output means), 210 ... OR circuit (output means), 205i ... match signal, 208i ... incomplete signal, 211 ... instruction fetch signal ("0") / instruction fetch inhibition Signal ("1").

Claims (1)

(57) [Claims] Storage means for storing a VLIW including a plurality of instruction words; and a pipeline comprising a plurality of fields corresponding in number to the number of instruction words included in the VLIW, and being included in the VLIW by these pipelines. Execution means for independently executing instructions to be executed; hardware resources referenced by operands of respective instruction words executed by the execution means; and a field of the execution means for storing an execution result of an instruction currently being executed. Comparing the first operand for execution with the second operand referenced by the instruction currently being executed in each field of the execution means, and if the second operand includes one that matches the first operand,
Providing means for providing a match signal; generating means for generating an incomplete signal for each field when instruction execution is not completed in each field of the execution means; and the match signal from the providing means and the generation ANDing with the incomplete signal from the means for each field of the execution means, and outputting an instruction fetch inhibition signal when any of the fields yields true for the logical AND; Output means for outputting an instruction fetch signal when a false result is obtained for the logical product; and when the output means outputs the instruction fetch signal, the instruction is included in the VLIW from the storage means to the pipeline of the execution means. Simultaneously transfer one or more command words,
Means for stopping transfer of the VLIW instruction word from the storage means to the execution means when the output means outputs the instruction fetch inhibition signal.