JP2928557B2 - Disc playback device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Purpose of the Invention] (Industrial application field) The present invention relates to an optical disc reproducing apparatus such as a CD-ROM drive.

2. Description of the Related Art Conventionally, as a position detector used in a disk reproducing apparatus and the like, there is a position detector described in Japanese Patent Application No. 62-260165. This position detector detects the position of the pickup by detecting the amount of rotation of the pickup feed motor.

The pickup is mounted on a rack gear, and a pinion gear meshing with the rack gear is rotationally driven by a motor. A magnet is attached to the rotating shaft of the motor, and two Hall elements are arranged near the magnet.
A signal having a phase difference of 90 degrees is output from the Hall elements.

(Problems to be Solved by the Invention) However, the Hall elements usually have a sensitivity variation of about 20%, and when there is a difference in sensitivity between the two Hall elements used here, FIG. As shown, a difference occurs between the absolute values of the output signals A and B.

This output signal is differentiated and rectified and added to obtain the speed signal C.
, Ripple occurs in the speed signal C due to the output voltage difference as shown in FIG. 6 (b).

The present invention has been made in view of such a problem,
An object of the present invention is to provide a disk reproducing apparatus that does not cause ripples in a speed detection signal even if the two detection elements have variations in sensitivity.

[Means for Solving the Problems] In order to achieve the above object, the present invention provides a disk reproducing apparatus for reading information recorded on a disk via a pickup, wherein the pickup is mounted in a radial direction of the disk. A pair of detecting means for detecting the position of the pickup by the driving means and outputting two signals having phases substantially different by 90 degrees; and
An adder for adding two signals having different degrees, a subtractor for subtracting two signals having phases that are different from each other by about 90 degrees, and differentiating outputs of the adder and the subtractor to obtain a speed signal of a pickup. A speed signal detecting unit; and a unit that compares the speed signal with a reference speed signal and feeds back a difference signal to the driving unit.

(Operation) In the present invention, since two signals having phases different by 90 degrees are added and subtracted, the absolute values of the output signals of the adder and the subtractor become equal.

For this reason, when such signals are differentiated, rectified and then added to obtain a speed signal, no ripple occurs in the speed signal because the absolute values of the two output signals are equal.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of a disk reproducing apparatus according to one embodiment of the present invention.

As shown in the drawing, this recording / reproducing apparatus includes a motor 1, a pickup 3, a tracking servo circuit 5, a switch 305, position detectors 9a and 9b, an adder 301, a subtractor 303,
Exclusive OR Gate (EXOR) 205, Differentiator 13a, 13
b, rectifiers 15a, 15b, adder 17, controller 21, counter 23, position error detection circuit 25, switch 27a, comparator 2
9. It has a power amplifier 31.

FIG. 2 is a diagram showing a schematic configuration of a reading portion of the disk 33. The disk 33 on which information is recorded is rotated by a disk motor 35. A motor 1 for moving a pickup 3 for reading detailed information recorded on the disk 33
Rotates the pinion gear 41. This pinion gear 41
Are geared with the rack gear 39, and when the motor 1 rotates, the pickup 3 moves in the radial direction of the disk 33.

 The position detectors 9a and 9b detect the rotation amount of the motor 1.

FIG. 3 is a schematic diagram near the position detectors 9a and 9b, and FIG. 4 is a plan view near the position detector.

As shown in the figure, a magnet 47 and a pinion gear 41 are mounted on a motor shaft 45 of the motor 1 mounted on the motor mounting base 43.

When the magnet 47 rotates, the position detectors (Hall elements) 9a and 9b output a voltage corresponding thereto.

In FIG. 1, a tracking servo circuit 5 performs tracking servo of the pickup 3.

FIG. 5 is a circuit diagram showing a configuration of a main part of the recording / reproducing apparatus shown in FIG. In FIG. 5, the pickup 3, the tracking servo circuit 5, the switch 305
Is omitted.

The output signal from the terminal of the position detector 9a and the output signal from the terminal are sent to an adder 301 and a subtractor 303, respectively.

The output signal from the terminal of the position detector 9b and the output signal from the terminal are sent to the adder 301 and the subtractor 303, respectively.

The adder 301 includes an operational amplifier 307, resistors 309, 311, 313, 3
It consists of 14, 315 and 316.

The subtractor 303 includes an operational amplifier 317, resistors 319, 321, 323, and 3
It consists of 25, 327, and 329.

The adder 301 adds the output signals of the position detectors 9a and 9b.

The subtractor 303 subtracts the output signals of the position detectors 9a and 9b.

With the operational amplifier 53a, the capacitor 55a, and the resistor 58a,
A differentiator 13a is configured.

 The differentiator 13a differentiates the output signal of the adder 301.

The waveform shaping circuit 12a includes an operational amplifier 65a and resistors 67a and 69a.

The waveform shaping circuit 12a shapes the waveform of the output signal of the operational amplifier 307.

The output signal of the waveform shaping circuit 12a is input to the exclusive OR gate 205 via the diode 201a and to the transistor 81b.

Similarly, the output signal of the waveform shaping circuit 12b is
The signal is input to the exclusive OR gate 205 and the transistor 81a via 01b.

The exclusive OR gate 205 includes a waveform shaping circuit 12a,
Generate a clock signal from the output signal of 12b and
Send to 3a, 23b.

The rectifier 15a includes an operational amplifier 71a, resistors 73a, 75a, 77a, 7
9a, comprising a transistor 81a.

The rectifier 15a rectifies the output signal of the differentiator 13a.

When the transistor 81a is on and the resistance 77a is equal to the resistance 73a, the operational amplifier 71a functions as an inverting amplifier with a gain of “−1”. When the transistor 81a is off, the operational amplifier 71a has a non-gain of “1”. Functions as an inverting amplifier.

The configurations of the position detector 9b, the differentiator 13b, and the rectifier 15b are the same as those of the position detector 9a, the differentiator 13a, and the rectifier 15a.

 The adder 17 includes resistors 83a and 83b and a connection point 85.

The adder 17 adds the output signals of the rectifiers 15a and 15b.

The controller 21 performs processing such as setting preset data in the counter 23 and switching the switches 27a and 305 with the switch control signal SW.

The counter 23 includes 8-bit counters 23a and 23b that count down.

The position error detection circuit 25 converts the output signals of the counters 23a and 23b into an analog signal using a ladder resistor.

When the switch control signal SW is “1”, the transistor 27a is turned on, and the output signal of the position error detection circuit 25 is sent to the comparator 29.

Further, since the switch control signal SW is sent to the switch 305 not shown in FIG. 5, when the switch control signal SW is “1”, the switch 305 is open.

When the switch control signal SW is "0", the transistor 27a is turned off and the switch 305 is turned on.

The comparator 29 and the power amplifier 31 are composed of the operational amplifier 91, the resistor 93, and the capacitors 95 and 97.

The operational amplifier 91 compares the output signal of the gain switch 19 with the speed reference voltage, amplifies the signal, and sends the amplified signal to the motor 1.

The AND circuit 101 calculates the logical product of the output signals of the MAX terminals of the counters 23a and 23b, and inputs the logical product to the STOP terminal of the controller 21 as a counter-up signal.

The operational amplifier 103 converts impedance.

The track jump direction switching circuit 105 is connected to the operational amplifier 1
07, a transistor 109, and resistors 111, 113, 115, and 117.

The track jump direction switching circuit 105 switches the track jump direction according to a signal output from the F / R terminal of the controller 21.

When the F / R signal is “1”, the transistor 109 is turned on. Therefore, if the resistances 111 and 115 are equal, the operational amplifier 10
7 functions as an inverting amplifier with a gain of “−1”. When the F / R signal is “0”, the transistor 109 is turned off.
The operational amplifier 107 functions as a non-inverting amplifier having a gain of “1”.

 Next, the operation of the present embodiment will be described.

First, the schematic operation of this embodiment will be described with reference to FIG.

When the motor 1 rotates, the magnet 47 rotates accordingly, and signals H1P and H2P are output from the terminals of the position detectors 9a and 9b. In addition, the signals H1N, H2N
Is output.

These signals are added and subtracted by operational amplifiers 307 and 317, respectively, and then differentiated by differentiators 13a and 13b.
Signals H1D and H2D are output.

There is a difference in sensitivity between the position detectors 9a and 9b, and the output signal A
When B1 has a difference in absolute value as shown in FIG. 6 (a), the output signals A2 and B2 of the adder 301 and the subtracter 303 are as shown in FIG. 6 (a). Their absolute values are equal.

For example, assuming that the output signal of the position detector 9a is Asinθ and the output signal of the position detector 9b is Bcosθ, the output signal of the adder 301 is Asinθ + Bcosθ = (A ² + B ² ) ^1/2 sin (θ + α). The output signal of 303 becomes Asinθ−Bcosθ = (A ² + B ² ) ^1/2 sin (θ−α), and the absolute values of the output signals of the adder 301 and the subtractor 303 become equal.

This signal is differentiated by differentiators 13a and 13b, and rectifiers 15a and 15b
Since the signal C2 rectified by the above and added by the adder 17 has the same absolute value of the output signals of the adder 301 and the subtractor 303, no ripple occurs. The output signals of the adder 301 and the subtractor 303 are shaped by the waveform shaping circuits 12a and 12b, and the signals H1S and H2S are output. Further, the signals H1D and H2D are rectified by the rectifiers 15a and 15b, respectively, and the signals H1V and H2V are output.

These signals H1V and H2V are added by the adder 17, compared with the speed reference signal by the comparator 29, amplified by the power amplifier 31, and fed back to the motor 1.

At the time of position control, the controller 21 sets the switch control signal SW to “0”. At this time, the switch 27 selects the output signal of the tracking servo circuit 5, and since this output signal is used as a speed reference signal, control is performed so that the output signal of the adding unit 17 matches the output signal of the tracking servo circuit 5. Is performed.

At the time of speed control, the controller 21 sets the switch control signal SW to “1”. At this time, switch
27 selects the output signal of the position error detection circuit 25, and this output signal is used as a speed reference signal, and control is performed such that the output signal of the adder 17 matches the output signal of the position error detection circuit 25.

Next, the operation of this embodiment will be described in detail with reference to FIG.

(1) Operation During Position Control The controller 21 sets the switch control signal SW to “0” during position control. For this reason, the transistor 27a is turned off, and the switch 305 not shown in FIG. 5 is turned on, so-called feed servo is performed.

(2) Operation at the Time of Speed Control At the time of speed control, the controller 21 determines whether the destination point to which the pickup 3 should be moved is the reverse direction when viewed from the current position of the pickup 3 and determines the direction.

In the positive direction, for example, the F / R signal is set to “1”, and the transistor 109 is turned on. At this time, if the resistances 111 and 115 are equal, the operational amplifier 107 functions as an inverting amplifier with a gain of “−1”, and sends a signal obtained by inverting the output signal of the operational amplifier 103 to the operational amplifier 91 via the transistor 27a.

In the reverse direction, the controller 21 sets the F / R signal to "0" and turns off the transistor 109. At this time, the operational amplifier 107 functions as a non-inverting amplifier having a gain of “1”, and sends an output signal of the operational amplifier 103 to the operational amplifier 91.

Next, the controller 21 sets data corresponding to the distance in the terminals D0 to D7. Then, the signal LOAD is set to “0”, and the data set in the terminals D0 to D7 is
Preset to a and 23b.

Next, the signal LOAD is returned to “0” to start counting, and the switch control signal SW is set to “1”.

As a result, the transistor 27a is turned on, and the switch 2
7b is off, transistors 61a and 61b are on, switch 89
Turns on.

At this time, the output signal VE of the position error detection circuit 25a and the output signals H2V and H1V of the rectifiers 15a and 15b are input to the operational amplifier 91 so that VE / R99 = − (H2V / R83a + H1V / R83b). Controlled.

The signals H2V and H1V are almost equal to 0 because they are rotating at very low speed.

Therefore, the motor 1 is fully accelerated in a predetermined direction.

When the motor 1 rotates, position signals H1S and H2S are generated,
The count values of the counters 23a and 23b decrease, and the magnitude of the signal VE also decreases.

Therefore, the reference speed voltage of the motor 1 also decreases, and the rotation speed becomes the smallest when the values of the counters 23a and 23b are "1".

When the pickup 3 reaches the target position, the counter 23
The count values of a and 23b become "0" and the counters 23a and 23b
Are both "1", the signal 1 is sent to the STOP terminal via the AND gate 101.

When the STOP signal becomes "1", the controller 21 sets the switch control signal SW to "0" and returns to the above-described position control state.

Note that the present invention can be variously modified within the scope of the technical idea.

For example, in the present embodiment, the speed detection is performed by the position detectors 9a and 9b.
However, a so-called moving magnet type speed detector of a magnet and a coil type may be separately provided.

Further, a magnetic, optical or electrostatic position detector may be used.

Various motors such as a linear motor, an electrostatic motor, a brushless motor, and a stepping motor can be used as the motor 1.

The position detectors 9a and 9b are of a two-phase type, but may be of a polyphase type.

Further, the position of the pickup at the time of a track jump is detected by pulse counting, but a speed integration method or a potentiometer method may be used.

FIG. 7 is a block diagram showing a configuration of the multiplier. This multiplier includes waveform shaping circuits 601a and 601b, an adder 603, a subtractor 605, and exclusive OR gates 607, 609, and 611.

 FIG. 8 is a waveform diagram of a signal of each section of the multiplier.

Signals S5 and S6 are signals S3 and S4 obtained by shaping signals S1 and S2.
Is a signal obtained by adding and subtracting.

The signal S7 is an exclusive OR signal of the signals S3 and S4, and the signal S8 is an exclusive OR signal of the signals S5S and S6.
9 is an exclusive OR signal of the signals S7 and S8.

As shown in the figure, the signal S9 has a quadruple pulse number.

Further, by performing the addition / subtraction processing, it is possible to achieve a multiplication of 2n times.

FIG. 9 is a block diagram showing a configuration of a multiplier for multiplying a signal by 2n times.

As shown in this figure, this multiplier is composed of n adders 70.
,.., 701-n and n subtracters 703-1,.
−n, and the i-th adder 701-i has the (i-th)
1) The first adder 701- (i-1) and the subtractor 703- (i-
The output signal of 1) is input, and the i-th subtractor 703-i
To the (i-1) th adder 701- (i-1) and the output signal of the subtractor 703- (i-1).

By providing an exclusive OR gate in this multiplier, the signal can be multiplied by 2n.

[Effects of the Invention] As described in detail above, according to the present invention, it is possible to provide a disk reproducing apparatus that does not cause ripples in the speed detection signal even if the two detection elements have variations in sensitivity. .

[Brief description of the drawings]

FIG. 1 is a block diagram showing the overall configuration of a disk reproducing apparatus using a pickup feed servo circuit according to one embodiment of the present invention, FIG. 2 is a schematic diagram showing the vicinity of the pickup, and FIGS. Front view and plan view near the detector,
FIG. 5 is a circuit diagram showing a configuration of a pickup feed servo circuit, FIG. 6 is a waveform diagram of output signals of a position detector and an adder,
FIG. 7 is a block diagram showing the configuration of the multiplier, and FIG.
FIG. 9 is a block diagram showing a configuration of a multiplier for multiplying a signal by 2n times. 1 Motor 3 Pickup 9a, 9b Position detector 13a, 13b Differentiator 15a, 15b Rectifier 17 Adder 21 Controller 23 Counter 25 Position error detection circuit 27 …… Switch 29 …… Comparator 31 …… Power amplifier 301 …… Adder 303 …… Subtractor

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G01P 3/487 G01P 3/481 G01B 21/08 G01D 5/245

Claims (2)

(57) [Claims] 1. A disk reproducing apparatus for reading information recorded on a disk via a pickup, comprising: driving means for driving the pickup in a radial direction of the disk; A pair of detection means for outputting two signals having different degrees, an adder for adding two signals having phases substantially different by 90 degrees, and a subtractor for subtracting two signals having phases different from each other substantially 90 degrees, Speed signal detecting means for obtaining the speed signal of the pickup by differentiating the outputs of the adder and the subtractor; means for comparing the speed signal with a reference speed signal and feeding back the difference signal to the driving means; A disc reproducing apparatus, comprising: 2. The driving means has a brushless motor,
2. A disk reproducing apparatus according to claim 1, wherein said speed detecting means detects a position signal of said brushless motor.