JP2928301B2 - Vector processing equipment - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vector data processing device, and more particularly to compression and expansion processing of vector elements.

[Related Art] A vector data processing device can use a plurality of arithmetic units in a time overlapping manner by a chaining function, and has a high data processing capability.

That is, in the vector data processing device, vector elements are processed in parallel in one machine cycle in order to realize high data processing capability.

Therefore, for example, in the case of 4-element parallel processing, 4n
(N = 0, 1, 2,...) A plurality of sets of vector registers and arithmetic units for processing elements, a set for processing 4n + 1 elements, a set for processing 4n + 1 elements, 4n + 3
It is composed of independent sets for processing the No. element, and each set can perform one element of arithmetic processing in one machine cycle. Thereby, the arithmetic processing of four elements is achieved in one machine cycle.

An example of such a vector element processing device is described in Nikkei Electronics, December 28, 1987, (No. 4
37) The ones introduced on pages 111-125 are known.

By the way, in image processing or the like, in order to enable high-speed operation, there is a case where compression and expansion processing of effective elements of vector elements are performed on vector data. That is, for example, in a matrix operation, component data that does not require an operation between matrices or component data for which a result can be predicted in advance is excluded, matrix data is compressed, and an operation is performed. In some cases, the arrangement is restored (extended) to the arrangement of the original matrix.

Such compression and expansion of vector data is easy when element parallel processing is not performed, for example, by one-element parallel processing. However, this cannot speed up the operation.

Therefore, when compression and expansion are performed by image processing or the like, it is necessary to switch vector elements between mutually independent element parallels to enable element parallel processing.

For this reason, there have been various studies on efficient vector data compression and expansion means.

For example, Japanese Patent Application Laid-Open No.
A first prior art described in 63268 and a second prior art described in JP-A-59-140581 are known.

In these prior arts, a mask bit indicating the validity / invalidity of each vector element is provided in correspondence with the vector element. Of the elements, only those elements whose mask bits indicate valid (perform the operation) are extracted by the aligner circuit, the intervals are narrowed (consecutive), and written in the first row of the data buffer having four rows as one element. In the empty portion of the first row of the data buffer, only the elements of the following second four elements, for which the mask bits are valid, are extracted by the aligner circuit, and the intervals are reduced to write the empty elements, thereby performing the compression process. Has been realized. In other words, in order to obtain one compressed row, it is necessary to write to the same row of the data buffer a plurality of times. In addition, among the elements in the second four elements extracted by the aligner circuit, the elements not written in the first row must be written in the first next row.

Also, by utilizing the hardware configuration described in the second prior art, the aligner circuit is read out based on the data of the first row compressed from the data buffer, that is, four elements in this example, and information of mask bits. Extracts only the elements belonging to the first matrix from among the four elements, restores the first matrix by rearranging the original matrix, and extracts only the elements belonging to the second matrix among the remaining elements, If there is an insufficient element, the second row is read from the data buffer, only the elements belonging to the second matrix are extracted, the original row is rearranged, and the first row is rearranged. The extension processing can be realized by restoring the second matrix together with the one restored from the row. In this case, among the elements in the second row, elements that do not belong to the second matrix must be used for restoring the subsequent matrix.

[Problems to be Solved by the Invention] According to the above-described conventional technology, there is a problem that control of the write address of the data buffer, switching timing, and the like is complicated. In particular, as described above, in a process in which a row before compression or expansion processing extends to a different row after processing, the complexity of the control is remarkable.

In addition, there is a problem that the amount of hardware increases to realize such complicated control.

Accordingly, it is an object of the present invention to provide a vector data processing device capable of realizing compression and expansion of vector elements by simple control without increasing the physical quantity of hardware.

[Means for Solving the Problems] To achieve the above object, the present invention provides a first method for holding m vector data composed of n vector elements and vector elements belonging to the same vector data in parallel.
, A second vector register holding in parallel one or more vector data consisting of n vector elements, and vector elements belonging to the same vector data, and each vector element held in the first vector register Corresponding to the above, a vector mask register having n × m mask bits indicating data validity / invalidity, a data buffer capable of holding n vector elements in parallel, and stored in a first vector register Aligner means for sequentially storing, in the data buffer, vector elements in each of the vector elements of the vector data, for which the corresponding mask bit indicates validity, in the data buffer in the order of parallel arrangement in the first vector register. And n vector elements are data buffers Means for storing the vector elements stored in the data buffer in parallel in the second vector register when the vector elements are stored in the first vector data processor.

Further, according to the present invention, in order to achieve the above object, a first vector register holding, in parallel, one or more vector data composed of n vector elements and vector elements belonging to the same vector data, A second vector register that holds m vector data composed of elements and vector elements belonging to the same vector data in parallel, and a vector data corresponding to each vector element of the vector data to be stored in the second vector register. A vector mask register having n × m mask bits indicating valid / invalid, a data buffer capable of holding n vector elements, and one vector data to be stored in the second vector register as a unit. Mask bit indicating valid among corresponding mask bits A number of vector elements are extracted in the order of storage of the vector data in the first vector register from the earlier parallel array in the first vector register, and are stored in the data buffer in parallel as effective vector elements of the vector data. And an aligner for rearranging valid vector elements for the one vector data stored in the data buffer based on an array of mask bits indicating validity among mask bits corresponding to the vector data.
Means for storing, in parallel, only valid vector elements for the vector data in the storage area of the second register corresponding to the mask bits indicating validity, based on the mask bits corresponding to the vector data. And a second vector data processing device.

Further, according to the present invention, in order to achieve the object, m vector data including n vector elements
One or more sets of vector registers for holding vector elements belonging to the same vector data in parallel, and a vector mask register having n × m mask bits indicating validity / invalidity of data corresponding to each vector element to be processed A first data buffer capable of holding n vector elements in parallel; a second data buffer capable of holding n vector elements in parallel; each vector data to be processed during compression processing; Of the vector elements of which the mask bit corresponding to the vector data indicates validity is extracted in parallel in the order of the parallel arrangement in the vector register.
During the expansion process, the vector elements in the vector register are stored in the vector register in units of one vector data, the number of mask bits indicating the validity among the mask bits corresponding to each vector data to be processed. Storage means for extracting data from the earlier parallel arrangement in the vector register in the order of data storage, and storing the vector data as an effective vector element in the first data buffer; first, the vector element stored in the data buffer Aligner means for sequentially rearranging and storing in a second data buffer by referring to a mask bit corresponding to the vector element according to the processing, and a vector element stored in the second data buffer according to the processing Is referred to the mask bit corresponding to Providing a third vector data processing apparatus characterized by comprising means for controlling the parallel writing to placement of the vector register, a.

That is, in order to achieve the above object, the present invention includes a process of compressing or expanding vector data held in a plurality of vector registers provided in units of element parallel, and a process of reading from a vector register to a data buffer; 2. The order conversion process by the aligner circuit and the writing process from the data buffer to the vector register are realized in three types.

That is, in the case of vector data compression: 1. Realization of logic for reading vector elements from vector registers.

Implement logic to sequentially set the vector elements read in 2.1 in the data buffer provided by the number of parallel elements.

Implement logic to read the vector elements set in 3.2 by the number of valid mask bits and write them to the vector register.

 It is.

In addition, in the case of expansion of vector data, 1. Realization of the logic to read only vector elements for which mask bits are valid from the vector register.

Implementation of logic for setting the vector element read in 2.1. In the data buffer corresponding to the element indicating that the mask bit of the data buffer provided for element parallelism is valid.

3. Realize the logic of reading the contents of the data buffer sequentially, sending a write instruction only to the vector register corresponding to the element indicating that the mask bit is valid, and writing valid data in 2.

 It is.

[Operation] According to the first vector data processing device of the present invention, in the compression processing, first, the aligner means performs the corresponding processing in each vector element of the vector data in the order stored in the first vector register. Vector elements whose mask bits indicate validity are sequentially stored in the data buffer in the storage space in the order of parallel arrangement in the first vector register.

Then, when the n vector elements are stored in the data buffer, the vector elements stored in the data buffer in parallel are stored in the second vector register.

Further, according to the second vector data processing device of the present invention, first, the first vector data to be stored in the second vector register
Using the vector data as a unit, vector elements for the number of mask bits indicating validity among the mask bits corresponding to the vector data are stored in parallel in the first vector register in the order of storage of the vector data in the first vector register. It is extracted from the earlier one in the arrangement and stored in parallel in the data buffer as an effective vector element of the vector data. Then, the aligner reorders the valid vector elements for the one vector data stored in the data buffer based on the sequence of the mask bits indicating valid among the mask bits corresponding to the vector data. After that, based on the mask bits corresponding to the vector data, only the rearranged valid vector elements for one vector data are stored in parallel in the storage area of the second register corresponding to the mask bits indicating validity. .

According to the third vector data processing device of the present invention, at the time of compression processing, first, among the vector elements of each vector data to be processed, a vector element in which a mask bit corresponding to the vector data indicates validity Are extracted in parallel in the order of the parallel arrangement in the vector register and stored in the first data buffer. Also, at the time of expansion processing, first, one vector data corresponds to each vector data to be processed. Vector elements of the number of mask bits indicating validity among the mask bits to be extracted are extracted in the order of storage of the vector data in the vector register from the earlier parallel arrangement in the vector register, and are extracted as valid vector elements of the vector data. 1 data buffer.

Then, the vector elements stored in the first data buffer are sequentially rearranged by the aligner with reference to the mask bits corresponding to the vector elements according to the processing, and stored in the second data buffer. You. Further, the vector elements stored in the second data buffer are written in parallel to the vector register based on the corresponding mask bits according to the processing.

Embodiment An embodiment of a vector processing device according to the present invention will be described below.

FIG. 1 shows a configuration of a vector processing device according to the present embodiment.

Vector registers 1a to 1d independent of element parallel
Is composed of RAM, the vector data 4n element is stored in the vector register 1a, the 4n + 1 element is stored in the vector register 1b, the 4n + 2 element is stored in the vector register 1c, and the 4n + 3 element is stored in the vector register. 1d holds (n = 0, 1, 2, 3
…).

Although not shown, each vector register 1a
1 to 1d, a register of a number designated by a program composed of a plurality of sets is read and selected.

Further, read address generation circuits 2a to 2d indicating the addresses of the read elements are provided corresponding to the vector registers 1a to 1d, respectively, and the read address generation circuits 2a to 2d are provided.
2d is composed of counter logic, generates a RAM address in which a vector data element is stored according to a count-up instruction instructed by the vector data read control circuit 4 on a one-to-one basis, and stores held data from the vector registers 1a to 1d. Output.

In a normal operation, the read address is incremented by a count-up instruction sent simultaneously from the vector data read control circuit 4 to the read address generation circuits 2a to 2d, and the vector data is read simultaneously for four elements.

The vector mask registers 3a to 3d have 1-bit mask bits indicating validity / invalidity of the element data of the vector data held in the vector register corresponding to each vector element.
3a to 3d are independently provided corresponding to the vector registers 1a to 1d.

The data buffers 5a to 5d correspond to the vector registers 1a to 1d, and hold data read from each vector register.

The data buffers 6a to 6d correspond to the data buffers 5a to 5d, and the contents of the data buffers 5a to 5d are transferred.

The mask data buffers 9a to 9d correspond to the vector mask registers 3a to 3d and hold the mask bits read from each vector mask register.

The contents of the mask data buffers 9a to 9d are copied to the mask data buffers 10a to 10d during the processing of the extension instruction.

The aligner circuit 7 has a crossbar switch structure in this example, and converts the vector element data held in the data buffers 6a to 6d into data buffers 8a to 8d.
Can be changed and copied for all of the mask data buffers 9a to 9d and the mask data buffers 10a to 10d.
Operate according to the content of

The data buffers 11a to 11d correspond to the data buffers 8a to 8d, and the contents of the data buffers 8a to 8d are transferred.

The mask count circuit 14 counts the number of valid mask bits '1' in the mask data buffers 9a to 9d at the time of processing a compression instruction, and generates a write signal for the vector registers 12a to 12d via the selectors 17a to 17d. .

The vector data write control circuit 15 outputs the count-up instruction in synchronization with the vector element data output from the vector data read control circuit 4 and the vector element data read instruction.
13a to 13d. Write address generation circuits 13a-1
3d generates write addresses for the vector registers 12a to 12d in accordance with this.
17a to 17d Selectively output the contents of the mask data buffers 10a to 10d and mask writing of the vector registers 12a to 12d.

Vector registers 12a to 12d are data buffers 11a to 11d
Is written. The written result becomes the result of the compression or expansion processing.

Note that the write address generation circuits 13a to 13d have the same configuration as the read address generation circuit. Further, the vector registers 12a to 12d are also the vector registers.
It is assumed to have the same configuration as 1a to 1d.

Here, the outline of the compression and expansion processing described below is described in the second section.
It is shown in the figure (see FIG. 2).

Hereinafter, the operation of the vector data inter-element compression instruction processing will be described.

The vector data stored in the vector registers 1a to 1d is read in parallel by four elements according to a read instruction issued from the vector data read control circuit 4. In addition, the mask bits stored in the vector mask registers 3a to 3d are set to 4 in synchronization with the vector data read instruction.
Elements are read out.

The data buffers 5a to 5d are buffers for temporarily setting vector element data read from the vector registers 1a to 1d in parallel, and are controlled by the vector data read control circuit 4 (not shown). Vector element data is read from the data buffers 5a to 5d serially in ascending order of element number.

The data buffers 6a to 6d are data buffers for sequentially setting vector element data serially read from the data buffers 5a to 5d, and a set instruction is issued from the vector data read control circuit 4.

The aligner circuit 7 converts the vector element data held in the data buffers 6a to 6d into data buffers.
It has a crossbar switch structure that can switch to all of 8a to 8d.

The mask data buffers 9a to 9d are configured to be able to hold the mask bits read from the vector mask registers 3a to 3d for each element parallel. When the vector element data read from the data buffers 5a to 5d is serially set in the data buffers 6a to 6d for four elements, the mask bits for the four elements are simultaneously masked by an instruction from the vector data read control circuit 4. Data buffers 9a to 9d are set. To be more precise, when the first element data for four elements is set in the data buffer 6a, they are simultaneously set for four elements.

When processing the compression instruction between elements of vector data,
In the aligner circuit, the mask data buffers 9a to 9d are inspected, and the contents of the data buffers 6a to 6d corresponding to the element in which the valid mask bit '1' is set are sequentially transferred to the data buffers 8a to 8d and copied.

This is because, for example, when the contents of the mask data buffers 9a to 9d are '1001', the contents of the data buffer 6a are copied to the data buffer 8a and the contents of the data buffer 6d are copied to the data buffer 8b in the first processing. In the next process, if the contents of the mask data buffers 9a to 9d are "1010", the contents of the data buffer 6a are copied to the data buffer 8c, and the contents of the data buffer 6c are copied to the data buffer 8d.

The mask count circuit 14 includes mask data buffers 9a to 9b.
Counting the number of valid mask bits '1' in 9d,
When the number of '1's is counted up to four, a write instruction signal for the vector registers 12a to 12d is generated.
At this time, the vector data that has been subjected to the compression processing at the same time is held in the data buffers 8a to 8d for four elements.

The data held in the data buffers 8a to 8d are set in the data buffers 11a to 11d sequentially read from the data buffer 8a in a serial manner. When the vector data for four elements is completed, the data is simultaneously sent to the write destination vector registers 12a to 12d. Then, in accordance with the write instruction signal output from the mask count circuit 14, the compressed data is synchronized with the vector register 12 and
Write four elements simultaneously to a-12d.

On the other hand, the vector data write control circuit 15 sequentially sends the vector data output from the vector data read control circuit 4 and a count-up instruction to the write address generation circuits 13a to 13d in synchronization with the vector data read instruction, thereby sequentially The write addresses of the vector registers 12a to 12d are incremented.

With the above processing, the compression instruction processing can be realized.

Note that the selectors 17a to 17d are vector registers 12a to 1d provided independently for element parallelism, respectively.
The write instruction signal is issued corresponding to 2d, and the output of the mask count circuit 14 is selected only at the time of inter-element compression processing of vector data.

As described above, according to the present embodiment, in the inter-element compression processing, writing of one line of compressed data only needs to be performed once to the vector register, and the control is sequentially performed to a certain number of effective mask bits. Since this can be realized by a simple method of counting the number, the vector processing device according to the present embodiment can be realized with simpler hardware than in the related art.

In the present embodiment, the aligner circuit has a cross-basis switch structure. However, as described above, in the compression processing according to the present embodiment, the rearrangement of the vector data is one.
It is performed sequentially for each vector element data. Therefore, the aligner circuit can have a time switch structure or the like, thereby further reducing the amount of hardware.

Next, the operation at the time of processing the expansion instruction between elements of vector data will be described.

The vector data read control 4 executes the vector register 1a
When issuing a count-up instruction corresponding to an instruction to read out the vector data held in to 1d, the mask bits are read from the vector mask registers 3a to 3d and sequentially inspected, and when the mask bit is '1', that is, when the vector element is When the data is valid and when this mask bit is the first valid bit, a count-up instruction is sent to the read address generation circuit 2a, and the vector data is read from the vector register 1a. Next, when the read mask bit is valid, a read address generation circuit 2b is sent out, followed by 2c and a count-up instruction. Each time the mask bit is valid, the read address generation circuits 2a to 2b are independently output. To send a count-up instruction.

As a result, during the inter-element expansion instruction processing of the vector data, new vector element data is set in the data buffers 6a to 6d only when the corresponding mask bit is "1".

The valid data in the data buffers 6a to 6d is switched through the aligner circuit 7 to the data buffers 8a to 8d in which "1" is set in the contents of the mask data buffers 10a to 10d. For example, when the contents of the mask data buffers 10a to 10d are '1001' and the data from the vector registers 1a to 1d are transferred only to the data buffers 6a to 6b, the contents of the data buffer 6a are transferred to the data buffer 8a. The contents of the data buffer 6b are switched to the data buffer 8d through the aligner circuit 7.

The contents of the mask data buffers 9a to 9d are transferred to the mask data buffers 10a to 10d.

The selectors 16a to 16d are provided with mask data buffers 10a to 10d.
A write instruction signal is generated only for the vector registers 12a to 12d corresponding to the elements whose contents are valid. As a result, only valid vector data can be written to the vector registers 12a to 12d.

 By the above processing, the extension processing can be realized.

As described above, according to the present embodiment, prior to the processing such as the change of the element data, the data included in one line after the expansion processing is extracted from the compressed data,
After that, since processing is performed in units of one line after extension processing,
Subsequent processing can be easily performed. In particular, the line before the expansion process is
After the processing, no special processing is required even in the case where the processing spans different lines. Therefore, according to the present embodiment, it is possible to provide a vector processor that can realize the extension processing with a small amount of hardware.

In the present embodiment, the vector processing apparatus capable of realizing both the compression instruction processing and the expansion instruction processing has been described. However, only one of these processings may be realized independently. In addition, the transfer (5a
(Between .about.c and 6a.about.c, and between 8a.about.c and 11a.about.c) is serial transfer, but this is shown as an example for reducing the amount of hardware, and may be parallel transfer.

[Effects of the Invention] As described above, according to the present invention, it is possible to provide a vector processing apparatus capable of realizing compression and expansion of vector data by simple control without increasing the physical quantity of hardware.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a vector processing apparatus according to one embodiment of the present invention, and FIG. 2 is an explanatory diagram showing the concept of vector data compression and expansion processing. 1a to d ... vector registers, 2a to d ... read address generation circuits, 3a to d ... vector mask registers, 4 ...
... Vector data read control circuit, 6a to d... Data buffer, 7... Aligner circuit, 8a to d... Data buffer, 9a to d... Mask data buffer, 10a to d.
Mask data buffer, 11a-d ... data buffer, 1
2a-d ... vector registers, 13a-d ... write address generation circuits, 14 ... mask count circuits, 15 ... vector data write control circuits, 16a-d ... selectors, 17a-d ... selectors.

Claims (1)

(57) [Claims] 1. A first vector register for holding a plurality of rows of a data string composed of a plurality of vector element data constituting vector data, and at least one data string composed of a plurality of vector element data constituting the vector data. A second vector register for holding the number of rows, a data buffer capable of holding the vector element data by the number of vector element data constituting the data string, and a mask bit indicating whether the vector element data is valid or invalid. A vector mask register for holding each vector element data stored in the first vector register, a reading unit for reading a plurality of vector element data from the first vector vector register in units of the data string, From reading means From the extracted plurality of vector element data, vector element data indicating that the mask bit stored in the vector mask register is valid is extracted, and the extracted vector elements are arranged in the read plurality of vector element data in the earlier order. In order from the aligner means for storing in the data buffer; and when the data buffer stores vector element data for the number of vector element data constituting the data string, a plurality of vector elements stored in the data buffer are stored. Writing means for reading the vector element data and writing it as a data string composed of a plurality of vector element data constituting the vector data in a second vector register. .