JP2927231B2 - Semiconductor integrated circuit failure analysis method and apparatus - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and an apparatus for analyzing a failure of a semiconductor integrated circuit, and more particularly to a method of analyzing a marginally defective semiconductor integrated circuit which is in a failure state depending on an operating condition, to specify a failure occurrence portion in a shorter time. The present invention relates to a failure analysis method and an apparatus capable of doing so.

[0002]

2. Description of the Related Art A technique of forming a potential distribution image of a signal wiring or the like from a detected amount of secondary electrons when a semiconductor integrated circuit is irradiated with an electron beam is effective as a means for analyzing a failure of a semiconductor integrated circuit. An electron beam tester has been developed as a device for performing failure analysis.

A method of analyzing a marginally defective semiconductor integrated circuit, which becomes defective depending on operating conditions, in a short time using this electron beam tester is disclosed in, for example, Japanese Patent Application Laid-Open No. 7-2.
No. 09387 (Japanese Patent Application No. 6-672). That is, the above publication discloses that a potential failure image of a semiconductor integrated circuit is output in real time by alternately outputting a potential distribution image of a non-defective product or non-defective product condition and a potential distribution image of a defective product or defective product condition alternately in time. A method for shortening the failure time has been proposed, and more specifically, while alternately switching between a test vector under conditions in which the semiconductor integrated circuit operates under good conditions and a test vector under conditions under which defective products operate, These test vectors are applied to an integrated circuit to cause the integrated circuit to alternately cause a good product state and a defective product state to form a potential distribution image, and display the state of the formed potential distribution image on a predetermined image display means. A way to do that has been proposed.

In this conventional failure analysis method, a potential image in a non-defective product state and a potential image in a defective product state are alternately and repeatedly displayed, so that there is a difference in potential between the non-defective product state and the defective product state. A certain location, that is, a location where a failure has occurred and a location where the failure has propagated are blinking on the image display device and can be easily visually recognized. For this reason, it has become possible to search for a defective portion of the semiconductor integrated circuit in a shorter time than before.

[0005]

In the above-described conventional failure analysis method, when alternately displaying a non-defective product state and a defective product state, a switching cycle in which a defective operation portion is easily visible is about 0.5 seconds or less. It is.

However, since the potential distribution image formed from the detected amount of secondary electrons by irradiating the integrated circuit with the electron beam contains noise due to its method,
In order to obtain a potential image with better image quality, it is necessary to continuously form a potential image for a certain period of time in the same operation state, accumulate the potential image in a frame buffer or the like, and perform processing such as averaging. For this reason, the preferable switching time is often longer than the above-described switching display cycle of the alternate display of the non-defective product state and the defective product state.

Further, when alternately displaying the non-defective product state and the defective product state while performing the averaging process, immediately after the potential image is switched between the non-defective product state and the defective product state, immediately before the switching is performed. The image quality is poor because it is averaged together with the potential image.

For this reason, according to the above-mentioned conventional method, it is impossible to alternately display the good product state and the defective product state in a switching cycle with good image quality and good visibility.

SUMMARY OF THE INVENTION Accordingly, the present invention has been made in view of the above-mentioned problems, and an object of the present invention is to change the non-defective state and the defective state of an integrated circuit at a switching cycle with good image quality and good visibility. An object of the present invention is to provide a method and apparatus for alternately displaying.

[0010]

In order to achieve the above object, the present invention provides a method of forming a potential distribution image from a detected amount of secondary electrons by irradiating a semiconductor integrated circuit with an electron beam,
A defect analysis method for a semiconductor integrated circuit, comprising identifying a defective portion of the semiconductor integrated circuit by observing the potential distribution image, wherein a repetitive application of a test vector to the semiconductor integrated circuit under non-defective product operating conditions includes The repetitive application of the test vector to the semiconductor integrated circuit under the operating conditions is alternately switched, and in synchronization with the switching of the non-defective and defective operation conditions, the potential distribution image during the non-defective operation is used for non-defective products. Writing to the frame buffer, accumulation and averaging processing, and writing, accumulation and averaging processing of the potential distribution image during the defective operation to the defective frame buffer,
Alternately switching and displaying the contents of the non-defective and defective frame buffers alternately and asynchronously with the switching of the non-defective and defective operation conditions. Provide an analysis method.

Further, the present invention is to form a potential distribution image from a detected amount of secondary electrons by irradiating an electron beam to a semiconductor integrated circuit, and to observe the potential distribution image output to an image display means. In the defect analysis device for a semiconductor integrated circuit, the defect analysis device is configured to identify a defective portion of the semiconductor integrated circuit, and repeatedly applying a test vector to the semiconductor integrated circuit under a non-defective product operation condition; Means for alternately switching the test vector to the semiconductor integrated circuit, and a non-defective frame buffer in which a potential distribution image during the non-defective operation is written and accumulation and averaging are performed, A defective frame buffer in which a potential distribution image at the time of the defective product operation is written and accumulation and averaging processing are performed. Writing the potential distribution image to the non-defective frame buffer, storing and averaging the potential distribution image, and writing the potential distribution image to the defective frame buffer during the defective product operation, storing and averaging the Means for alternately switching the non-defective and defective product operating conditions in synchronization with the switching of the non-defective product and defective product operating conditions, asynchronously with the switching of the non-defective product and defective product operating conditions, at a cycle optimal for visual recognition of the observed image, A failure analysis device for a semiconductor integrated circuit, characterized in that the content of the failure frame buffer is alternately switched and displayed on the image display means.

In each frame buffer, the potential image is accumulated and averaged. However, the contents of the potential image may be changed by an operation such as moving an observation point in the integrated circuit. If the averaging process is continued, the potential image is superimposed on the potential image in the previous state, and the potential image is averaged. After a while, a potential image that clearly shows the state after the operation cannot be obtained.

In the present invention, for this purpose, the accumulation and averaging processing of the two frame buffers is initialized in response to the input of an operation request for causing a change in the potential image content.

Alternatively, the degree of change in the content of the formed potential image is checked, and when it is determined that the change is large, the accumulation / averaging process of the frame buffer is initialized.

[0015]

According to the present invention, the above method is used to alternately display the good state and the defective state of the integrated circuit with good image quality. And the image quality will be improved.

According to the present invention, even if the cycle of alternately displaying the non-defective state and the defective state is shortened for the sake of visibility and the like,
Alternate display can be performed without deteriorating image quality.

[0017]

Embodiments of the present invention will be described in detail below with reference to the drawings.

In one embodiment of the present invention, an example in which an LSI logic tester is used to apply a test vector to a semiconductor integrated circuit and an electron beam tester is used to form a potential image will be described.

FIG. 1 is a diagram for explaining an embodiment of a method for analyzing a failure of a semiconductor integrated circuit according to the present invention. FIG. 2 is a diagram schematically showing a configuration for applying a test vector to a semiconductor integrated circuit by an LSI logic tester and forming a potential image by an electron beam tester.

Referring to FIG. 1, in one embodiment of the present invention, repeated application of a test vector under non-defective product operation conditions (101) and repeated application of a test vector under defective product operation (102) Are alternately switched to form a potential image of each semiconductor integrated circuit (103), and the potential image under the non-defective product operating condition and the potential image under the defective product operating condition are respectively subjected to the non-defective frame buffer and the defective product. The switching of the operations for writing, storing, and averaging to and from the frame buffer for use (switching between processes 104 and 105) is performed by switching the operating conditions (101
And the switching of 102), and the contents of the non-defective frame buffer and the defective frame buffer are alternately switched and displayed asynchronously with the above switching (that is, the processing is performed).
Switching between 106 and 107 is asynchronous with switching between processes 104 and 105).

Referring to FIG. 2, semiconductor integrated circuit 5 as a device under test is placed in vacuum chamber 6 of electron beam tester 1.
To be able to observe the electron beam system,
Electrical connection is made through a jig 8 and a connection cable 7,
The signal of the test vector generated by the LSI logic tester 3 is applied to the semiconductor integrated circuit 5 (note that an electron beam generator, a secondary electron detector, etc. in the electron beam tester 1 are not shown in FIG. 2). .

A test program and a test vector for a semiconductor integrated circuit to be analyzed are loaded in the LSI logic tester 3 in advance. In the test program, control is performed so that the test vector is repeatedly generated under each condition while alternately switching the non-defective product operation condition and the defective product operation condition. When such a test program is executed on the LSI logic tester 3, the test vector is transmitted from the driver (not shown) of the LSI logic tester 3 via the cable 7 and the jig 8 to the vacuum chamber 6.
Is applied to the semiconductor integrated circuit 5 inside.

A potential image obtained by detecting secondary electrons when the semiconductor integrated circuit 5 is irradiated with an electron beam is formed by the electron beam tester 1.

In the present embodiment, the formed potential images are stored in two frame buffers (not shown) built in the electron beam tester 1, that is, the potential images at the time of applying the test vector under the non-defective condition are transferred to the non-defective frame buffer. The potential image when the test vector is applied under the defective product condition is written into the defective product frame buffer while being alternately switched.

The switching of the two frame buffers is performed at the same timing as the switching of the repetitive application of the two test vectors.

For this reason, it is assumed that the LSI logic tester 3 and the electron beam tester 1 are connected to each other via a predetermined network 9 so that they can communicate with each other so as to synchronize with each other. At this time, the switching timing of the two frame buffers is determined on the side of the electron beam tester 1, and the switching timing is transmitted to the LSI logic tester 3 via the network 9 to achieve synchronization. Or, conversely, L
The switching timing is determined on the SI logic tester 3 side,
The switching timing may be transmitted to the electron beam tester 1 via the network 9 so as to achieve synchronization.

As a method for achieving synchronization, for example, the timing is transmitted each time a buffer is switched. Alternatively, the switching cycle may be determined in advance, and only the start timing may be transmitted. Further, even if another control means is prepared, and this control means controls the timing via the network 9, the above-mentioned object of the present invention can be achieved similarly.

In the two frame buffers for the non-defective product and the defective product, processing for accumulating and averaging the potential images is performed together with writing to each of them (processing 10 in FIG. 1).
4, 105).

The display of the potential image is performed by alternately switching the two frame buffers. This switching does not need to be synchronized with the switching of the operating conditions and the switching between the two frame buffers described above, so that the period is set so that the difference between the two potential images is most easily recognized.

In this embodiment, the two frame buffers and the display system (CRT 2) used in the electron beam tester 1 are used, but it is needless to say that these may be performed by another device. is there.

Each frame buffer stores and stores a potential image.
Although the averaging is performed, the contents of the potential image may be changed by an operation such as moving an observation point in the semiconductor integrated circuit.

As this kind of operation, an electron beam tester 1
On the side, for example, there are movement, rotation, enlargement, reduction, contrast adjustment, brightness adjustment, and focus adjustment of the observation place in the semiconductor integrated circuit. On the LSI logic tester 3 side, for example, start and stop of test vector application are performed. is there.

If the accumulation and averaging process is continued in the frame buffer when such an operation is performed, the potential image is averaged by superimposing the potential image in the previous state. If the time does not elapse for a while, a potential image that clearly shows the changed state cannot be obtained.

In order to cope with this problem, the input contents of the operation request in the electron beam tester 1 and the LSI logic tester 3 are examined, and whether or not the operation request is an operation causing change in the contents of the potential image is determined. In order to determine whether or not the operation is included in a list enumerated in advance as a corresponding operation, a search is performed (for example, an electron beam tester or L
Automatic search by the processing unit of the SI logic tester).

Then, when an operation request that causes a change in the content of the potential image is input, the accumulation / averaging processing of the two frame buffers is initialized. At this time, each frame buffer is initialized based on the time required to execute the operation and the time required until the change in the potential image is stabilized.

Further, as another method, a method of examining the degree of change in the contents of the formed potential distribution image and initializing the accumulation / averaging processing of each frame buffer when it is determined that the change is large is also possible. You may use together.

In order to check the degree of change in the potential distribution image, the difference between the latest potential distribution image formed and the previous potential distribution image is calculated, and this difference value is within a range where the same image can be stochastically generated. Is determined, and if not, each frame buffer is initialized.

In the present embodiment, the above-mentioned two methods are used for the purpose of initializing the frame buffer when the potential image content changes, but any one of the methods can achieve this purpose.

In the above embodiment, an LSI logic tester has been described as an example of a test apparatus for supplying a test vector to a semiconductor integrated circuit as a device under test.
The present invention is not limited to this, and is of course applicable to other test devices.

[0040]

As described above, according to the present invention,
With respect to an integrated circuit that becomes defective depending on the operating conditions, a non-defective product state and a defective product state can be alternately displayed with a clearer image having less noise than the failure analysis method of the related art and with a period that is easily visible.

As a result, according to the method of the related art, it is possible to more quickly recognize a small difference portion that has been difficult to grasp from a potential image, and it is possible to reduce the possibility of erroneous reading. It has a great effect. For this reason, according to the present invention, it is possible to detect a defective portion in a short time.

[Brief description of the drawings]

FIG. 1 is a diagram for explaining an embodiment of the present invention.

FIG. 2 is a diagram showing a combined configuration for applying a test vector to a semiconductor integrated circuit by an LSI logic tester and forming a potential image by an electron beam tester in one embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Electron beam tester 2 CRT 3 LSI logic tester 4 CRT 5 Semiconductor integrated circuit (device under test) 6 Vacuum chamber 7 Cable 8 Jig 9 Network

Claims (6)

(57) [Claims] A potential distribution image is formed from a detected amount of secondary electrons by irradiating the semiconductor integrated circuit with an electron beam, and a defective portion of the semiconductor integrated circuit is specified by observing the potential distribution image. In the semiconductor integrated circuit failure analysis method, alternate application of a test vector to the semiconductor integrated circuit under a non-defective product operating condition and repeated application of a test vector to the semiconductor integrated circuit under a defective product operating condition are alternately performed. The writing of the potential distribution image during the non-defective operation to the non-defective frame buffer, the accumulation and the averaging process, and the potential during the non-defective operation, in synchronization with the switching of the non-defective and defective operation conditions. Writing the distribution image to the defective product frame buffer, accumulation and averaging processing are alternately performed, and asynchronously with the switching of the non-defective and defective operation conditions, The contents of the frame buffer serial good and for defective switches alternately display, failure analysis method of a semiconductor integrated circuit, characterized in that. 2. The method according to claim 1, wherein the accumulating and averaging processes of the non-defective and defective frame buffers are initialized in response to an operation request that causes a change in the content of the potential image. A failure analysis method for a semiconductor integrated circuit. 3. Examining the degree of change in the content of the formed potential image and, if it is determined that the change is large, initializing the accumulation and averaging of the non-defective and defective frame buffers. 2. The method of claim 1, wherein the failure analysis is performed on a semiconductor integrated circuit. 4. A potential distribution image is formed from the amount of secondary electrons detected by irradiating the semiconductor integrated circuit with an electron beam, and the potential distribution image output to an image display means is observed, whereby the semiconductor integrated circuit is observed. A defect analysis device for a semiconductor integrated circuit, which is configured to specify a defective portion of the test vector when applying a test vector to the semiconductor integrated circuit from a test device. Means for alternately switching between repetitive application to the circuit and repetitive application of the test vector to the semiconductor integrated circuit under defective product operation conditions; and A non-defective frame buffer on which an averaging process is performed, and a potential distribution image during the operation of the defective product is written and accumulation and averaging processes are not performed. Writing, accumulating and averaging the potential distribution image during the non-defective operation to the non-defective frame buffer, and a defective frame buffer of the potential distribution image during the non-defective operation. Means for alternately switching between writing and storing and averaging processing in synchronization with the switching of the non-defective and defective operation conditions, and performing the observation asynchronously with the switching of the non-defective and defective operation conditions. Defective in a semiconductor integrated circuit, wherein the contents of the non-defective and defective frame buffers are alternately switched and displayed on the image display means at an optimal cycle for visual recognition of an image. Analysis device. 5. The failure analysis of a semiconductor integrated circuit according to claim 4, wherein the frame buffers for the non-defective product and the defective product are initialized in response to an operation request that causes a change in the content of the potential image. apparatus. 6. A non-defective and defective frame buffer is initialized when the degree of change in the content of the formed potential image is examined and it is determined that the change in the content of the potential image is large. The failure analysis device for a semiconductor integrated circuit according to claim 4.