JP2927183B2 - Semiconductor memory for image processing - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

The present invention relates to a semiconductor memory for image processing,
In particular, the present invention relates to an image processing semiconductor memory in which a plurality of processor arrays and memory cell arrays are integrated on one chip.

[0002]

2. Description of the Related Art In a conventional semiconductor memory for image processing comprising a plurality of processor arrays and memory arrays of this type, one memory cell array is allocated to one processor array, and each memory cell array is assigned an image. Are stored in the column direction. 1
One processor array processes one pixel in the row direction of image data.

Referring to FIG. 3 which shows an example of a conventional image processing semiconductor memory, each of the image processing semiconductor memories shown in FIG. 3 stores image data in a column direction of an image and stores one line in the row direction of the image. Memory cell arrays M1 to Mn corresponding to the number of pixels
1 and a main word line driving circuit D1 for setting a corresponding main word line to a selection level in accordance with the selected main word line and a sub word line selection address signal B1 to Bp for setting a corresponding sub word line to a selection level in accordance with sub word line selection address signals B1 to Bp. To Dn, a plurality of sense amplifiers respectively corresponding to the respective bit lines of the memory cell arrays M1 to Mn, and sense amplifier circuits SA1 to SAn for amplifying signals of the corresponding bit lines;
Processor arrays PE1 to PE corresponding to each of
En.

Each of the memory cell arrays M1 to Mn includes a plurality of sub-word lines W11 to Wnx, a plurality of bit lines (not shown) intersecting the sub-word lines W11 to Wnx, and the bit lines and the sub-word lines W11 to Wnx. W
A plurality of memory cells (not shown) for reading data from and writing data to the corresponding bit lines when the corresponding sub-word lines W11 to Wnx are at the selected level and provided corresponding to the intersections of nx (not shown) ) Respectively.

In this conventional semiconductor memory for image processing,
One memory cell array is allocated to each of the processor arrays, and each of the memory cell arrays stores image column direction image data. Each processor array performs processing for one pixel of the row direction image data.

Next, the operation of the conventional image processing semiconductor memory will be described with reference to FIG. 4 showing a time chart of a memory cell selection operation. The main word line drive circuit 1 supplies address signals A1 to Al. In response, one of the 2 ^l main word lines L1 is set to the selected level. Each of the sub-word line driving circuits D1 to Dn controls the selection level of the main word line L1 and the
To Bp, one of the 2 ^p × 2 ^l sub-word lines W11 to Wnx in each of the corresponding memory cell arrays M1 to Mn is set to a selection level, and a desired memory cell is selected. . Therefore, n memory cell arrays are selected at a time.

[0007]

In the conventional semiconductor memory for image processing described above, one line in the column direction of image data is allocated to one processor array, so that one line in the image row direction is processed. Has a disadvantage that power consumption is increased because all memory cell arrays are selected.

[0008]

According to the present invention, there is provided a semiconductor memory for image processing, comprising: a first memory for one line in a row direction of image data;
First to n-th processing each of the n-th pixel data
Processor array, a sense amplifier row composed of n sense amplifiers and memory cells arranged in a matrix, and
A plurality of memory cell arrays for storing the first to n-th image data; first to n-th data buses respectively connected to the first to n-th processor arrays; and n memory buses in each memory cell array. N data lines connected to the sense amplifier and connected to the n data buses;
The input / output of the first to n-th image data is performed by selecting only one of the plurality of memory cell arrays.

[0009]

FIG. 1 is a block diagram showing an embodiment of the present invention, in which constituent elements common to those in FIG. 3 are denoted by common reference characters / numerals. The image processing semiconductor memory includes a main word line driving circuit 1, sub word line driving circuits D1 to Dn, and a sense amplifier circuit SA.
1 to SAn and processor arrays PE1 to PEn, and n memory cell arrays M1A to MnA similar to the conventional one except that they store image data of n pixels for one line in the image row direction. A memory cell array selection circuit SL1 to SLn for selecting one of the corresponding memory cell arrays M1A to MnA in accordance with a block selection signal BS1 to BSn for controlling a memory cell array to be selected; N data lines X1 for inputting and outputting image data for one line
To Xn, and n data buses Y1 to Yn connecting the memory cell arrays M1A to MnA and the corresponding processor arrays PE1 to PEn.

Next, a data input / output operation between each of the processor arrays PE1 to PEn and each of the memory cell arrays M1A to MnA of this embodiment will be described with reference to FIGS. First, the main word line drive circuit 1 sets one of the 2 ^l main word lines L1 to the selected level in response to the supply of the address signals A1 to Al. Next, one of the block selection signals BS1 to BSn, in the present embodiment, BS2 is selected, and a memory cell array storing image data for one line in the row direction, here M2
A is set to the selected state via the memory cell array selection circuit SL2. The sub-word line driving circuit D2 of the selected memory cell array M2A responds to the selection level of the main word line L1 and the supply of the sub-word line selection address signals B1 to Bp, and the 2 ^p × 2 ^l sub-word lines W11 of the memory cell array M2A. ＮWnx is selected as the selection level. Therefore, the data line X of the memory cell array M2A is
1 to Xn and data buses Y1 to Yn.

As described above, the data input / output operation between the processor array for processing one line of pixel data in the row direction and the memory cell array (corresponding memory cell array) storing each of the one line of pixel data. Can be performed with only the corresponding memory cell array selected.

[0012]

As described above, the image processing semiconductor memory of the present invention assigns n pixels for one line in the row direction of image data to one memory cell array to correspond to n processor arrays, respectively. (1) Since the number of memory cell arrays selected at a time can be reduced, there is an effect that current consumption can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a semiconductor memory for image processing of the present invention.

FIG. 2 is a time chart illustrating an example of an operation in the image processing semiconductor memory according to the embodiment.

FIG. 3 is a block diagram showing an example of a conventional semiconductor memory for image processing.

FIG. 4 is a time chart illustrating an example of an operation in a conventional image processing semiconductor memory.

[Explanation of symbols]

 1 Main word line driving circuit D1 to Dn Sub word line driving circuit M1 to Mn, M1A to MnA Memory cell array SL1 to SLn Memory cell array selection circuit W11 to Wnx Subword line SA1 to SAn Sense amplifier PE1 to PEn Processor array X1 to Xn Data line Y1 to Yn data bus

Claims (2)

(57) [Claims] 1. A first image data for one line in a row direction of image data.
1 to n-th processor arrays (PE1 to PEn) for processing the respective n-th pixel data, and a sense amplifier array (SA1 to SA1 ) including n sense amplifiers.
Wherein the memory cells of one memory array selected consists SAn) and the matrix array of memory cells first to n
A plurality of memory cell array in which the image data of Ru stored (M
And 1A~MnA), said n sense amplifiers of the first to the data bus of the n (Y 1 Y n), each of the memory cell array are connected to each of the processor array of the first to n Noso
Connect respectively to each of the different data bus of said n lines
N data lines (X. 1 to X n) and the provided sub-word line and said n Sensuan selected one memory cell array of the previous texture Moriseruarei
A semiconductor memory for image processing , including means for activating a memory and inputting / outputting the first to n-th image data. 2. A memory cell array selecting means for selecting and activating a memory cell array storing first to n-th pixel data of the first row in response to a supply of a control signal. The image processing semiconductor memory according to claim 1.