JP2924797B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device,
In particular, the present invention relates to a semiconductor memory device provided with a synchronization circuit.

[0002]

2. Description of the Related Art Recently, a synchronous memory is required to operate at a high frequency of 100 MHz or more (clock cycle: 10 ns). However, when the synchronous memory is composed of a CMOS (complementary MOS), the input receiver circuit receives an external clock and uses it as a chip internal clock, so that a delay time until buffering takes, for example, about 3 ns to 4 ns. .

[0003] The circuit in the chip starts operating with the internal clock as a starting point, so that 3 ns to 4 ns becomes a dead time.

FIG. 11 shows an example of the specifications (specifications) of a 64 Mb synchronous DRAM as a specific example. The specifications in parentheses are provisional specifications. For example, synchronous DRA
M (also referred to as “SDRAM”) at a clock frequency of 117
When operating at MHz, a clock access time of 7 ns or less is required. However, as described above, since the data output circuit starts operating after receiving the internal clock delayed by 3 to 4 ns from the external clock, it is very severe to output data 7 ns after the external clock.

In view of such circumstances, recently, a PLL (Phase Locke) has been provided in a synchronous memory chip.
d Loop; phase-locked loop), SMD (Sync)
By providing a block synchronization circuit such as a synchronized mirror delay (synchronized mirror delay) and using an output of the synchronization circuit as an internal clock,
Devices have been designed to eliminate the dead time and speed up the internal operation of the chip.

FIG. 7 shows such a conventional technique. FIG.
2 shows a clock circuit of a synchronous memory. Referring to FIG. 7, RAS # (row address strobe), CAS #
(A column address strobe), a command signal such as CS # (chip select), an input circuit 401 for inputting address signals A0 to Ai, a command decoder 402,
An address latch circuit 403, a mode setting address decode & latch circuit (referred to as "mode register set circuit") 405, an input circuit 406 for inputting an external clock CLK, and a synchronization circuit 408 such as a PLL or SMD are provided. It is configured.

[0007]

One of the problems of the prior art is that it has no means for switching between use and non-use of the synchronization circuit 408, so that the synchronization circuit 408 operates even when the clock frequency is low. By using the output as the internal clock of the chip, extra power is consumed by the operation of the synchronization circuit 408 itself.

That is, the synchronous D shown in FIG.
Looking at the specifications of the RAM, when the CAS latency is low, the clock frequency may be low and the clock access time may be slow. For example, the clock access time when the CAS latency is “2” is 10 ns, which is a value that can operate sufficiently without using a synchronization circuit.

The synchronous circuit of the SMD and the PLL uses the 77M
At an operating frequency of Hz, about 5 mA of power is consumed, which is extra power consumption compared to a case where a synchronous circuit is not used.

The synchronous RAM shown in FIG.
The data out hold time (data output hold time) does not depend on CAS latency,
Although the values are the same, there is actually a need by the user to increase the data out hold time when the CAS latency is low and the clock access time is slow.

Since the data out hold time becomes shorter as the clock access becomes faster, if a synchronous circuit is used with a low CAS latency, there is a possibility that the user's needs cannot be met.

Next, as a second problem of the prior art,
There is no switching means for selecting and operating two or more types of synchronous circuits.

Referring to FIG. 8, FIG. 9 and FIG.
This will be described using the L circuit as an example. FIG. 8 is a block diagram showing a configuration of a PLL circuit, and includes a phase detector 501 for inputting a clock input and a feedback signal.
, A charge pump 502 to which the output signals up and down of the phase detector 501 are input, and a loop filter (LP
F) 503, a voltage-current conversion circuit 504, and a voltage-controlled oscillator (referred to as “VCO”) 505.

FIG. 9 shows a voltage-current conversion circuit 50 among them.
4 and an example of a circuit configuration of the VCO 505. Referring to FIG. 8, a voltage level change of LPF (low-pass filter) 503 is converted into VCO 50 by voltage-current conversion circuit 504.
5 is converted into a change in the current capability of the Nch transistor and the Pch transistor in each inverter (signals PCON and NCON), thereby changing the oscillation frequency of the VCO 505. This relationship is shown in FIG.
Shown in In FIG. 10, the horizontal axis represents the output voltage of the LPF, and the vertical axis represents the oscillation frequency of the VCO.

In the region of "non-use frequency" shown in FIG. 10, the change in the oscillation frequency of the VCO with respect to the change in the level of the LPF is too large, and the oscillation frequency is largely changed only by a little noise on the LPF. However, the frequency range cannot be used because there is a risk that the phase synchronization may be lost. Therefore, one type of PLL has a limitation in an operating frequency band.

In particular, the maximum operating frequency of a synchronous DRAM differs depending on the CAS latency. Therefore, a wide operating frequency range is required for a PLL mounted on the synchronous DRAM, and one type of PLL cannot cover this. Can not.

For this reason, for example, it is necessary to separately prepare a PLL corresponding to a low frequency by increasing the number of inverter stages constituting the ring type oscillator in the VCO.
Conventionally, there is no device provided with the switching technology.

To summarize the above, the conventional semiconductor device has no means for switching between use and non-use of the synchronous circuit, so that extra power is consumed at the time of low frequency operation. Since there is no means for switching between use and non-use of the device, there is a problem that a wide operating frequency band cannot be provided.

Accordingly, the present invention has been made in view of the above circumstances, and an object of the present invention is to provide a synchronous memory equipped with a synchronous circuit, which reduces power consumption at low clock frequency operation and has a wide operating frequency band. It is an object of the present invention to provide a semiconductor device having the following.

[0020]

In order to achieve the above object, a semiconductor device according to the present invention comprises a synchronous circuit ,
Frequency is high and CAS latency is higher than the specified value.
Sometimes, using the synchronization circuit, the clock frequency is low
When the CAS latency is smaller than a predetermined value, the synchronization
Semiconductor storage device in which switching is made so that circuits are not used
And the low frequency does not necessarily require the synchronization circuit.
In some specifications, the mode signal allows the user to
To be able to choose to use and non-use of the road, the synchronization times
For high-frequency specifications that require a path, the same as above can be achieved by setting the master slice switch or fuse switch.
Ing is configured to use the period circuit.

[0021]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a configuration of the first embodiment of the present invention, and shows a clock circuit of a synchronous memory.

Referring to FIG. 1, a first embodiment of the present invention comprises a command such as RAS # and address signals A0 to A0.
Ai input circuit 101 and command decoder 1
02, an address latch circuit 103, an address decode & latch circuit for mode setting (referred to as a "mode register set circuit") 105, a clock input circuit 106 for a synchronous circuit, and a clock input circuit 10 for a non-operating synchronous circuit.
7. Synchronizing circuit 108 such as PLL or SMD, and using the output FCLK # of the synchronizing circuit 108 as the internal clock of the chip or the output I of the clock input circuit 107 for synchronizing circuit non-operation.
And a selector 109 for selecting whether to use CLKP.

The mode register set circuit 105
Is a circuit that outputs CAS latency, burst length (burst length), and wrap type mode signals in accordance with an address at the time of a mode register set cycle. The synchronous circuit activation signal φ is output simultaneously with the mode signal, and the synchronous circuit input signal 106, the synchronous circuit non-operation input circuit 107, the synchronous circuit 108, the selector 109,
To control the activation and deactivation of these circuits.

When the synchronous circuit activation signal φ is set to the synchronous circuit activation mode in the mode register set cycle, the synchronous circuit input circuit 106 and the synchronous circuit 108 are activated and the synchronous circuit non-operation input Circuit 107
Is deactivated, and the selector 109 selects the synchronous circuit output FCLK # as the chip internal clock ICLK.

Conversely, when the synchronous circuit is set to the inactive mode, the synchronous circuit input circuit 106 and the synchronous circuit 1
08 is inactive, and the input circuit 107 for the non-operation of the synchronous circuit is used.
And the input circuit 1 for the non-operation of the synchronous circuit.
07 is selected as the chip internal clock ICLK.

FIG. 2 shows an example of a circuit configuration of the input circuit and the selector 109. In FIG. 2, the Pch transistors P1 to P3 and the Nch transistors N1 to N4 are a synchronous circuit non-operating input circuit 10 including a current mirror amplifier (a differential amplifier having a load as a current mirror circuit).
7, VREF is the reference level of the input circuit,
V _B determines the bias level of the current mirror amplifier (the gate bias voltage of the constant current source transistor N3 of the differential circuit). That is, the differential pair transistor N3 whose sources are commonly connected and connected to the constant current source transistor N3
The reference voltage VREF and the clock signal CLK are input to the gates of the first and N2, and the output terminal (Pch transistor P) of the current mirror circuit forming the load of the differential pair transistor
An output is taken out from a connection point between the drain of the transistor N2 and the drain of the transistor N2. The N-channel transistor N4 has a gate to which the synchronous circuit activation signal φ is input, and is connected between the output of the current mirror amplifier and the ground.

First, when the synchronous circuit activation mode is set, the synchronous circuit activation signal φ becomes high level, and P
ch the transistor P ₁ is turned off and stopped the supply of current to the current mirror amplifier, at the same time the Nch transistor the current mirror amplifier is inactivated N
_{When 4} is turned on, ICLKP is pulled low.

At this time, in the selector 109, a Pch transistor P4 which is connected in series between the power supply terminal and the ground terminal and has φ as an input to the gate, and ICLKP to the gate.
Becomes inactive because the Pch transistor P4 of the Pch transistor P5 and the Nch transistor N5 which have the input as the input is turned off. On the other hand, of the Pch transistor P6, the Nch transistor N6, and the Pch transistor P7 connected in series between the power supply terminal and the ground terminal, the Nch transistor N6 having φ as an input to the gate is turned on, so that the synchronous circuit output FCLK # is turned on. P as gate input
The inverter including the channel transistor P6 and the Nch transistor N7 is activated, and the output of the synchronous circuit is selectively output as ICLK.

[0029] Conversely, if it is set to a mode of the synchronization circuit inactive, is a synchronous circuit activation signal phi = low level, Pch transistor P ₁ is turned on in the input circuit, Nch
When the transistor N4 is turned off, the current mirror amplifier is activated. At the same time, in the selector 109, when the Pch transistor P4 is turned on, the Pch transistor P5 and the Nch transistor N5 which receive ICLKP as an input.
Is activated by the CMOS type
KP is selected and output as ICLK.

Further, in the portion of the selector 109 composed of the Pch transistor P ₆ , the Nch transistor N6 and the Pch transistor P7, when the synchronous circuit is in the inactive mode, FC
If LK # is controlled to be fixed at a high level, Pch transistor P6 and Nch transistor N6
Turns off and becomes inactive.

FIG. 3 is a diagram showing another example of the configuration of the selector 109. The selector 109 is constituted by a transfer gate. The CMOS type transfer gates P7 and N8 which receive ICKLP and FCLK # are input. And the output of the two transfer gates is output as the internal clock ICLK via the connected inverter and buffer.

When the synchronous circuit activation mode is set, the P-channel transistor P7, the N-channel transistor N8, and the N-channel transistor N9 which have the signal φ and its inverted signal as the gate input when the synchronous circuit activation signal φ = high level. Since P7 and N8 of the Pch transistor P8 are off and P8 and N9 are on, FCLK # becomes ICL.
It is selected and output as K.

When the synchronous circuit is set to the inactive mode, the synchronous circuit activating signal φ is set to the low level, the Pch transistor P7 and the Nch transistor N8 are turned on, and the Pch transistor P8 and the Nch transistor N9 are turned on. By turning off, ICLKP is selected and output as ICLK.

Next, the mode register set circuit will be described. As described in the above prior art, a synchronous circuit is required only for use at a high CAS latency requiring a high clock frequency and a high-speed clock access.

Therefore, the use / non-use of the synchronous circuit is determined by C
By linking (connecting) with the mode signal of the AS latency and automatically activating the synchronization circuit only in the case of the high CAS latency, the user does not have to be aware whether or not the synchronization circuit is built in the chip. You can use the device.

FIG. 4 shows a configuration of a mode register set circuit for realizing this function.

In FIG. 4, Al, Am and An represent CA
This is an address for selecting S latency, and outputs activation signals CLT1 to CLT4 for CAS latencies 1 to 4 via the decoder & latch circuit 105.

The switches 1 and 2 are, for example, aluminum master slice switches which can select switching in the final step of chip manufacturing, or switches using fuses.

In FIG. 4, when the CAS latency is "4", CLT4 is set to the high level, and φ is automatically set to the high level to activate the synchronization circuit.

When the CAS latency is "3",
Activation of the synchronous circuit can be selected by the switch 2 according to the judgment at the time of manufacture.

In the synchronous RAM, since the speed is increased with each generation and the specifications are changed, the specifications of the clock frequency and the clock access are loose even at a high CAS latency in the initial stage, so that only some users are required. It is conceivable that high clock frequency operation requiring a synchronous circuit is required, and specifications will require a synchronous circuit after several generations.

The mode set by Ai in FIG. 4 and the MDi which latches the mode is provided in consideration of this situation, and the switch 1 is initially switched to the MDi to request some high-speed products. Only the user has the address Ai
To enable the use of the synchronous circuit by the mode register set, and to switch the switch 1 to the power supply voltage VCC side when the specifications due to the high speed are changed.

FIG. 5 shows the configuration of the second embodiment of the present invention. Referring to FIG. 5, the second embodiment of the present invention is different from the first embodiment in that a synchronization circuit is further provided.
The activation signal φ _{1 of} the synchronization circuit 1 (208) output from the mode register set circuit 205 and the activation of the synchronization circuit 2 (208) It is configured to be controlled by activating signal phi ₂ of ').

The activation of the synchronizing circuit is, as in the first embodiment, synchronized with the CAS latency, for example, the synchronizing circuit is not used in the CAS latencies 1 and 2, and the synchronizing circuit 1 (208) in the CAS latency 3 And the CAS latency 4 uses the synchronous circuit 2 (20
8 ') is controlled.

FIG. 6 shows the configuration of the third embodiment of the present invention. Synchronous DRAMs require high speed especially in clock access time. Therefore, internal clocks using synchronous circuits are used only for data output control, and other circuit blocks are controlled via normal input circuits and buffered. It is conceivable to adopt a configuration in which an internal clock is used.

The third embodiment of the present invention is a clock system circuit for realizing such a configuration, and includes an output circuit control circuit 310 for performing processing such as calculating a CAS latency,
A selector 30 for selectively inputting and controlling the output of the synchronous circuit 308 or the output of the synchronous circuit non-operation input circuit 307 only to the output circuit 311 as in the first embodiment.
9 '. Otherwise, the normal input circuit 312
Are configured to use a clock signal as a chip internal clock.

[0047]

As described above, according to the present invention,
Use or non-use of synchronous circuits, use of multiple synchronous circuits
By providing a means for switching between non-use and a mode in which the switching is performed by the mode signal determined in the mode register set cycle, extra power consumed by the synchronous circuit itself when the synchronous memory operates at a low frequency is provided. This makes it possible to reduce the number of memory cells, and also enables the synchronous memory to have a wide operating frequency band.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a first exemplary embodiment of the present invention.

FIG. 2 is a diagram illustrating an example of an input circuit and a selector section for non-operation of a synchronous circuit according to the first embodiment of the present invention.

FIG. 3 is a diagram illustrating another configuration example of the selector unit according to the first embodiment of the present invention.

FIG. 4 is a diagram illustrating an example of a configuration of a mode setting address decoder and a latch circuit according to the first embodiment of the present invention.

FIG. 5 is a diagram showing a configuration of a second exemplary embodiment of the present invention.

FIG. 6 is a diagram illustrating a configuration of a third exemplary embodiment of the present invention.

FIG. 7 is a diagram showing a configuration of a conventional technique.

FIG. 8 is a block diagram illustrating a configuration of a PLL circuit used as a synchronization circuit.

FIG. 9 is a diagram illustrating an example of a configuration of a voltage-current conversion circuit and a voltage-controlled oscillator.

FIG. 10 is a diagram showing a change in oscillation frequency with respect to the level of an LPF of a voltage controlled oscillator.

FIG. 11 is a diagram showing an example of the specifications of a synchronous DRAM.

[Explanation of symbols]

101, 201 input circuit 102, 202 command decoder 103, 203 address latch circuit 104, 204 mode setting command 105, 205 mode setting address decoder & latch circuit 106, 206 synchronous circuit input circuit 107, 207 synchronous circuit non-operation input circuit 108 Synchronous circuit 109 Selector 208 Synchronous circuit 1 208 'Synchronous circuit 2 209 Selector 1 210 Selector 2 310 Output circuit control unit 311 Output circuit

Claims (4)

(57) [Claims] A clock circuit having a high clock frequency;
When the CAS latency is larger than a predetermined value,
Clock circuit is low and CAS latency is low.
When the seat is smaller than a predetermined value, the synchronization circuit is not used.
A low-frequency specification that does not necessarily require the synchronization circuit.
In lets the user select the use and non-use of the synchronizing circuit by a mode signal, the high frequency specification that requires the synchronization circuit, Ri by <br/> master slice switch or a fuse switch configuration, the A semiconductor memory device having a configuration using a synchronous circuit . 2. When the synchronous circuit is not used, a clock from an input circuit is used as an internal clock. When the synchronous circuit is used, an output of the synchronous circuit which receives a clock from the input circuit is used as an internal clock. 2. The semiconductor memory device according to claim 1, wherein: Based on 3. CAS Tray Tenshi mode signal and the setting of the switch, if it is CAS Tray Tenshi predetermined value, characterized in that it comprises a means for outputting a signal for activating the synchronization circuit 3. The semiconductor memory device according to claim 1, wherein: 4. A data output control circuit and a data output circuit for selecting an output clock of the synchronization circuit and a clock from an input buffer according to use or non-use of the synchronization circuit. 2. The semiconductor memory device according to claim 1, wherein an output from a synchronization circuit or a clock from said input buffer is input.