JP2924774B2 - Nonvolatile semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device, and more particularly to a nonvolatile semiconductor memory device which can be electrically written, rewritten, and erased.

[0002]

2. Description of the Related Art In a nonvolatile semiconductor memory device capable of electrically writing or rewriting (hereinafter simply referred to as "writing") and erasing data, a field effect transistor (hereinafter referred to as a memory cell transistor) for forming a memory cell is usually used. The data writing and erasing are performed by electrically changing the threshold voltage of (2). A typical example of such a memory cell transistor is a field effect transistor having a floating gate.

FIG. 7 shows an example of a general nonvolatile semiconductor memory device using a field effect transistor having a floating gate as a memory cell transistor. FIG.
In FIG. 1, a circuit relating to data reading is omitted, and the following description will be given mainly of data writing and erasing.

This nonvolatile semiconductor memory device is configured such that a memory cell transistor is divided into a plurality of blocks, and data of the memory cell transistors in the block is collectively erased in units of the divided blocks.

In each block, a memory cell array 1 in which memory cell transistors M11 to Mmn are arranged in a plurality of rows (m rows) and a plurality of columns (n columns) is provided corresponding to each of the plurality of rows of memory cell transistors. A plurality of word lines WL1 to WLm connected to the control gates of the memory cell transistors in the corresponding row, and a plurality of digit lines provided corresponding to the plurality of columns of the memory cell transistors and connected to the drains of the memory cell transistors in the corresponding columns, respectively. During a write operation in which the write control signal WE is at an active level with DL1 to DLn, one of the plurality of word lines WL1 to WLm is selected according to the row address signal ADr to supply a write voltage, and the erase control signal ER is activated. In the level erasing operation, all of the plurality of word lines WL1 to WLm are set to the ground potential level. A row selection circuit 2 which, except during the erase operation as the released state all of the plurality of digit lines DL1~DLn the erasing operation (during a write operation, read operation or the like)
Includes a column decoder 3 and a column selection circuit 4 for selecting one of a plurality of digit lines DL1 to DLn according to a column address signal ADc, and an erase operation (ERa is at an active level).
When the block selection signal (BS1 etc.) is at the activation level, the source voltage Vsx for erasing is supplied to all the sources of the memory cell transistors M11 to Mmn, and all sources of the memory cell transistors M11 to Mmn are set to the ground potential level except during the erasing operation. (0 V) and an erasing source voltage generating circuit 9x.

A portion other than these blocks of the nonvolatile semiconductor memory device includes a write drain voltage generation circuit 7 for generating a write drain voltage VDx in accordance with write control signals WEa to WEc which are activated during a write operation.
x, a write circuit 8 that processes the write drain voltage VDx in accordance with the level of the write data signal WDS and outputs it as the write drain voltage pulse signal Pvdx, and selects one of a plurality of blocks according to the block address signal ADb. Then, the write drain voltage pulse signal Pxd processed by the write circuit 8 on the digit line selected by the column decoder 3 and the column select circuit 4 of the selected block.
The configuration includes a block decoder 5 for supplying x and a block selection circuit 6.

Next, a detailed circuit configuration of each section of the nonvolatile semiconductor memory device will be described.

[0008] Memory cell transistors M11 to Mmn
Is, for example, as shown in FIG.
A source 11 and a drain are formed in the
A floating gate 14 and a control gate 13 are sequentially formed on a channel between the drain 1 and the drain via an insulating film 15 to form a stacked gate.

During a write operation, control gate 1
3, a write / erase power supply voltage Vpp (eg, about 12 V) is applied to the drain 12, and a write drain voltage (eg, about 6 to 7 V) is applied to the drain 12. Hot electrons are generated in the channel portion near the drain 12 by the electric field, and the hot electrons are injected into the floating gate 14 by the high voltage applied to the control gate 13. As a result, the threshold voltage of the memory cell transistor increases. If the threshold voltage at this time is set higher (for example, 7 V) than the voltage of the control gate 13 (for example, 5 V) at the time of the read operation, the memory cell transistor becomes non-conductive at the time of the read operation. In the state and the erase state, the threshold voltage is low (for example, 3 V), so that the state is in the conductive state, and these can be distinguished.

In the erase operation, the control gate 13 is set to the ground potential and the drain 12 is set to the open state.
A high electric field is generated between the control gate and the source by applying a source voltage Vsx having substantially the same level as the write / erase power supply voltage Vpp to the source 11, and electrons accumulated in the floating gate 14 are drawn out to the source 11 (F -N tunneling phenomenon), and lower the threshold voltage (for example, to about 3 V).

The write drain voltage generating circuit 7x receives a write / erase power supply voltage Vpp at one end, and a resistor R1x formed of polycrystalline silicon and one end of the resistor R1x.
, The other end of which is connected to the ground potential point, and composed of resistors R2x formed of polycrystalline silicon.
A reference voltage generator 71x that outputs a reference voltage Vrx from a connection point of R2x;
A p-channel transistor Q71 receiving p and a write control signal WEa at its gate, a drain connected to the drain of this transistor Q71 and a gate connected to a reference voltage Vr
x, an N-channel transistor Q72 having a drain connected to the source of transistor Q72, a gate receiving write control signal WEb and a source connected to the ground potential point, and a drain connected to power supply potential Vcc. An N-channel depletion-type transistor Q7 which receives a write control signal WEc at a receiving gate, connects a source to a connection point between transistors Q72 and Q73, and outputs a write drain voltage VDx from the source.
4 is provided.

Here, the resistors R1x and R2x are formed so as to have the same temperature coefficient, so that the reference voltage Vrx is a constant voltage with respect to a temperature change.

The write circuit 8 has a source connected to the ground potential point, and has a gate which has an N-channel depletion-type write data signal WDS which becomes an active level according to the level of write data and sets a write time by the period of the active level. An N-channel transistor Q81 received through a transistor Q85 of the same, and a write data signal WDS received at a gate by receiving a write drain voltage VDx at a source.
P-channel transistor Q82 which receives drain through transistor Q85 and connects the drain to the drain of transistor Q81, and has a drain voltage VDx for writing at its source.
A P-channel transistor Q83 having a gate connected to the drains of the transistors Q81 and Q82 and a drain connected to the gates of the transistors Q81 and Q82, a write / erase power supply voltage Vpp at the drain, and a write data signal WDS at the gate. An N-channel transistor Q84 that outputs a write drain voltage pulse signal Pxdx from a receiving source is provided.

The block selection circuit 6 is provided corresponding to each of the plurality of blocks, and receives a corresponding block selection signal (B1 to Bk) from the block decoder 5 at a gate, and a column selection circuit 4 and a write circuit 8 of each block. And N-channel transistors Q61 to
Q6k, the column selection circuit 4 is provided corresponding to each of the digit lines DL1 to DLn, and the corresponding column selection signal (Y1 to Y
n) N-channel type transistors Q41 to Q4 receiving n)
n, and selects one digit line according to the column selection signals Y1 to Yn and connects it to the corresponding transistor (for example, Q61) of the block selection circuit 6.

The erasing source voltage generating circuit 9x includes an AND circuit G91 for performing an AND process between the erasing control signal ERa and the block selection signal BS1, an inverter IV91 for inverting the output signal of the AND circuit G91, a source and a drain. One of them has an N-channel depletion type transistor Q91 which receives the output signal of the AND circuit G91 and connects the gate to the ground potential point, and has the source connected to the ground potential point and the gate connected to the source of the transistor Q91.
An N-channel transistor Q92 connected to the other of the drains, and a source / write power supply voltage Vp
P, which receives p and connects its gate to the gate of transistor Q92 and its drain to the drain of transistor Q92
Channel type transistor Q93 and source
The transistor Q9 receives the erasing power supply voltage Vpp and changes its gate to the transistor Q9.
2. Connect to drain of Q93 and connect drain to transistor Q
P-channel transistor Q94 connected to the gates of transistors 92 and Q93; N having a source connected to the ground potential point, a gate receiving the output signal of inverter IV91, and a drain connected to the sources of memory cell transistors M11-Mmn.
Channel type transistor Q95 and source
The transistor Q9 receives the erasing power supply voltage Vpp and changes its gate to the transistor Q9.
2, a P-channel transistor Q96 connected to the drain of Q93 and the drain connected to the drain of transistor Q95.

Next, the operation of the nonvolatile semiconductor memory device will be described.

First, the write operation will be described. In this case, the write control signals WE, WEa to WEc are at an active level, the erase control signals ER, ERa are at an inactive level, and the write data signal WDS is at a high level from a normal low level for a predetermined period according to the write data level. It is also assumed that the transistor Q61 of the block selection circuit 6 is turned on by the block decoder 5 (at this time, the block selection signal BS1 also goes to the active level).

The active levels of the write control signals WEa to WEc are as follows: WEa and WEc are at a low level and WEb is at a high level. Since the transistor Q72 is pulled in the potential direction, the transistor Q72 also becomes conductive. However, the conduction resistance of the transistor Q73 is set extremely large, and the write drain voltage VDx is set to VDx = Vrx-Vt72. Here, Vt72 is the transistor Q72
The threshold voltage takes into account the back gate bias effect (hereinafter similarly indicated). Note that the reference voltage Vrx
Represents the resistance values of the resistors R1x and R2x as R1x,
Assuming that R2x, Vrx = Vpp.R2x / (R1x + R2x).

The write drain voltage VDx is supplied to the write circuit 8, and during the period when the write data signal WDS is at a low level, the transistors Q81, Q83, and Q84 become non-conductive, so that transmission of the write drain voltage VDx is suppressed. The transistors Q81 and Q8 only during the high level period
3, Q84 conducts, and the gate of the transistor Q84 is supplied with the write drain voltage VDx through the transistor Q83.
Vt84) is output as the write drain voltage pulse signal Pvdx.

This write drain voltage pulse signal Px
The dx passes through the transistor Q61 of the block selection circuit 6 and is supplied to one digit line (for example, DL1) through the transistor (for example, Q41) of the column selection circuit 4 which is turned on by the column decoder 5.

On the other hand, the row selection circuit 2 supplies a row address signal A
One word line (for example, WL1) is selected in accordance with Dr and a voltage of a word line for writing, for example, a power supply voltage for writing / erasing Vpp is supplied.

The erasing source voltage generating circuit 9x
Since the erase control signal ERa is at the inactive level (low level), the output of the AND circuit G91 goes low, the output of the inverter IV91 goes high, and the transistor Q9
3, Q95 are turned on, and transistors Q92, Q94,
Q96 is turned off, and the memory cell transistors M11 to M11 are turned off.
The source of Mmn is set to the ground potential.

In this way, one memory cell transistor (M11) is selected, and its control gate is applied with the write / erase power supply voltage Vpp, its drain is applied with the write drain voltage pulse signal Pxdx, and its source is grounded. This memory cell transistor (M
Data writing to 11) is performed. The time for writing data to the memory cell transistor (M11) is determined by the pulse width of the write drain voltage pulse signal Pxdx. The pulse width is determined by the threshold voltage of the memory cell transistor in the initial state and the erased state (reading). The time is set to the time required to change from a conductive state (for example, 3 V during operation) to a write state value (for example, 7 V (non-conductive state during read operation)). Further, the voltage Vpdx of the write drain voltage pulse signal Pvdx at this time is given by Vpdx = Vpp.R2x / (R1x + R2x) -Vt
72-Vt84. Since the path leading to the supply of the voltage Vpdx to the drain of the selected memory cell transistor includes some circuit resistance, the actual voltage applied to this drain is slightly lower than the voltage Vpdx. .

Next, the erasing operation will be described.

In this case, the erase control signal ER becomes active level, and the column decoder 3 turns off all the transistors Q41 to Q4n of the column selection circuit 4 to open all the drains of the memory cell transistors M11 to Mmn. 2, the memory cell transistor M1
All control gates 1 to Mmn are set to the ground potential level. Also, a block selection signal (for example, BS) corresponding to the selected block among the blocks of the erase unit
1) and the erase control signal ERa is at an active level (high level)
Since the output of the AND circuit G91 is at a high level and the output of the inverter IV91 is at a low level, the transistors Q92, Q94 and Q96 are turned on, and the transistor Q9 is turned on.
3, Q95 are turned off, and the memory cell transistor M
The power supply voltage V for writing / erasing is applied to all the sources 11 to Mmn.
An erasing source voltage Vsx of level pp is supplied.

Thus, the memory cell transistor M11
To Mmn, a high voltage is applied between all the source and control gates, electrons in the floating gate are extracted, and the threshold voltage decreases. Vpp level erase source voltage V is applied to memory cell transistors M11-Mmn.
The time during which sx is applied is determined by the period during which the erase control signal ERa is at the active level. During that period, the threshold voltage of the memory cell transistor is changed from the value in the write state (for example, 7 V) to the initial state and the erase state. (For example, 3 V).

During the erase operation, the write control signals WE, WEa to WEc, etc. are of course inactive, the write data signal WDS is always at a low level, the write drain voltage VDx is at the power supply voltage Vcc level, and the transistor Q84 is It is non-conductive.

[0028]

In the conventional nonvolatile semiconductor memory device, the reference voltage generating section 71 is used during a write operation.
x for a constant level of reference voltage V
rx, the threshold voltage Vt72 of transistor Q72
The write drain voltage VDx is generated as low as possible, and the write drain voltage VDx is processed by the write data signal WDS and the voltage level is further reduced as the write drain voltage pulse signal Pvdx by the threshold voltage Vt84 of the transistor Q84. The transistors (Q61, Q41) of the block selection circuit 6 and the column selection circuit 4
, Etc.), and the threshold voltages Vt72, Vt84 of the transistors Q72, Q84 hardly change in response to a temperature change. Therefore, the threshold voltages Vt72, Vt84 are applied to the drain of the memory cell transistor. Voltage Vpdx becomes substantially constant with respect to temperature change, but as the temperature rises, the transistors (Q84, Q61) connected in series with the memory cell transistor
To Q6k, Q41 to Q4n), the amount of current flowing from the drain of the memory cell transistor due to the write drain voltage pulse signal Pvdx is reduced, and the threshold voltage of the memory cell transistor is changed between the initial state and the erased state. The time required to change from the value to the value in the write state becomes longer, that is, the write speed becomes slower, and the threshold voltage in the write state may not be reached within the pulse width of the write drain voltage pulse signal Pvdx. If the pulse width is increased to solve this problem, there is a problem that the write operation speed is reduced. The change in the writing time with respect to the temperature is, as shown in FIG.
In some cases, the temperature becomes about 3.5 times between 100 and 100 ° C.

In the erasing operation, a constant writing / erasing power supply voltage Vpp is applied to the source of the memory cell transistor for a predetermined period in response to a temperature change.
During the erase operation, the threshold voltage in the written state is changed from the threshold voltage in the initial state to the threshold voltage in the erased state as the temperature rises in the memory cell transistor. There is a danger that the erasing time is shortened, that is, the erasing speed is increased, and there is a risk that an overerased state may occur. If the application period of the erasing source voltage Vsx is shortened in an attempt to eliminate this, insufficient erasing occurs at low temperatures There was a problem of doing. The change in the erase time with respect to the temperature is about twice as shown in FIG. 10 between the temperature of 0 ° C. and 100 ° C.

An object of the present invention is to provide a stable write characteristic by suppressing a write time and a change amount of a write speed with respect to a temperature change without lowering a write operation speed during a write operation. Another object of the present invention is to provide a nonvolatile semiconductor memory device which can obtain a stable erasing characteristic by suppressing a change amount of an erasing time and an erasing speed with respect to a temperature change.

A nonvolatile semiconductor memory device according to the present invention comprises a memory cell array in which memory cell transistors for writing and erasing data by electrically changing a threshold voltage are arranged in a plurality of rows and a plurality of columns. And a plurality of digit lines provided corresponding to the plurality of columns of the memory cell transistors and connected to the drains of the memory cell transistors in the corresponding columns, and a predetermined digit line of the plurality of digit lines during a write operation. A column selecting means for selecting, and a reference voltage generating section for generating a reference voltage from a power supply voltage of a predetermined level, including generating a write drain voltage pulse signal having a predetermined pulse width at a voltage level corresponding to the reference voltage. Writing drain voltage supply means for supplying to the digit line selected by the column selection means,
An erase source voltage generating means for generating an erase source voltage during an erase operation and supplying the source voltage to all the memory cell transistors of the memory cell array; A circuit for generating the write drain voltage pulse signal of a voltage level having a predetermined temperature characteristic during a write operation, wherein a write state of the memory cell transistor is determined based on a threshold voltage in an initial state and an erase state during the write operation; It is configured to reduce the amount of change with respect to temperature change during the time required to change to the threshold voltage.
Further, the temperature characteristic of the voltage level of the write drain voltage pulse signal is configured to have a positive temperature coefficient with respect to a temperature change.

The reference voltage generator included in the write drain voltage supply means includes a first resistor having a first resistance value having a first temperature characteristic and a first resistance receiving a power supply voltage of a predetermined level at one end; Is connected to the other end of the first resistor, the other end is connected to the ground potential point, and a second resistor having a second resistance value having a second temperature characteristic different from the first temperature characteristic is provided. And a circuit for generating a reference voltage having a predetermined temperature characteristic from a connection point of the first and second resistors. Further, the first and second resistors of the reference voltage generator are connected to different activation energies. And have a predetermined resistance value, and are configured as resistors having mutually different temperature characteristics and a predetermined resistance value.

Further, the erasing source voltage generating means is a circuit for generating an erasing source voltage having a voltage level having a predetermined temperature characteristic during an erasing operation, and a threshold when the memory cell transistor is in a writing state during the erasing operation. It is configured to reduce the amount of change with respect to the temperature change during the time from the value voltage to the threshold voltage in the initial state and the erase state, and furthermore, the temperature characteristic of the voltage level of the erase source voltage is improved. , And has a negative temperature coefficient with respect to a temperature change.

The erasing source voltage generating means receives a power supply voltage of a predetermined level at one end and has a third resistor having a third temperature characteristic, and one end is connected to the other end of the third resistor. A fourth resistor having a fourth resistance value having a fourth temperature characteristic different from the third temperature characteristic and having an end connected to a ground potential point, and a connection point between the third and fourth resistances. An erasing reference voltage generator for generating an erasing reference voltage; and an erasing source voltage having a voltage level corresponding to the erasing reference voltage. Are formed so as to have different activation energies and a predetermined resistance value,
The resistors are configured to have different temperature characteristics and a predetermined resistance value.

[0034]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

This embodiment is different from the conventional nonvolatile semiconductor memory device shown in FIG. 7 in that a write drain voltage generation circuit 7x is replaced with a reference voltage generation section 71 therein.
x, a first resistor R1 having a first resistance value having a first temperature characteristic having a write / erase power supply voltage Vpp at one end.
And a second resistor R2 having one end connected to the other end of the resistor R1, the other end connected to the ground potential point, and having a second temperature characteristic different from the first temperature characteristic. A reference voltage generator 71 for generating a reference voltage Vra having a positive temperature coefficient with respect to a temperature change from the connection point of R2 is provided as a write drain voltage generator 7, and a memory cell transistor (M11 to Mmn) during a write operation is provided. The amount of change in the writing time (hereinafter, simply referred to as writing time) from the threshold voltage in the initial state and the erasing state to the threshold voltage in the writing state (hereinafter simply referred to as writing time) is reduced ( Control).

The temperature characteristics and resistance values of the resistors R1 and R2 are as follows:
As shown in FIG. 2, the temperature characteristics are both negative coefficients, and the resistance R1 changes more greatly than the resistance R2.
At 25 ° C., the resistance R1 is set to 6.5 MΩ and the resistance R2 is set to 8.0 MΩ. By setting the temperature characteristics and the resistance values of the resistors R1 and R2 in this manner, a reference voltage Vra having a positive temperature coefficient as shown in FIG. 3A can be generated. Is applied to the gate of the transistor Q84, the current flowing through the transistor Q84 having the characteristic that the transfer conductance decreases as the temperature rises, and the gate voltage rises. The source voltage, that is, the voltage level of the write drain voltage pulse signal Pvd also increases.

Accordingly, the block selection circuit 6 connected in series with the selected memory cell transistor (eg, M11)
Even if the transfer conductance of the transistors (Q61, Q41) of the column selection circuit 4 becomes small, the current flowing through these transistors is written into the write drain voltage pulse signal Pv
d, the voltage level applied to the drain of the selected memory cell transistor (M11) also increases, so that the amount of current flowing into the drain of the memory cell transistor (M11) is reduced. As shown in FIG. 3B, the amount of change in the writing time with respect to the temperature change was 3.5 times as large as 0 ° C. to 100 ° C. in the conventional example. .5 times.

In the first embodiment, the resistance R
In order to give the temperature characteristics as shown in FIG. 2 to the resistors R1 and R2, the resistors R1 and R2 are formed of polycrystalline silicon.
The fact that the resistance formed of this polycrystalline silicon has the following properties is utilized.

(A). The temperature characteristic of the resistor R is R = Roex
It is represented by p (Eo / kT). Where Ro is a constant, E
o is activation energy, k is Boltzmann's constant, and T is temperature.

(B). Ro and Eo shown in the section (a) are determined by the structure of the polycrystalline silicon, and can be controlled by the impurity concentration to be doped. Activation energy Eo and resistivity (Ro
/ Length) can be increased by increasing the concentration of the impurity to be doped.

From the above item (a), it is understood that the temperature dependence of the resistance R can be increased by increasing the activation energy. Further, according to the item (b), the activation energy Eo can be controlled by the impurity concentration to be doped.
In this first embodiment, the reference voltage Vra is
In order to have a temperature characteristic as shown in FIG.
This is realized by making the temperature dependency of 1 larger than the resistance R2. Specifically, the activation energy Eo of the resistor R2 is set to 0.1 eV, while the activation energy Eo of the resistor R2 is set to 0.2 eV.
eV, and further, by adjusting the width and length of these resistors R1 and R2, the resistance value is set to R1 =
The values are set to be about 6.5 MΩ and R2 = 8.0 MΩ.

Thus, a reference voltage Vra having a temperature characteristic as shown in FIG.
By driving the drain of the memory cell transistor with a write drain voltage pulse signal Pvd of a voltage level corresponding to a, the temperature dependence of the write time (write speed) as shown in FIG. Even if the pulse width of the write drain voltage pulse signal Pvd is kept constant, the threshold value of the memory cell transistor after the write operation can be made to fall within a predetermined range. , Stable writing characteristics can be obtained.

FIG. 4 is a circuit diagram of a main part of the second embodiment of the present invention.

In the second embodiment, the present invention is applied to an erasing source voltage generating circuit portion.
In the first embodiment shown in FIG. 1 and the conventional erase source voltage generation circuit 9x shown in FIG. 7, the write / erase power supply voltage Vpp is directly supplied to the sources of the transistors Q93, Q94 and Q96. On the other hand, in the second embodiment, the erasure that generates the erasure power supply voltage Vep having a predetermined temperature characteristic with a circuit configuration similar to that of the write drain voltage generation circuit 7 of the first embodiment. An erasing power supply voltage generating circuit 92 is provided. The erasing power supply voltage generating circuit 9 is used as a circuit for supplying the erasing power supply voltage Vep to the sources of the transistors Q93, Q94 and Q96.

At the time of the erase operation, the memory cell transistor (M
When the voltage applied to the source of (11-Mmn) is constant, the erasing speed decreases with a decrease in temperature, that is, the time required to change from the threshold voltage in the writing state to the threshold voltage in the erasing state. In the second embodiment, the voltage applied to the source of the memory cell transistor (the erasing source voltage Vs) is high at low temperatures and low at high temperatures. The temperature coefficients of the resistors R3 and R4 of the reference voltage generator 91 are set so as to have a negative temperature characteristic with respect to the temperature change.
Set the resistance value.

In the second embodiment, the activation energy Eo of the resistor R4 is set to 0.2 eV and R3 is set to 0.1 eV, so that the temperature dependence of the resistor R4 is made larger than that of R3. Adjust width and length to R4 =
The temperature characteristics shown in FIG. 5 are set with 9 MΩ and R3 = 1 MΩ, and the erasing power supply voltage Vep and the erasing source voltage Vs of the temperature resistance shown in FIG. 6A are obtained ( The operation of the erasing power supply voltage generating circuit 92 is substantially the same as the operation of the writing drain voltage generating circuit 7 of the first embodiment, and thus will not be described.

By supplying the erasing source voltage Vs having such temperature characteristics to the source of the memory cell transistor, the electric field between the source and the floating gate at a low temperature is increased to increase the FN tunneling current, The amount of change in the erasing time can be reduced to about 1.3 times as shown in FIG. 6B, compared to the conventional example which was about twice between 0 ° C. and 100 ° C. Therefore, even if the application time of the erasing source voltage Vs to the source of the memory cell transistor is kept constant, the threshold voltage of the memory cell transistor after the erasing operation can be made to fall within a predetermined range, resulting in an over-erased state. Can be prevented from occurring, and stable erase characteristics can be obtained with respect to a temperature change.

In these embodiments, the resistors R1 to R1
Although the activation energy of R4 is set to 0.1 eV and 0.2 eV, the present invention is not limited to this, and a reference voltage having a desired temperature characteristic is generated by setting the resistance value arbitrarily, and writing is performed. The temperature dependence of the speed (writing time) and the erasing speed (erasing time) can be controlled. Also,
The resistor may be made of a material other than polycrystalline silicon. In short, the resistor may be formed of a material that can use the difference in activation energy.

Further, in these embodiments, the flash memory type in which all the memory cell transistors of the memory cell array 1 are collectively erased is used. However, the present invention is not limited to this, and other types of EPROM, EEPROM, etc. The present invention can be applied to any configuration in which data is written and erased by electrically changing the threshold voltage. Further, the present invention can be applied only to the erase source voltage generation circuit.

[0051]

As described above, according to the present invention, during a write operation, a write drain voltage pulse signal of a voltage level having a predetermined temperature characteristic is generated and applied to the drain of the memory cell transistor. Time required to change from the threshold voltage in the initial state and erase state to the threshold voltage in the write state (write time)
Since the amount of change with respect to temperature change was reduced,
Even if the pulse width of the write drain voltage pulse signal is fixed, the threshold voltage of the memory cell transistor after the write operation can be made to fall within a predetermined range, so that the temperature change can be performed without lowering the write operation speed. In addition, a stable writing operation can be obtained, and at the time of erasing operation, an erasing source voltage having a predetermined temperature characteristic is generated and applied to the source of the memory cell transistor. Since the amount of time (erasing time) required to change from the threshold voltage to the threshold voltage in the erased state with respect to the temperature change is reduced, the time for applying the erasing source voltage to the source of the memory cell transistor is reduced. Even if the threshold voltage is kept constant, the threshold voltage of the memory cell transistor after the erasing operation can be kept within a predetermined range. It is possible to prevent the occurrence of the erase such an effect can be obtained a stable erasing characteristics with respect to temperature changes.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a temperature characteristic diagram of a resistance of a reference voltage generating unit of the embodiment shown in FIG.

FIGS. 3A and 3B are a temperature characteristic diagram of a reference voltage and a characteristic diagram for explaining an effect of reducing an amount of change with respect to a temperature change of a writing time according to the embodiment shown in FIG. 1;

FIG. 4 is a circuit diagram of a main part of a second embodiment of the present invention.

FIG. 5 is a temperature characteristic diagram of the resistance of the reference voltage generating unit of the embodiment shown in FIG.

6A and 6B are a temperature characteristic diagram of an erasing source voltage and a characteristic diagram for explaining an effect of reducing a change amount of an erasing time with respect to a temperature change in the embodiment shown in FIG. 4;

FIG. 7 is a circuit diagram showing an example of a conventional nonvolatile semiconductor memory device.

FIG. 8 is a sectional view showing a structure of a memory cell transistor used in the nonvolatile semiconductor memory device.

9 is a characteristic diagram illustrating a change amount of a writing time with respect to a temperature change, for describing a problem of the nonvolatile semiconductor memory device illustrated in FIG. 7;

10 is a characteristic diagram showing a change amount of an erasing time with respect to a temperature change, for explaining a problem of the nonvolatile semiconductor memory device shown in FIG. 7;

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 memory cell array 2 row select circuit 3 column decoder 4 column select circuit 5 block decoder 6 block select circuit 7, 7x write drain voltage generator 8 write circuit 9, 9x erase source voltage generator 71, 91 reference voltage generator 92 Power supply voltage generation circuit for erasing DL1 to DLn Digit line M11 to Mmn Memory cell transistor R1 to R4, R1x, R2x Resistance WL1 to WLm Word line

Claims (4)

(57) [Claims] 1. A memory cell array in which memory cell transistors for writing and erasing data by electrically changing a threshold voltage are arranged in a plurality of rows and a plurality of columns, and a plurality of columns of the memory cell transistors are associated with the memory cell transistors. A plurality of digit lines provided and connected to the drains of the memory cell transistors in the corresponding columns; column selecting means for selecting a predetermined digit line among the plurality of digit lines during a write operation; and a power supply voltage of a predetermined level. A write including a reference voltage generator for generating a reference voltage, generating a write drain voltage pulse signal having a predetermined pulse width at a voltage level corresponding to the reference voltage, and supplying the write drain voltage pulse signal to the digit line selected by the column selecting means; Drain voltage supply means;
An erase source voltage generating means for generating an erase source voltage during an erase operation and supplying the source voltage to all the memory cell transistors of the memory cell array; A circuit for generating the write drain voltage pulse signal at a voltage level having a predetermined temperature characteristic during a write operation; and a reference included in the write drain voltage supply means.
The voltage generating section receives a predetermined level of power supply voltage at one end, and
A first resistor having a first resistance value having a temperature characteristic of 1;
Is connected to the other end of the first resistor, and the other end is connected to the ground potential point.
And a second temperature characteristic different from the first temperature characteristic.
And a second resistor having a second resistance value.
From the connection point of the two resistors, a reference voltage having a predetermined temperature characteristic
A non-volatile semiconductor storage device, wherein the non-volatile semiconductor storage device is a circuit for generating . 2. The first and second resistors of the reference voltage generating section are formed so as to have different activation energies and have a predetermined resistance value, and have different temperature characteristics and a predetermined resistance value. 2. The nonvolatile semiconductor memory device according to claim 1, wherein: 3. The method according to claim 1 , wherein the threshold voltage is electrically changed to obtain data.
Memory cell transistors for writing and erasing data
A memory cell array arranged in rows and a plurality of columns;
Provided corresponding to each of a plurality of columns of cell transistors.
Connect to the drain of the memory cell transistor in the corresponding column
A plurality of digit lines, and the plurality of digit lines during a write operation.
A column that selects a given digit line from the digit lines
Selecting means for generating a reference voltage from a predetermined level of the power supply voltage;
Conductive and the corresponding pre-Symbol reference voltage includes a reference voltage generator for life
Drain voltage for writing with predetermined pulse width at voltage level
A pulse signal is generated, and a pulse selected by the column selection means is generated.
Writing drain voltage supply means for supplying the write line,
During the erase operation, an erase source voltage is generated and the memory
To the source of all memory cell transistors in the array.
Non-volatile semiconductor device having an erase source voltage generating means for supplying
In the conductor storage device, the write drain voltage supply
Means for applying a voltage level having a predetermined temperature characteristic during a write operation.
For generating the write drain voltage pulse signal
A predetermined path at one end to the erasing source voltage generating means.
A third resistor having a third temperature characteristic receiving the power supply voltage of the bell;
And one end connected to the other end of the third resistor, and the other end grounded.
A fourth temperature different from the third temperature characteristic, which is connected to the
A fourth resistor having a fourth resistance value having characteristics.
Generate reference voltage for erasing from connection point of 3rd and 4th resistors
An erasing reference potential generating section for performing the erasing reference potential generation.
Generates erase source voltage at voltage level corresponding to voltage
A non-volatile semiconductor storage device characterized by the above . 4. The third and fourth resistors of the erasing reference voltage generating section are formed so as to have different activation energies and have a predetermined resistance value, and to have different temperature characteristics and predetermined resistance values. 4. The nonvolatile semiconductor memory device according to claim 3, wherein said nonvolatile semiconductor memory device has a resistance.