JP2924766B2 - Hold time error elimination method and method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and a method for removing a hold time error in a layout design of an LSI (integrated circuit), a PWB (printed wiring board) or the like.
In particular, the present invention relates to a layout design method and method for removing a hold time error of a logic circuit.

[0002]

2. Description of the Related Art In a conventional layout system,
It is generally assumed that automatic placement and routing processing is performed based on logical connection information for the purpose of shortening the total wiring length and improving wiring properties, and a path hold time error occurs in delay analysis after placement and routing. In such a case, the hold time error is removed by manually correcting the placement and routing, or by correcting the logic and laying out the layout again. Alternatively, a delay gate (delay gate) is inserted in advance in the logic design stage to prevent a hold time error. In addition, about the conventional layout method, the publication (Yukizo Kinoshita (editor), IPSJ published,
"CAD for Logic Devices", published March 20, 1981, pp. 30-62).

[0003]

A first problem in the above-mentioned conventional layout method is that automatic layout and wiring processing is performed based on only logical connection information for the purpose of shortening the total wiring length and improving the wiring property. Is what is happening.

As described above, when the automatic placement and routing process is performed based only on the logical connection information, a hold time error may occur in a path with a large skew or a path with a small delay time by delay analysis after the placement and routing. is there.
As a conventional technique relating to delay analysis of a minimum delay time error or the like, Japanese Patent Laid-Open Publication No. Hei 5-6405 discloses that an error path whose data path minimum delay time is less than a limit value has a maximum error path delay time limit. In order to provide a correction means in which the minimum delay time of the error path is equal to or greater than the limit value while maintaining the value equal to or less than the value, in order to guarantee the minimum delay time while considering the increase in the maximum delay time due to the insertion of the delay buffer. By finding the optimal combination of the type and number of delay buffers to be inserted into the error path, a minimum delay time error is guaranteed, and a new problem caused by useless delay buffer insertion (for example, occurrence of a maximum delay time error) is prevented. A configuration of the delay analysis device described above has been proposed. A similar prior art is disclosed in Japanese Patent Laid-Open No. 4-309179.
In order to provide an automatic correction system for the minimum delay time error, Japanese Patent Laid-Open Publication No. H10-15083 discloses an error in which the minimum delay time is determined to be less than the limit value in order to guarantee the minimum delay time for each error path. A system has been proposed in which the type and number of delay buffers to be inserted into an error path are selected in order to guarantee a minimum delay time based on a difference between a path and a limit value.

Further, in the above-mentioned conventional method, it is necessary to avoid the generated hold time error by manually correcting the placement and routing results, or to correct the logic design and to perform the placement and routing again. Therefore, there is a problem that a large number of man-hours are required for repair work and re-arrangement and wiring.

Further, when a delay gate is inserted in advance in the logic design stage, the wiring length is estimated only from the logical connection information, and the delay gate is inserted into a path that may cause a hold time error. Therefore, there is a problem that the delay gate is inserted more than necessary and the accommodation capacity of the layout is deteriorated.

Accordingly, the present invention has been made in view of the above-mentioned problems of the prior art, and an object of the present invention is to generate a path with a large skew or a path with a small delay time by delay analysis after placement and routing. It is an object of the present invention to provide a method and a method of automatically eliminating a hold time error, thereby eliminating the need for manual correction of the hold time error and the number of work steps required to perform a logical correction and re-layout.

Further, the present invention provides a method and a method for avoiding deterioration of layout accommodation by inserting delay gates more than necessary in a path in order to remove a hold time error in a logic design stage. The aim is to provide a method .

[0009]

In order to achieve the above object, a hold time error elimination method according to the present invention comprises:
In the layout design of SI, PWB, etc., logical connection information between blocks constituting a circuit, physical information of a block arrangement result and a wiring result of connection between blocks, parameters for calculating a block internal delay and wiring delay required for delay analysis, etc. Logic / library input means for inputting delay information of the following, and path delay constraint input means for inputting a delay time limit value of (a minimum delay time limit and a maximum delay time limit) of a path defining a target performance of the circuit. A path skew calculating means for performing a delay analysis of a path, a clock skew calculating means for extracting a path constituting a clock net and obtaining a clock skew using the path delay analyzing means, and the path delay analyzing means, Perform path delay analysis taking into account the clock skew calculated by the clock skew calculation means and perform a hold time error. Hold time error detection means for detecting a path causing a minimum delay time error) and a maximum delay time error for a net on the path having a hold time error detected by the hold time error detection means. Delay gate inserting means for selecting and inserting a delay gate capable of removing a hold time error within a range that does not occur, and delay gate disposing means for disposing the delay gate inserted by the delay gate inserting means at a position where a hold time error can be avoided. Incremental wiring means for rewiring a net that needs to be changed due to the arrangement of the inserted delay gates, and output means for outputting a placement and routing result;
And control means for controlling each of the means.

Further, according to the present invention, there is provided a virtual wiring estimating means for estimating a virtual wiring of each net from an arrangement result when the logical / library input means according to the first aspect of the present invention does not input a wiring result of connection between blocks. Having path delay analysis means for performing path delay analysis using the virtual wiring,
A configuration in which only the arrangement result is output without using the incremental wiring means may be adopted.

[0011]

According to the present invention, in consideration of the clock skew calculated by the clock skew calculating means, the path delay analyzing means performs a path delay analysis based on the placement and routing results.
The hold time error detection means detects the hold time error (minimum delay time error) of the path, and the delay gate insertion means does not cause the maximum delay time error for the net on the path where the error has occurred. The delay gate arranging means arranges the selected delay gate at a position where the hold time error can be avoided, and inserts the delay gate at a position where the hold time error can be avoided. By re-wiring the nets that need to be changed due to the arrangement of the delay gates, the arrangement and wiring results from which the hold time error has been eliminated can be automatically obtained.

According to the present invention, the delay gate inserting means inserts as many delay gates as necessary on the basis of the actual arrangement and wiring results, thereby minimizing the deterioration of wiring accommodation. .

Further, according to the present invention, the delay gate arranging means and the incremental wiring means perform incremental arrangement and wiring correction on the initial layout result, so that the time required for error removal is short and no new hold time error occurs. .

[0014]

FIG. 1 is a block diagram showing the configuration of an embodiment of a hold time error elimination system according to the present invention. Referring to FIG. 1, in the present embodiment, logical connection information 111 between blocks constituting a circuit, physical information 112 of a block arrangement result and a wiring result of connection between blocks, a block internal delay and wiring required for delay analysis Logic / library input means 102 for inputting delay information 113 such as delay calculation parameters, and delay time constraint information (minimum delay time limit, maximum delay time limit) 11 for the path that defines the target performance of the circuit
3, a path delay constraint input means 103 for inputting a clock signal 3, a path delay analysis means 104 for delay analysis of a path, and a clock skew calculation means for extracting a path constituting a clock net and obtaining a clock skew using the path delay analysis means 104. A hold for detecting a path causing a hold time error (a violation of a minimum delay time constraint) by performing a path delay analysis in consideration of the clock skew calculated by the clock skew calculation means using the path delay analysis means and the path delay analysis means. Time error detecting means 106 and a delay gate capable of removing a hold time error within a range that does not cause a maximum delay time error for a net on a path having a hold time error detected by the hold time error detecting means 106 Select and insert delay gate Means 107, delay gate arranging means 108 for arranging the delay gate inserted by delay gate inserting means 107 at a position where a hold time error can be avoided, and rewiring for a net which needs to be changed by the arrangement of the inserted delay gate. , An output unit 110 that outputs placement and routing result information 115, and a control unit 101 that controls these units.

A clock driver 20 as shown in FIG.
1. A part of a logical connection relationship composed of clock buffers 202 to 205, flip-flops (FF) 206 and 207, gate 208, and nets 209 to 218 connecting these blocks will be described as an example. Although the example shown in FIG. 2 shows a part of the logic, the arrangement line processing is performed for the whole. In the example of the logical connection shown in FIG. 2, a path 312 exists as a path between flip-flops.

Here, layout processing is performed by taking as an example a case where the maximum delay time limit of all the paths between flip-flops is "20T"("T" is a unit of time) and the minimum delay time limit is "5T". Shall be.

When the conventional layout method is used, automatic placement and routing processing for the purpose of shortening the total wiring length and improving the wiring property is performed based on the logical connection information.
It is assumed that the placement and routing result as shown in FIG. 3 is obtained. Here, in the conventional method, since the delay time limitation is not particularly taken into consideration, the result of the delay analysis after the placement and routing indicates that the flip-flop (FF) 206-the flip-flop (F
F) Assuming that the delay time of the path 312 between 207 is “5T” and the clock skew is “−1T”,
From the following equation (1), the minimum delay time constraint is violated (the hold time is not satisfied).

5T + (− 1T) = 4T <5T (1)

In the hold time error elimination system according to one embodiment of the present invention, the following units are executed under the control of the control unit 101 shown in FIG.

First, the logic / library input means 102
Are logical connection information 111 between blocks, physical information 112 such as a block arrangement result and a wiring result of inter-block connection, and arrangement and wiring result information 115, and delays such as internal delays required for delay analysis and parameters for calculating a wiring delay. Information 11
Enter 3. Each input information is referred / updated by each means as described later.

As the placement and routing result information 115, for example, the placement and routing result shown in FIG. 3 is input. Thereafter, the path delay constraint input unit 103 inputs “20T” in this example as the maximum delay time constraint of the path and “5T” as the minimum delay time constraint as path delay constraint information 114.

Next, the clock skew calculating means 105 calculates the clock skew between all the flip-flops having the path connection by using the path delay analyzing means 104.

In the example shown in FIG.
1 from the output pin P1 to the clock buffers 202 and 204.
And the delay time of the path leading to the clock input pin P10 of the flip-flop 206 via the clock driver 20.
1 from output pin P1 to clock buffers 203 and 205
, The delay time of the path leading to the clock input pin P16 of the flip-flop 207 via the clock is obtained, and “−1T”, which is the time difference, is calculated as the clock skew.

Next, the hold time error detecting means 106 calculates the delay time of each inter-flip-flop path by using the path delay analyzing means 104, and adds the clock skew obtained by the clock skew calculating means 105.
By comparing with the minimum delay time constraint of the path delay constraint information 114, a path causing a hold time error (a violation of the minimum delay time constraint) is detected.

In the example shown in FIG. 3, as a result of the conventional method, the path 312 is connected to the flip-flop 2 as described above.
In the area between 06 and the flip-flop 207, "5T" and the clock skew "-1T", 5T + (-1T) = 4T <5T, and it is detected that a hold time error has occurred.

The delay gate inserting means 107 selects and inserts a delay gate necessary for removing the hold time error with reference to the delay information 113, and updates the logical connection information 111.

As shown in FIG. 4, for example, as shown in FIG. 4, a plurality of delay gates registered in the delay information 113 are used as delay gates to be inserted into the path 312.
A delay gate 4 that does not exceed the maximum delay time limit 20T and satisfies the minimum delay time limit "5T".
02 is selected and inserted. Since the circuit delay time of the delay gate 402 is “2T”, the path 312 after insertion is
Is (6T) from the following equation (2), and it is expected that the hold time error can be removed.

[0028]

It should be noted that the actual delay time cannot be simply added, and it is difficult to accurately obtain the delay time only after the placement and routing. Therefore, the delay gate is selected with some margin.

If it is detected in the subsequent processing that the prediction here has failed and the delay gate selection has failed, the selection is performed again.

In this example, the delay gate inserting means 10
7, the logical connection information 111 is updated as shown in FIG.

The inserted delay gate (here, “delay gate” is a function name) 402 has a name (block name) “gate 503” and is inserted into the net 217 in FIG. The nets 501 and 502 are newly generated by dividing the nets 501 and 502. That is, as shown as logical connection information in FIG. 5, a delay gate 5 having a delay time of “2T” is provided after the gate 208 between the data paths of the flip-flops 206 and 207.
03 is inserted.

When the logical connection information is updated, the wiring result 310 of the net 217 in FIG. 3 is deleted from the placement and wiring result, and the result is as shown in FIG.

Next, the delay gate arrangement means 108
The gate 503 inserted as a delay gate is shown in FIG.
As shown in (2), it is arranged at a position where it is expected that the hold time error can be removed.

In this example, the circuit is arranged on the path of the removed wiring result 310. However, if the circuit delay time of the inserted delay gate is short, it is arranged at a position to bypass the wiring to reduce the delay. It can also occur.

In the arrangement example shown in FIG.
There is no wiring of other nets at the arrangement position of 03, but if wirings of many nets are present, wirings that cause wiring short-circuits or violation of wiring prohibition are deleted.

After that, the incremental wiring means 109
Is an unwired net, in this case,
Wiring of nets 501 and 502 is performed, and as shown in FIG.
1, 802 are obtained.

FIG. 9 is a block diagram showing the configuration of another embodiment of the hold time error elimination system of the present invention. The difference from the embodiment shown in FIG. 1 is that a virtual wiring estimation unit 904 is added, and the incremental wiring unit 10
9 is removed, and the placement and routing result information 115 is removed.
Is replaced by the arrangement result information 915.

In the above-described embodiment, the path delay analysis means 104 performs a delay analysis using the actual wiring result, and finally the wiring is output by the incremental wiring means 109 to output the arrangement and wiring result.

On the other hand, in the method of the present embodiment, the virtual wiring estimating means 904 shown in FIG. 9 estimates the virtual wiring using the result of only the placement, and uses this to estimate the path delay analyzing means 905. Performs delay analysis, calculates clock skew, inserts a delay gate, and then places a delay gate. In particular, it is a method used in the initial stage of design before entering detailed design.

[0041]

As described above, according to the present invention,
There is an effect that a placement and routing result from which a hold time error has been removed can be automatically obtained.

According to the present invention, the path delay analyzing means performs the path delay analysis based on the placement and routing results in consideration of the clock skew obtained by the clock skew calculating means, and the hold time error detecting means performs the hold of the path. A time error (minimum delay time error) is detected, and the delay gate insertion means selects a delay gate that can avoid a hold time error within a range that does not cause a maximum delay time error for a net on the path where the error occurs. The delay gate placement means places the delay gate at a position where a hold time error can be avoided, and the incremental wiring means performs rewiring for a net that needs to be changed due to the delay gate placement.

Further, according to the present invention, there is an effect that the deterioration of the wiring accommodating property due to the addition of the delay gate inserted for improving the hold time error can be minimized. This is because only a delay gate necessary for removing a hold time error is inserted.

Further, according to the present invention, there is an effect that the time required for removing the hold time error is short and no new hold time error occurs. This is for performing an incremental placement and routing process on the initial layout result.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is an example of logical connection information for describing an embodiment of the present invention.

FIG. 3 is a diagram illustrating an example of a placement and routing result according to a conventional technique for the logical connection information of FIG. 2;

FIG. 4 is a diagram for explaining an embodiment of the present invention, and is a diagram illustrating an example of a delay gate that is selected and inserted by a delay gate inserting unit.

FIG. 5 is a diagram for explaining an embodiment of the present invention. FIG. 5 is a diagram illustrating a logic of a result of inserting a delay gate by the delay gate inserting unit according to the embodiment of the present invention with respect to the logical connection information of FIG. FIG. 7 is a diagram illustrating an example of connection information.

FIG. 6 is a diagram for explaining one embodiment of the present invention, and is a diagram showing an example of a wiring result deleted by the delay gate inserting unit in one embodiment of the present invention.

FIG. 7 is a diagram for explaining an embodiment of the present invention, and is a diagram showing an example of an arrangement result in which delay gates are arranged by a delay gate arranging unit in one embodiment of the present invention;

FIG. 8 is a diagram for explaining one embodiment of the present invention, and is a diagram showing an example of a wiring result by the incremental wiring means in one embodiment of the present invention.

FIG. 9 is a block diagram showing a configuration of another embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 101 control means 102 logic / library input means 103 path delay constraint input means 104 path delay analysis means 105 clock skew calculation means 106 hold time error detection means 107 delay gate insertion means 108 delay gate placement means 109 incremental wiring means 110 placement / wiring results Output means 112 Physical information 113 Delay information 114 Path delay constraint information 115 Arrangement and wiring result information 201 Clock driver 202 to 205 Clock buffer 206, 207 Flip-flop 208 Gate 211 to 217 Net 301 to 306, 308 to 311 Wiring result 312 Path 401 to 401 404 delay gate 503 gate 801, 802 wiring result 904 virtual wiring estimation means

Claims (4)

(57) [Claims] 1. In a layout design of an LSI, a PWB or the like, logical connection information between blocks constituting a circuit, physical information of a block arrangement result and a wiring result of connection between blocks, a block internal delay and wiring required for delay analysis. Logic / library input means for inputting delay information such as delay calculation parameters, minimum delay time limitation of a path for defining a target performance of a circuit,
Path delay constraint input means for inputting a delay time limit value, and a maximum delay time limit; a path delay analysis means for performing path delay analysis; and a path for forming a clock net and extracting the path by using the path delay analysis means. A clock skew calculating means for obtaining a clock skew, and a path delay analysis in consideration of the clock skew obtained by the clock skew calculating means by using the path skew calculating means, and a hold time error (ie, a minimum delay time error). Hold time error detecting means for detecting a path that has caused a hold time error, and a hold time within a range that does not cause a maximum delay time error with respect to a net on a path having a hold time error detected by the hold time error detecting means. Select and insert a delay gate that can eliminate errors Delay gate inserting means, delay gate arranging means for arranging the delay gate inserted by the delay gate inserting means at a position where a hold time error can be avoided, and a net which needs to be changed depending on the arrangement of the inserted delay gate. A hold time error elimination method comprising: an incremental wiring means for performing rewiring; an output means for outputting a placement and routing result; and a control means for controlling each of the means. 2. A virtual wiring estimating means for estimating a virtual wiring of each net from an arrangement result when the logic / library input means does not input a wiring result of inter-block connection, and a path delay using the virtual wiring. 2. The hold time error elimination method according to claim 1, further comprising a path delay analysis unit for performing an analysis, and outputting only the arrangement result without using the incremental wiring unit. 3. A clock skew obtained from a delay analysis of a clock path between flip-flops of a clock distribution system circuit extracted from a result of arrangement and wiring of a logic circuit in a layout design method of an LSI, a PWB, or the like; And the delay time of the data path between
It is determined whether or not a predetermined minimum delay time is violated (referred to as “hold time error”), and the hold time error is determined from a plurality of delay gates registered in advance for the path where the hold time error is detected. Select a delay gate that resolves and satisfies the predetermined maximum delay time constraint and inserts it into the net on the corresponding logical connection. The delay gate is automatically arranged at a position where the hold time error can be avoided, and the incremental wiring means performs rewiring for a net that needs to be changed due to the arrangement of the delay gate, thereby eliminating the hold time error. And a method of automatically outputting a wiring result. 4. A clock skew obtained from a delay analysis of a clock path between flip-flops of a clock distribution system circuit based on virtual wiring from a layout result of a logic circuit in a layout design method of an LSI, a PWB or the like, and From the delay time of the data path between, the violation of the predetermined minimum delay time ("hold time error"
Is determined, and the hold time error is eliminated from a plurality of delay gates registered in advance for the path where the hold time error is detected, and the predetermined maximum delay time constraint is satisfied. A method for removing a hold time error, wherein a delay gate is selected and inserted into a net on a corresponding logical connection, and the delay gate is automatically arranged at a position where the hold time error can be avoided.