JP2920998B2 - Semiconductor integrated circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly, to a test circuit for measuring rise and fall times of an output buffer.

[Prior Art] In a conventional semiconductor integrated circuit, a measurement terminal is connected to a dedicated test device to measure a rise and fall time of an output buffer.

[Problem to be Solved by the Invention] In the conventional measuring method described above, since the output terminal of the output buffer, which is the terminal to be measured, needs to be connected to the dedicated test device, the load capacity of the dedicated test device is inevitably loaded. There is a drawback that the rise and fall time characteristics with respect to the load capacity cannot be measured accurately, and that the test time becomes longer because the rise and fall time characteristics of the output buffer are measured after performing a functional test. is there.

An object of the present invention is to provide a semiconductor integrated circuit that can determine whether the characteristics of the rise and fall times of an output buffer satisfy a standard without connecting the output buffer to a dedicated test device and simultaneously performing a functional test. To provide.

[Means for Solving the Problems] A semiconductor integrated circuit according to the present invention includes a Schmitt trigger circuit that inputs an output of an output buffer, a test terminal to which a test signal is applied, and a sampling clock input terminal to which a sampling clock is input. A plurality of master-slave latch circuits with reset are connected in series, and when a test signal is applied to a test terminal, the reset is released and the output of the Schmitt trigger circuit is latched to the latch circuit by a sampling clock. When the test signal is applied to the sampling result output terminal for outputting the sampling result of the output buffer from the shift register and the test terminal, the sampling clock input to the sampling clock input terminal is input to each latch circuit of the shift register. Means to make You.

[Operation] When a test signal is applied to the test terminal to put the semiconductor integrated circuit into a test state and a sampling clock is input from the sampling clock input terminal, the sampling result obtained by latching the output of the Schmitt trigger circuit in the shift register is output to the sampling result output terminal. Is done. By checking this sampling result with a dedicated test device,
The rise / fall time of the output buffer can be measured. The reason why the Schmitt trigger circuit is used is that the criterion for determining the output potential of the output buffer differs between rising and falling.

Example Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of a main part of a semiconductor integrated circuit according to one embodiment of the present invention.

P-channel transistor 2a and N-channel transistor
An output buffer 3 is constituted by 2b. A signal from an internal logic circuit (not shown) is input through the inverter 1 and output to the output terminal 20. The output of the output buffer 3 is output via the Schmitt trigger circuit 4. A master-slave latch circuit with reset (the reset signal is at a high potential during a reset period, and the latch circuit output at that time is at a low potential).
Is connected. From the test terminal 21, a test signal T for controlling whether the output buffer is set to the test state or the operation state is input. The sampling clock input terminal 22 is a terminal for inputting the sampling clock X, is connected to each clock input terminal Cp of the shift register 13 via the transfer gate 15, and is connected to the internal logic circuit via the transfer gate 16. The sampling result output terminal 23 is connected to the output terminal Q of the shift register 13 via the transfer gate 17 and to the internal logic circuit via the transfer gate 18. An N-channel transistor 14 is connected between each clock input terminal Cp of the shift register 13 and the ground. The test terminal 21 is connected to the gates of the transfer gates 15 and 17, and the transfer gate 1 is connected via an inverter 19.
6, 18, the gates of the N-channel transistor 14 and the reset terminals R of the master-slave latch circuits 5-12 with reset. When the test signal T is at a low potential (hereinafter referred to as “L”), the transfer gates 18 and 16 conduct and the transfer gates 17 and 15 do not conduct, so that the terminals 23 and 22 are used as normal output terminals of the integrated circuit. Is done. At this time, the N-channel transistor 14 is turned on, and the clock input Cp of the shift register 13 is fixed at “L”. Next, when the test signal T is at a high potential (hereinafter referred to as “H”), that is, in the test state, the transfer gate 1
5 and 17 conduct, and the transfer gates 16 and 18 become non-conductive. In this case, a sampling clock X required to latch a change in the output waveform of the output buffer 3 into the shift register 13 can be input from the sampling clock input terminal 22. The output Q of the shift register 13 is connected to the sampling result output terminal 23, so that a sampling result E of rising and falling time characteristics can be output. Then N
Channel transistor 14 is non-conductive.

FIG. 2 shows the waveforms of various parts when the circuit of FIG. 1 is in a test state. In particular, FIG. 2 shows a case where the rise time characteristic of the output buffer 3 is sampled and the sampling result is output ing.

The waveform A in FIG. 2 (3) is an ideal waveform when there is no delay of the internal element and there is no capacitance at the output terminal 20. However, actually, the waveform rises as shown in FIG. 2 (5) due to the delay of the internal element and the load capacitance of the output terminal 20.
When the waveform D of FIG. 2 (5) is input to the Schmitt trigger circuit 4, the output B of the Schmitt trigger circuit 4 becomes a waveform of FIG. 2 (6). The reason why the waveform of the output terminal 20 is changed to the waveform of FIG. 2 (6) is that the input standard of the external circuit is set to “H”.
Assuming 2.0V at the time and 0.7V at the time of 'L', the output potential becomes 'L' →
When the output circuit changes to 'H', the external circuit recognizes it as 'H' at 2.0V or more.When the output potential changes from 'H' to 'L', the external circuit recognizes 'L'. This is because the output voltage is 0.7 V or less, and the criterion for determining the output potential is different between rising and falling.

When the rising timing of the ideal waveform and the change timing of the test signal are simultaneously changed as shown in FIGS. 2 (2) and (3), the reset signal of the shift register 13 changes from “H” to “L”,
At the same time, the sampling clock X is applied to the sampling clock input terminal 22 and input to the shift register 13. The output B of the Schmitt trigger circuit 4 is latched in the shift register 13 at the rising timing of the sampling clock X.
The data latched in the shift register 13 enters the sampling result output period from the eighth pulse of the sampling clock C (FIG. 2 (4)) because the shift register 13 is an eight-stage shift register. In the sampling result output period, the result held in the shift register 13 during the sampling value latch period is extended by increasing the period of the sampling clock (FIG. 2 (4)) (the sampling input from the sampling clock input terminal 22). The sampling result E is output from the sampling result output terminal 23. Here, the reason for lengthening the cycle of the sampling clock X is that the waveform of the sampling result output terminal 23 may be rounded because a dedicated test device is connected to the sampling clock output terminal 23, and the rounding of the waveform may occur. It is necessary to lengthen the cycle of the C waveform to a negligible extent. An example in which the sampling result E is output from the sampling result output terminal 23 will be specifically described below. The sampling time when the pulse width of the sampling clock is 10 ns is shown below the waveform in FIG. 2 (7). When the waveform of FIG. 2 (5) is 2.0V, the waveform of FIG.
Since it changes to “H”, it changes from “L” to “H” during the sampling time of 70 ns and 90 ns. At the rising edge of the eighth pulse of the waveform in FIG. 2 (4), the data of each of the latch circuits 5 to 12 of the shift register 13 stores “H” in the latch circuits 12, 11, and 10, and latch circuits 9, 8, and 7. , 6 hold 'L'. The held result (sampling result E) is sequentially output from the sampling result output terminal 23 with the sampling clock C as shown in FIG. The rise time can be determined by checking the above sampling result E with a dedicated test device.

What has been described above is the rise time of the output buffer 3. In the case of the fall time, the fall time can be determined by the same method except that the fall determination potential of the Schmitt trigger circuit 4 is changed. .

〔The invention's effect〕

As described above, according to the present invention, by inputting a sampling clock from an input terminal in a test state, it is possible to check whether the rise and fall times of the output buffer have desired characteristics. Can be checked without connecting to dedicated test equipment,
Further, if the check of the present invention is added to the test pattern for the function test of the dedicated test apparatus, there is an effect that the test time can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram of a semiconductor integrated circuit according to one embodiment of the present invention, and FIG. 2 is a waveform diagram showing waveforms at various parts in the embodiment of FIG. 1, 19 Inverter 2a P-channel transistor 2b N-channel transistor 3 Output buffer 4 Schmitt trigger circuit 5-12 Master-slave latch circuit with reset 13 Shift register 5-18 Transfer gate 20 Output terminal 21 Test terminal 22 Sampling clock input terminal 23 Sampling result output terminal

Claims (1)

(57) [Claims] 1. A semiconductor integrated circuit, comprising: a Schmitt trigger circuit for inputting an output of an output buffer; a test terminal to which a test signal is applied; a sampling clock input terminal for inputting a sampling clock; Are connected in series, and when a test signal is applied to the test terminal, the reset is released and the output of the Schmitt trigger circuit is latched in the latch circuit by the sampling clock, and the output buffer from the shift register And a means for inputting a sampling clock input to a sampling clock input terminal to each latch circuit of the shift register when a test signal is applied to the test terminal. Feature Conductor integrated circuit.