JP2919871B2 - Method and apparatus for reconstructing a color burst signal of a color television video signal - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Color television systems PAL or SECAM use composite video signals for video transmission. The composite video signal comprises a pure sine wave signal, referred to as a color burst signal (hereinafter referred to as chrominance), at the rear of each line synchronization pulse, over a line of the line of elimination. With the initial frequency and phase of the color subcarrier modulated by the effective portion of the line. This chrominance is used at the beginning of each line to synchronize the demodulated subcarrier of the chrominance signal at the receiver.

In order for the receiver to be able to accurately recover the phase due to the color subcarrier by chrominance under any circumstances, the chrominance should be included in the CCIR report 624, especially regarding the chrominance output point relative to the beginning of the line sync pulse. Satisfies the requirements described and splits the phase (rupture de phas
e) must be formed of a pure sine wave signal without. However, the video signal may actually be subjected to multiple processing before it is received by the receiver, which is becoming more and more frequent. These processes include, for example, writing to a magnetic medium, crypto-type television broadcasting (
Conversion of digital signal to pseudo-random signal (embrouil) in case of mission de tlvison crypte
lage) and the operation of restoring the converted signal to its original form (dsembrouillage), etc. Such processing significantly reduces the quality of the video signal at the level of chrominance, and depending on the receiver, At the beginning, it becomes impossible to recover the phase of the color subcarrier exactly. As a result, the fringe effect (effets de fran
ges) appears and the screen becomes very difficult to see.

These fringes are particularly useful in SECAM systems, where transmission using a composite video signal with a certain amount of delay that causes the effective portion of each line to be displaced with respect to a line synchronization pulse in accordance with a particular code, using remote projection (tl- proj
ection) Appears on the device. That is, in order to perform such encryption, a composite video signal that is not delayed is selected each time a line synchronization pulse appears, and after chrominance is completed, a composite video signal having a desired delay is started before the effective video portion starts. It is common to switch to a video signal, but when these operations are performed, the chrominance is extended by a delay time, and a phase jump (saut de phase) occurs at the time of the switching,
The rhythm of the encoding will produce a fringe that moves the left edge of the screen.

It is an object of the present invention to overcome the disadvantages by restoring the position of the chrominance relative to the beginning of the line sync pulse and the spectral purity of these chrominances.

To achieve the above object, according to the present invention, there is provided a method for recalibrating a color burst signal of a video signal of a color television, wherein the video signal is sampled, one of which simultaneously writes and the other of which reads. Storing the samples of the video signal in two randomly addressed memory plans that function in parallel with each other, such that the functions of the memory plan are exchanged at the end of a time interval corresponding to the duration of one line. So that
The samples of each memory plan are read according to the chronological order of writing, except that the distortion-shifted samples (sample 94 to sample 130) appearing during the transition spanning around the start of the color burst signal are read. Instead, for the portion before the start of the color burst signal, the sample immediately before the portion is read, and for the portion after the color burst signal, one or more of the samples arranged in time order of writing. A plurality of samples are read, the samples being selected from the color burst signal after the transition period, covering all periods of the burst of the sinusoidal signal, and of the burst following the transition period. Color burst of a color television video signal characterized by combining in phase at the beginning of a sample sequence How to reconfigure No. it is provided.

The present invention also provides an apparatus for performing the method. The apparatus includes an input circuit for sampling a video signal to be recalibrated and for generating a synchronization signal leading to the video signal to be recalibrated, and storing the samples sent from the input circuit, one for writing and the other for writing. Functioning in parallel with each other, such as reading, such that these functions are swapped at the end of a time interval corresponding to the duration of one video line, and these memory plans Each memory plan includes a random access memory and a pre-positionable address counter, the address counter functioning with the sampling rhythm of the input circuit and pre-positioning. Loop during the transition period that spans around the start of the color burst signal. In order to reconstruct the signal to be read by re-reading the samples before and after the transition period, the action of the preposition loop causes the address counter to perform an address jump to the write order when reading the random access memory. It is characterized by becoming.

The preposition loop of the address counter of each memory plan advantageously comprises three read-only memories, the output signals of which are individually resynchronized by the registers to the sampling rate. The first read-only memory is used for decoding the starting point of the address jump and is directly addressed by the address counter. The second read-only memory decodes a condition enabling an address jump, and designates a signal which is addressed by a data read signal of the first read-only memory and a synchronizing signal from an input circuit and controls pre-positioning of an address counter. Send out. The third read-only memory is for decoding the address of the destination of the jump. The third read-only memory is addressed similarly to the second read-only memory, and sends the pre-arranged address to the address counter.

Other features and advantages of the present invention will become apparent from the following description of non-limiting embodiments, which is based on the accompanying drawings.

First, the implementation of the method of the present invention will be described by taking as an example a crypto transmission system for a video signal of a 625-line color television. The transmission system uses an embrouillage that displaces the effective portion of each line by a value O, R or 2R with respect to the line synchronization pulse. The value of the displacement is determined according to a pseudo-random encoding with a key that is known in both transmission and reception.

FIG. 1 simply shows a digital encoding circuit used in transmission to obtain a composite video signal that has been brouilled as described above. The circuit receives a decoded video signal to be displaced, converts the video signal into a series of digital samples, and extracts various synchronization signals; and A code generator 200 for sending a signal identifying the value of the delay to be applied to the effective part of the video signal line, and two identical types of memory plans 250, 300 with unique Randallm addressing circuits, Each can store a number of samples corresponding to an entire video line, one functioning in parallel with each other, such as writing and reading, etc., and these functions are interchanged to the video line inheritance rhythm. The chrominance recovery (recalage) and the introduction of the encoding displacement are performed under the control of the synchronization signal of the input circuit and the delay identification signal of the code generator 200. A memory plan implemented by read addressing (different from write addressing), and a series of digital samples sent from the memory plans 250, 300 are returned to analog form and the information from the coding generator 200 is converted into a composite video signal. And an output circuit 400 to be incorporated.

The input circuit 100 is a video signal processing means comprising an analog-to-digital converter 101, a continuous component recovery circuit 102 known as a clamp circuit upstream thereof, and an antirecouvrement low-pass filter 103. And a synchronization extraction circuit 1 for supplying various signals such as a line synchronization signal SyL, an even frame SyT, and an odd frame SyM.
04, an oscillator 105 with a phase-locked loop for supplying a sampling frequency adjusted to the line frequency and a line start signal PL, and a circuit 106 for detecting the color of chrominance,
It also includes a synchronization signal extraction and recalibration means composed of a circuit for controlling the two memory plans 250 and 300 when writing or reading.

The anti-overlap low-pass filter 103 limits the frequency band occupied by the input video signal to an upper limit of 6 MHz, and the energy of the frequency band exceeding 6 MHz overlaps with the above-mentioned frequency band due to a frequency spectrum folding phenomenon interposed at the time of later sampling. Make sure you don't have to.

As is known, the continuous component recovery circuit includes a synchronous extraction circuit 10.
4 black stop zone (palier de suppression du
It works by clamping to the black stop zone immediately following the line sync pulse with a clamp pulse centered to noir).

The synchronization extraction circuit 104 separates the video modulation and the synchronization signal, and outputs the line synchronization pulse SyL, the even frame SyT, and the odd frame.
SyM is selected and a clamp pulse Ic is generated as in all television receivers. Since the structure of this circuit is general and not included in the present invention, it will not be described in detail here.

The oscillator 105 with a phase-locked loop includes a voltage-controlled crystal oscillator 110, a phase-locked loop including a low-pass filter 111, and the oscillator 1 via the low-pass filter 111.
Phase comparator 112 controlling ten phase and frequency control inputs
Two frequency dividers 113 and 114 arranged between one of the output of the oscillator 110 and the input of the phase comparator 112;
And a third frequency divider 115 for connecting the other input of the second to the line synchronization output of the synchronization extraction circuit 104.

The voltage-controlled oscillator 110 synchronized with the line synchronization signal SyL of the synchronization extraction circuit 104 includes an analog-to-digital converter 1
01 and sampling frequency to memory plans 250 and 300
A point clock signal H of 17.734 MHz is sent. Said frequency is greater than twice the highest frequency of the video signal (6 MHz) and equal to 1/1135 harmonics of the line frequency (15625 Hz).

The frequency divider 113 divides the frequency of the oscillator 110 into 1/1135,
It is made equal to the frequency of the line synchronization signal SyL. Two dividers 114
And 115 are 1/2 frequency dividers, and the comparator 112 provides a symmetric rectangular signal. The signal transmitted from the 1/1135 frequency divider is a signal that is extremely stable at the line frequency, and does not include jitter that can act on the line synchronization signal SyL transmitted from the synchronization extraction circuit 104. However, this signal cannot be used as it is in place of the line synchronization signal. This is because, unlike the line synchronization signal, this signal has a residual phase provided by the phase comparator when the phase locked loop is at the equilibrium point. This residual phase shift is corrected by a recalibration digital circuit 116 consisting of a pre-positionable counter-1 / 1135 divider with an adjustable value. This frequency divider is rearranged by the rising front of the output signal of the frequency divider 113, and the overcapacity pulse constitutes the synchronization line start signal PL with the intermediate position of the rising front of the pulse of the line synchronization signal SyL.

A chrominance color extraction circuit 106 is connected to the output of the clamp circuit 102 and tunes to the sub-carrier frequency of 4.406 MHz of the sub-carrier of the SECAM system obtained unmodulated during the chrominance corresponding to the red component. A low pass filter 120 is included. Downstream of this low-pass filter 120 are two sampling-blocking circuits 12
1, 122 are arranged. The first sampling circuit 121 starts functioning with a clamp pulse generated inside the chrominance during the black rejection zone and sends out a binary value indicating whether the low pass filter 120 has separated the frequency of the red component subcarrier. . The second sampling-blocking circuit 122 starts functioning with the line start signal PL,
The value sent from the blocking circuit 121 is stored for the duration of one line of the video signal. This value constitutes a binary signal Dr representing the nature of the color components of the lines of the video signal being formed by reading one of the memory plans 250, 300.

The code generator 200 is not described in detail because it is not within the scope of the present invention. This generator mainly comprises a pseudo-random binary sequence generator and an auxiliary circuit with a microprocessor, from the output of said pseudo-random binary sequence generator towards the memory plan 250, 300, when reading, the effective part of the video line To determine delay values O, R, 2R to be given to
Two pieces of binary information C1 and C2 are transmitted. The auxiliary circuit with the microprocessor is provided with an initial loading of the pseudo-random binary sequence generator and a memory plan 250, 300 via a multiplexer 401 forming part of an output circuit 400.
Introducing the coding key into the frame blocking lines 310 and 622 of the video signal sent from the terminal and message-related operations (mess) by the terminal 210 to monitor the coding.
sagerie). The code generator receives the line synchronization signal SyL and the frames SyT, SyM from the synchronization extraction circuit 104, and these signals cause the frame reject lines 310 and 622 to be received.
To detect.

The output circuit 400 has two parallel inputs, namely memory plan 2
Input and code generator 2 connected to 50, 300 readouts
The multiplexer 401 having an input connected to the output of 00, a digital-to-analog converter 402, and an interpolating low-pass filter 403.

The memory plans 250 and 300 having the same structure, which will be described later in detail with reference to FIG. 3, have a point clock frequency H, a line start signal PL and a chrominance color signal.
As Dr, exchange binary information C1, C2 of coding and writing and reading function every time the line of video signal changes,
Complementary read / write orders W, W obtained at the terminals of an inverter 351 connected to the output of a bistable circuit 350 activated by the line start signal PL.

FIG. 2 schematically shows a digital decoding circuit suitable for the digital encoding circuit described above. This decoding circuit also includes a plurality of elements similar to the encoding circuit. These devices are shown with a dash (') on the same device. The main difference between this decoding circuit and the encoding circuit is that an inverted code generator 220 is used instead of a code generator, and the output circuit 400 'does not require a multiplexer.

The inversion code generator 220 provides a coding delay value O,
Decoded binary information C'1, which represents the difference between R and 2R with respect to 2R,
C'2 is sent to the memory plans 250 ', 300'. The difference is such that the memory plan is such that the active part of all video lines has the same value of 2R delay and can reproduce one distinct image.
This is in addition to the delay acting on the active portion of the video line when reading 250 ', 300'. Reverse code generator 220
Is not included in the scope of the present invention and will not be described in detail.
The inventor mainly includes a pseudo-random binary sequence generator of the same type as the code generator 200 and an auxiliary circuit with a microprocessor. The pseudo-random binary sequence generator outputs information C1 and C2, which are converted to information C1 'and C2' by simple inversion, for example, if they code the value of the natural binary delay. The auxiliary circuit with the microprocessor performs initial loading of the pseudo-random binary sequence generator using local information received via the keyboard 230 and coding keys written on the frame blocking lines 310,622. The coding key is separated from the analog video signal sent from the input circuit 100 'to the auxiliary circuit via the synchronizing signal SyL, the frame SyT and the frame SyM sent from the input circuit 100'.

The memory plans 250, 300, 250 'and 300' have a frequency of 17.735 MHz by the analog-to-digital converter of the input circuit.
And a high-speed memory capable of storing 1135 digital samples of the video lines provided by the memory, and an addressing circuit which allows the reading to be performed in an order different from the writing order by arbitrarily repeated address jumps.

FIG. 3 shows the structure of one of these memory plans in detail. This memory plan is composed of two synchronization registers 302, 3 functioning in accordance with the point clock signal H.
A high-speed memory arranged between 03 and having inputs and outputs arranged in parallel at 8-bit intervals
301 and a one-way bus amplification circuit 304 in a high impedance state that temporarily stores the output for connection in parallel with the output of the memory of the other memory plan. This high-speed memory 301 is addressed by a pre-positionable counter 305 that functions in accordance with the point clock signal H. The counter is a synchronous register interpolator 30.
It comprises three read-only memories 306, 307, 308 connected in cascade with 9, 310, 311.

The first read-only memory decodes the starting address of the optional jump. This memory uses the address counter 305
Addressed directly by the address counter 305
A signal is output from the output which codes the appearance of the jump departure address in the output with a plurality of parallel bits.

The second read-only memory 307 decodes the address jump condition and controls the pre-placement command of the address counter 305. In order to fulfill this function, this memory contains information C1 about the delay to be introduced into the active component of the video signal,
C2 or C'1, C'2, information S / C on the active SECAM or PAL system, and in the case of a SECAM system, a memory 30
The information Dr indicating whether the color component of the video signal read in 1 is red or blue, the line start signal Pl, the output signal of the first read-only memory 306, the synchronization register 309
And a read / write signal W sent with a one-point sampling delay via, and four bits of an output signal that is repeatedly reboucls via a synchronization register 310 to control the repetitive jump.

The third read-only memory 308 stores the destination address of the jump, and controls the parallel loading input of the address counter 305 via the synchronization register 311. This memory, like the second read-only memory, is supplied with a one-point sampling delay via the information C1 and C2 or C'1 and C'2, S / C, Dr, PL and the synchronization register 309. It is addressed by the output signal of one read-only memory 306.

The pulse of the line start signal PL is applied to the second read-only memory 30.
In step 7, the address of the write data area related to the pre-placement command of the address counter 305 is specified. In the third read-only memory 308, the address counter 305 is provided at the beginning of each video line.
Address the zero-valued data area so that is returned to zero.

When the dual memory plan write command signal W or its complement is high, the address counter 30
5 so that the address of the data area without the pre-placed order of the second read-only memory 307 is set to the write state of the memory 301 and the bus The output of the amplifier circuit 304 is set to a high impedance state.

The write control signal W or its complement in the dual memory plan puts the memory 301 in a read state at a low level and puts the output of the bus amplifier circuit 304 in a low impedance state. These signals also address the write data area in the second and third read-only memories 307, 308 for pre-placed order and jump destination addresses, and in the case of the SECAM system, FIG. 4 and FIG. In the case of the PAL system, the flowchart of FIG. 6 can be used. Using these flowcharts, the beginning of chrominance can be reconstructed without generating a phase discontinuity with the rest of the chrominance, as will be described later. Can be used to introduce the delay required for encoding or decoding into the video lines.

The reconstruction of the beginning of chrominance ignores digital samples of video lines that appear to straddle the theoretical beginning of chrominance over the transition period, and replaces these samples with respect to the part before the theoretical beginning of chrominance. This is accomplished by reading the previous sample anew with a backward address jump, and reading a series of samples that follow in chronological order for the portion after the beginning of chrominance. This series of samples is at the end of the sample sequence of the chrominance sine wave signal, which is phase-connected to the beginning of the sample sequence of the chrominance sine wave signal that appears after the transition period,
Selected from chrominance. The selection of a series of samples is performed by a forward address jump, and the connection at the end of the transition period is performed by a backward address jump.

FIG. 7 shows a method of reconstructing a transition period portion prior to the theoretical beginning of chrominance. Curve a7 shows SECAM or PAL using the front of the line synchronization pulse OH as the time origin.
Shows the beginning of the video line for the system. The beginning of the black stopband appears 4.7 μs later, and the beginning of the chrominance 5.58 μs
Appears later. Line b7 represents the instant of sampling of the video signal by the analog-to-digital converter of the input circuit, relative to the selected time scale. These points are numbered sequentially from zero according to the temporal order from the time origin OH. The temporal order is the order of writing digital samples to the memory 301. c7 represents the order of reading samples from the memory 301 after a time corresponding to one video line, that is, 64 μs. This order is the same as the writing order up to the beginning of the transition period. The beginning of the transition period is determined to be the 95th sample, sample 94 which is 5.30 μs from the time origin OH and 0.28 μs from the theoretical beginning of chrominance of SECAM or PAL. Ignoring the 95th to 99th samples written into memory 301, which theoretically appear before the beginning of chrominance, i.e. samples 94-98, replace these samples when reading samples 91, 92 and
93 is again read twice consecutively. This operation
Since the counter 305 returns to zero at the time origin OH, the order of writing the samples to the memory 301 also corresponds to the address sent from the counter. 30
Perform when reading 1. Between the address loading command and the actual coding into the address counter 305,
This situation is shown in FIGS. 4, 5 and 6 because there is a delay of three samples, i.e. the delay provided by the two successive synchronization register stages through which the signal in the preposition loop passes.
As shown in the flow chart in the figure, it is obtained by decoding the address 91 and subsequently loading the address 91. This loading command is not executed until the counter 305 reaches the address 94, and is repeated once per loop. The looping ends when the variable x of the jump count becomes 2.

The reconstruction of the part of the transition period after the theoretical beginning of chrominance consists of a sequence of successive samples of the sine wave signal of chrominance that can loop on its own without a phase jump when going from the last sample to the first sample. Decision is needed. The length of the sample sequence depends, of course, on the frequency of the sinusoidal signal.

SECAM system has a frequency of 4.25MHz for the blue component
Has FOB chrominance, 4.406MHZ for red component
Although having a chrominance of frequency FOR of z, the PAL system only has chrominance of a single frequency of 4.433 MHz.

Frequency FOR4.25 sampled at a frequency of 17.734 MHz
In one cycle of the MHz signal, a sample sequence including four samples is obtained. The last sample in this column is frequency FO
Sampled 9.7 ns after the end of the B signal period. This corresponds to a 15 ° phase jump in the case of a re-loop of the sample sequence. To mitigate this phase jump, a number of samples equal to a multiple of this sample sequence + 1 is used. The multiples are chosen such that the residual time is very close to the sampling period, justifying the use of supplemental samples. Since the sampling period is about 5.8 times the residual time of 9.7 ns, the multiple is set to 6. As a result, a row of 25 samples lasting 1.409 μs will be used. On the other hand, the six periods of the signal of the frequency FOB are 1.411 μs. This 2 ns residual time error corresponds to a 3 ° phase jump in the case of relooping, but such a jump can be substantially ignored.

Frequency FOR4 sampled at a frequency of 17.734MHz.
One cycle of a 406 MHz signal has a residual time error of
A sample sequence consisting of one sample is obtained. Said error corresponds to a negligible phase jump of 2.2 ° in the case of re-looping. Therefore, there is no need to determine a longer sample sequence.

Frequency 4.433 sampled at a frequency of 17.734 MHz
In one cycle of the MHz signal, a sample sequence of four samples is obtained with a residual time error of 1.1 ns. Said error represents a negligible phase jump of around 1.7 ° in the case of relooping. Therefore, in this case, it is not necessary to obtain a longer sample sequence.

Since the length of the sample rows based on the initial reconstruction of chrominance is fixed, it is necessary to determine the number of samples actually used in these rows. This number depends on the length of the beginning of the chrominance included in the transition period, and in the case of a SECAM system where the chrominance extends to the active component of the video line without interruption, it should be introduced for encoding or decoding. It also depends on the delay O, R, 2R. Therefore,
It varies depending on whether a PAL or SECAM system is used, and if the video line is a blue or red component line where the active component must delay the active component by O, R or 2R. .

FIG. 8 shows a method for reconstructing the beginning of chrominance in a blue component video line of a SECAM system in which no delay of the effective video part is required.

Curve a8 represents the beginning of a SECAM system video line where the front OH of the line sync pulse is used as the time origin. The beginning of the recalibrated chrominance is 5.58 μs away. Line b8 shows the beginning of the chrominance sampling time point against the selected time scale. These points are numbered sequentially from the time origin OH according to the time sequence. This order is the order of address specification when writing to the memory 301. Line c8 is memory 301 after one video line
Represents the order of reading samples.

In practice, it is sufficient to reconstruct the beginning of the chrominance over a segment comprised between about 1.4 μs, ie between sample 99 (inclusive) and 123 (inclusive). Here, the reconstruction is performed over a slightly longer time corresponding to the segment from sample 99 to sample 130.

The next 25 samples, ie, samples 131 to 155, are selected as the reconstructed sample sequence. The segments to be reconstructed
Because it extends over 32 samples, a single read of a sample of the reconstructed sample sequence is not sufficient. Thus, this reading is supplemented by reading samples 124-130. These samples, although present in the segment to be reconstructed, are more than one microsecond from the theoretical beginning of chrominance. Therefore, the sample
Reconstructing the segment from 99 to sample 130 is the same as replacing samples 99-130 with samples 124-155. This is shown in the flowchart of FIG.
This is performed by performing the address jump twice when reading the memory 301. That is, first, a forward address jump is performed to move from the temporal position 98 to the position 124 relative to the beginning OH of the line, and then a backward address jump moves from the address 155 to the address 131. As shown in the flowchart of FIG. 4, the command of the first jump is that the address counter is the output of the first loop.
Issued when 93 is reached. This corresponds in time to position 96 relative to the beginning OH of the line. As a result of this jump, address 12
Loading of the counter 305 at 4 is performed. The command of the second jump is issued when the address counter reaches 153 for the first time, ie at time 128 relative to the beginning of the line OH, and at time position 131 delayed by three samples, ie the address counter reaches 131. Implemented when relocated.

FIG. 9 illustrates the chrominance opening reconstruction method for the blue component video line of a SECAM system where the useful video portion must be delayed by a value R equal to 902 ns corresponding to a segment of 16 samples.

Curve a9 shows the beginning of the video line of the SECAM system where the front OH of the line sync pulse is used as the time origin, and 5.58
The beginning of chrominance appearing after μs is shown. line
b9 shows the sampling points at the beginning of the chrominance relative to the selected time scale, these points being numbered sequentially from the time origin according to the temporal order. This order is the order of addressing when writing to the memory 301. Line c9 represents the order of reading samples from memory 301 after one video line.

In this case as well, the reconstruction involves the segment from sample 99 to sample 130, as described above, and is performed using the next 25 samples, ie, samples 131 to 155, as the reconstructed sample sequence.

The segment to be reconstructed begins at sample 99 and includes 32 sample positions to be ignored and 16 sample positions representing the delay R to be applied to the active component of the video signal. The second half of samples 122-146 is formed by a complete re-reading of 25 samples of the reconstructed sample sequence, and the first half of samples 99-121 is formed by re-reading of the last 23 samples of the reconstructed sample sequence. Is done.

To this end, as shown in the flowchart of FIG. 4, address jumps are performed three times consecutively when reading the memory 301.

The first address jump is a forward jump, which causes the position from the temporal position 98 to the position 13 relative to the beginning OH of the line.
A move to 3 is made.

This jump starts when the address counter 305 reaches 93 at the output of the first loop, ie, at time 93 relative to the beginning of the line, OH, and is delayed by three samples, ie, when the address counter 305 reaches 133. Becomes effective when pre-arranged.

The second address jump is a backward jump, and a movement from address 155 to address 131 occurs. This jump is started when the address counter 305 reaches 153, and becomes effective when the counter reaches 156.

The third address jump is a jump count variable x.
Is the second repetition of the jump by the second loop processing, which ends when the value becomes 2.

FIG. 10 shows the chrominance start reconstruction method for the blue component video line of the SECAM system when the effective portion has to be delayed by a factor of 2R. The delay 2R is equal to 1804 ns, corresponding to a segment containing 32 samples.

Curve a10 represents the beginning of a video line in a SECAM system where the front OH of the line sync pulse is used as the time origin.

Line b10 shows the sampling time points at the beginning of the chrominance, relative to the selected time scale, and these time points are numbered sequentially from the time origin in chronological order.
This order is the order of addressing when writing to the memory 301. Line c10 represents the order of reading the first chrominance sample of the memory 301 after one video line.

In this case as well, the reconstruction involves the segment from sample 99 to sample 130 and is carried out using the next 25 samples selected as the sequence of reconstructed samples, ie samples 131-155.

The segment to be reconstructed starts at the location of sample 99 and includes the location of 32 samples to be ignored and 32 sample locations representing the delay 2R to be applied to the active component of the video signal. The rear part consisting of samples 138 to 162 and the middle part consisting of samples 113 to 137 are each of the reconstructed sample sequence.
Formed by a complete reread of 25 samples, the front part consisting of samples 99-112 is formed by a reread of the last 14 samples of the reconstructed sample sequence. To this end, as shown in the flowchart of FIG. 4, address jumps are performed four times consecutively when reading the memory 301.

The first address jump is a forward jump, which results in a movement from temporal position 98 to position 142 relative to the beginning of the line OH. This jump also occurs when the address counter 305 corresponds to the temporal position 96 with respect to the line start OH at the output of the first loop 93.
At the time when the address counter 305 is reached, and becomes effective when the address counter 305 is pre-arranged at 142 after a delay of three samples.

The second address jump is a backward jump, and movement from address 155 to 131 is performed. This starts when the address counter 305 reaches 153 and becomes effective when the counter reaches 156.

The third and fourth address jumps are repetitions of the second jump by the second loop that ends when the variable x of the jump count becomes three.

FIG. 11 shows a chrominance start reconstruction method for a video line of a PAL system or a video line of a SECAM system for a red component when a delay of an effective portion is not required.

Curve a11 represents the beginning of a video line of a SECAM or PAL system. In the case of a PAL system, the end of chrominance appears outside the section shown 7.85 μs after the rising front OH of the line sync pulse. Line b11 shows the sampling time at the beginning of the chrominance against the selected time scale. These points are numbered sequentially from the time origin OH according to the time sequence. This order is memory 30
This is the address specification order when writing to 1. Line c11 represents the order of reading the first sample of chrominance in the memory 301 after one video line.

At the PAL system frequency of 4.43 MHz, the reconstructed sample sequence may be limited to four consecutive samples as described above, as with the SECAM system red component chrominance frequency of 4.406 MHz.

Here, the chrominance opening segment extending over samples 99-113 is reconstructed by using the next four samples, samples 114, 115, 116 and 117, as the reconstructed sample sequence. This segment reconstruction is performed by forming the posterior portion of samples 102-113 by three rereads of the reconstructed sample sequence, and
This is done by forming the front part consisting of 9, 100 and 101 by rereading the last three samples of the reconstructed sample sequence. To this end, as shown in the flowcharts of FIGS. 5 and 6, the address jump is performed five times consecutively when reading the memory 301.

The first address jump is a forward jump, and the movement from the temporal position 98 to the position 115 with respect to the line beginning OH is performed. This jump is also performed by the address counter 305
It starts as soon as it reaches the position 96 relative to the beginning of the line OH at the output of the loop and is effective three delays by three samples, ie when the address counter 305 is pre-positioned at 115.

The second address jump is a backward jump, and moves from address 117 to address 114. This jump starts as soon as the address counter reaches 115,
The third, fourth and fifth address jumps, which take effect three sample delays, ie when the counter reaches 118, are due to a second looping which ends when the jump count variable x becomes four. This is the second repetition of the jump.

If it is necessary to delay the effective portion of the red component video line of the SECAM system by the value R for 16 samples or the value 2R for 32 samples, the number of repetitions of the second loop is changed and the fifth loop is repeated. As shown in the flowchart of FIG.
In the case of, change from 3 to 7. In this case, when the variable x of the jump count becomes 8, the looping ends. Or delay
In the case of 2R, change from 3 to 11. In this case, the looping ends when the variable x of the jump count becomes 12. In fact, each time the second loop is repeated, the chrominance is extended by four samples, without a problematic phase jump.

FIG. 12 shows a method of introducing a delay R of 16 samples into an effective portion of a video line of a PAL system. Curve a1
2 represents the beginning of the video line where the line synchronization pulse front OH is used as the time origin. Chrominance appears after 5.58 μs over a time of 2.25 μs, and the beginning of the effective video is
Appears after 10.5 μs. Line b12 shows the sample time of the black block after the end of the chrominance against the selected time scale. These points are numbered sequentially from the time origin OH according to the time sequence. This order is the order of address specification at the time of writing to the memory 301. Line c12 represents the order of reading in memory 301 one video line later for the black block sample after chrominance.

The introduction of the delay R between the valid video and the line sync pulse is
This is accomplished by repeating a segment between samples 159 and 174 for a 16 sample segment located in the black block after chrominance. For this purpose, as shown in the flowchart of FIG. 6, when reading the memory 301, the address jump from the address 174 to the address 159 is performed. This jump is started as soon as the address counter 305 reaches 172, and becomes effective when the counter reaches 175.

As shown in the flow chart of FIG. 6, the introduction of the delay 2R twice as long as the above-mentioned delay repeats the same address jump as in the case of the introduction of the delay R by the third loop which ends when the variable Y of the jump count becomes 2. It is implemented by.

Introducing a delay R or 2R between the line sync pulse and the active part of the video signal of a PAL or SECAM system,
The end of the effective part of one line occupies a guard interval (interval de garde) preceding the synchronization pulse of the next line. To eliminate this defect, the end of each line is corrected. This operation is performed for the effective part
Consists of removing 16 or 32 samples. For this purpose, as shown in the flowcharts of FIGS. 4, 5 and 6, an address jump is performed at the time of reading the memory 301, and when the delay R is introduced, the address 1091 to the address 1108 and the delay 2R are introduced. In this case, the address is moved from address 1075 to address 1108. This jump is caused by the delay introduced by the two synchronization register stages through which the signals in the prepositioned loop of the address counter 305 pass.
It starts when either 89 or 1073 is reached and is activated when the counter is prepositioned at 1108, three samples later.

Of course, the chrominance incipient recalibration method described above may be applied differently to uncoded or coded color television video signals, for example, by circular scaling (dcalages circulaires). The circular phase shift is obtained by making an appropriate jump through the address counter when reading the valid video portion of the memory plan.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a simplified explanatory diagram of a digital encoding circuit suitable for carrying out the recalibration method of the present invention and for cryptographic processing of a video signal of a color television, and FIG. FIG. 3 is a simplified explanatory diagram of a decoding circuit for performing the recalibration method of the present invention adapted to the encoding circuit, and FIG. 3 is a structure of a memory plan used in the encoding circuit and the decoding circuit of FIGS. 1 and 2; FIG. 4, FIG. 4, FIG. 5, and FIG. 6 are flow charts showing the functions of the memory plan of FIG. 3, FIG. 7, FIG. 8, FIG. 9, FIG. FIG. 12 is a flow chart which shows in time the conversion which a video signal line undergoes when encoding and decoding are optionally applied in addition to the recalibration method of the present invention. 100 ... input circuit, 250, 300 ... memory plan, 305 ...
Address counter, 400 ... Output circuit.

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-63-292788 (JP, A) JP-A-63-107386 (JP, A) JP-A-60-256287 (JP, A) JP-A-63-292 7093 (JP, A) Special Table 63-501113 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H04N 9/44 H04N 7/167

Claims (4)

(57) [Claims] 1. A method for recalibrating a color burst signal of a color television video signal, the method comprising sampling the video signal and operating in parallel with one another so that one writes and the other reads. Storing the samples of the video signal in two randomly-addressed memory plans, the functions of the memory plans being exchanged at the end of a time interval corresponding to the duration of one line; The samples of each memory plan are read according to the chronological order of writing, except that the samples (samples) which are shifted in phase due to distortion and appear during a transition period extending before and after the start point of the color burst signal.
The sample 130) is not read from 94, but instead reads the sample immediately before the portion of the color burst signal for the portion before the start of the color burst signal, and according to the time sequence of writing for the portion after the color burst signal. Reading one or more samples of side-by-side samples, wherein the samples are selected from the color burst signal after the transition period and cover all periods of the burst of the sine wave signal; A method of reconstructing a color burst signal of a color television video signal, comprising combining in phase at the beginning of a sequence of burst samples following a transition period. 2. The method according to claim 1, wherein said signal has a color burst signal extending continuously to an effective portion and is crypted by a constant delay.
Used for encoding or decoding of a composite video signal that displaces the effective portion of each video line with respect to the line synchronization pulse according to a specific code, the transition period is reconfigured during the transition period,
The method according to claim 1, further comprising an operation of extending the number of samples corresponding to a delay time to be added for encoding or decoding. 3. An apparatus for performing the method of claim 1, wherein the input circuit samples the video signal to be recalibrated and generates a synchronization signal that is connected to the video signal to be recalibrated. Store the samples sent from this input circuit, one functioning in parallel with the other, such as writing, reading, etc., and these functions change at the end of the time interval corresponding to the duration of one video line. Random access memory plans, and output circuits for returning samples resulting from reading these memory plans back to analog form, each memory plan including a random access memory and a pre-placeable address counter. The address counter functions with the sampling rhythm of the input circuit and has a pre-placed loop, Due to the action of the preposition loop, when reading the random access memory, the signal appearing in a transition period that spans before and after the start of the burst signal is reconstructed by rereading the samples before and after the transition period. Apparatus, characterized in that said address counter performs an address jump to a write order. 4. The preposition loop of an address counter includes three read-only memories, the output signals of these read-only memories being individually resynchronized by a register, and a first read-only memory for decoding an address jump starting point. And the second read-only memory decodes the condition enabling the address jump, and is addressed by the data read signal of the first read-only memory and the synchronization signal from the input circuit. The third read-only memory decodes the address of the jump destination, is addressed in the same manner as the second read-only memory, and sends the pre-arranged address to the address counter. 4. The method according to claim 3, wherein Apparatus.