JP2915725B2 - Active matrix substrate inspection method, inspection apparatus, and defect repair method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of inspecting an active matrix substrate for forming a display device in combination with a display medium such as a liquid crystal, an inspection device, and a defect correction method.

[0002]

2. Description of the Related Art An active matrix system in which picture element electrodes are arranged in a matrix on an insulating substrate and the picture element electrodes are independently driven is used for display devices such as liquid crystal televisions, word processors, and computer terminal displays. Has been put to practical use. As a switching element for selectively driving the picture element electrode, a TFT (thin film transistor) element, an MIM (metal-insulating layer-metal) element, a MOS transistor element, a diode, a varistor, and the like are generally known.

FIG. 31 is a schematic circuit diagram of an active matrix display device using TFTs as switching elements, and FIG. 32 is a partially enlarged view of the active matrix display device. This display device includes an active matrix substrate and a counter substrate that are disposed to face each other with a liquid crystal layer interposed therebetween. In the active matrix substrate, a plurality of gate bus lines 1 functioning as scanning lines are wired in parallel, and a large number of source bus lines 2 functioning as signal lines are wired in parallel with the gate bus lines 1. A TFT 3 is disposed near the position where the bus lines 1 and 2 intersect, and a pixel electrode 4 provided in a region surrounded by the bus lines 1 and 2 is connected to the TFT 3.

On the other hand, on a counter substrate facing the active matrix substrate, a counter electrode 5 is formed on the liquid crystal layer side, and a pixel capacitor CL is provided between the pixel electrode 4 and the counter electrode 5.
C is formed. An auxiliary capacitance (CS) 6 is formed in parallel with the pixel capacitance CLC. It is connected to the. That is, the above-described active matrix substrate is a so-called Cs-On-Gat
The structure is e.

[0005] The Cs-On-Gat thus configured
In an active matrix display device having a substrate having the e-structure, a signal A1 shown in FIG. 33 is applied to an odd-numbered gate bus line 1 via a wiring 7 shown in FIG.
The signal A2 is applied to the even-numbered gate bus line 1 via the wiring 8. Further, the signal B is applied to the source bus line 2 via the wiring 9 and the signal C is applied to the counter electrode 5. The signals A1 and A2 are signals for controlling the gate electrode of the TFT3 to be turned on / off. The signal B is a signal which does not change even after writing to each picture element by the TFT3 until the next frame is written. This is a signal fixed to an appropriate voltage value.

FIG. 34 is a schematic circuit diagram of another active matrix display device using TFTs as switching elements, and FIG. 35 is a partially enlarged view of the active matrix display device. This display device includes an active matrix substrate and a counter substrate that are disposed to face each other with a liquid crystal layer interposed therebetween. In the active matrix substrate, a plurality of gate bus lines 1 functioning as scanning lines are wired in parallel,
A large number of source bus lines 2 functioning as signal lines are arranged in parallel with the gate bus lines 1 in a direction perpendicular to the gate bus lines 1. A TFT 3 is disposed near the position where the bus lines 1 and 2 intersect, and a pixel electrode 4 provided in a region surrounded by the bus lines 1 and 2 is connected to the TFT 3.

On the other hand, on a counter substrate facing the active matrix substrate, a counter electrode 5 is formed on the liquid crystal layer side, and a pixel capacitor CL is provided between the pixel electrode 4 and the counter electrode 5.
C is formed. An auxiliary capacitance (CS) 6 is formed in parallel with the pixel capacitance CLC. One of the auxiliary capacitances 6 is connected to the pixel electrode 4 and the other is connected to an auxiliary capacitance common line 29 provided in parallel with the gate bus line 1. Have been. That is, the above-described active matrix substrate having another configuration is a so-called Cs-On-
It has a Common structure.

The Cs-On-Com structured as described above
In an active matrix display device having a substrate having a mon structure, a signal A3 shown in FIG. 36 is supplied to the gate bus line 1 via a wiring 28a shown in FIG.
Further, the signal B is applied to the source bus line 2 via the wiring 9 and the signal C is applied to the counter electrode 5. The above signal A
Reference numeral 3 denotes a signal for controlling the gate electrode of the TFT 3 to be turned on and off, a signal B is a signal which does not change even after writing to each picture element by the TFT 3 until the next frame is written, and a signal C is an optimum voltage value. This is a fixed signal.

[0009]

By the way, the former Cs
An active matrix substrate having an -On-Gate structure,
Even if a defect occurs in the latter active matrix substrate having a Cs-On-Common structure, it is conventionally possible to detect a part of the defect, but it is necessary to sufficiently detect the defect and perform defect correction. Could not. That is, as shown by broken lines in FIG. 33 in the case of the former substrate and in FIG. Mode can be detected. However, as described above, since the signal B does not change until the writing of the next frame even after writing to each picture element by the TFT 3, the leakage between the source electrode and the drain electrode causes
Even if the off characteristic of T3 is deteriorated, it is always constant, so that the off failure defect mode cannot be detected, and even if the leak between the picture element electrode 4 and the source bus line 2 is leaked,
For the same reason, the leak failure mode cannot be detected.

The signal C applied to the counter electrode 5 is
Since the opposing voltage is fixed to the optimum value, the opposing electrode 5 and the pixel electrode 4 leak due to metal dust or the like. Can be detected, but it is not possible to distinguish between the OFF defect mode caused by the same insulation defect and the leak defect mode.

As described above, conventionally, an off defect mode, a leak defect mode occurring between a source electrode and a drain electrode, between a counter electrode and a picture element electrode, or between auxiliary capacitance electrodes is detected. However, even if the presence of a defect can be detected, it is not possible to discriminate between the off defect mode and the leak defect mode. Further, even if an attempt is made to repair a defective portion, it is unknown where the defect mode has occurred, so that the defect cannot be substantially corrected and the yield is reduced.

The present invention has been made to solve the above-mentioned problems of the prior art, and can detect a defect mode which could not be detected so far, and can determine which defect mode and where a defect has occurred. Cs-On-Gate structure or C
It is an object of the present invention to provide an inspection method and an inspection apparatus for an active matrix substrate having an s-On-Common structure, and to provide a defect repair method capable of repairing a defective portion based on a detected defect mode.

[0013]

According to a method of inspecting an active matrix substrate of the present invention, a plurality of picture element electrodes and thin film transistors for driving the picture element electrodes are arranged in a matrix on an insulating substrate. A scanning electrode and a signal line which are respectively connected to the thin film transistor and intersect with each other are connected to a pixel electrode constituting each pixel via the thin film transistor, and are connected to the pixel electrode. In the method for testing an active matrix substrate, the auxiliary capacitance formed by the above is connected to another scanning line adjacent to the scanning line to which the pixel electrode is connected with the pixel electrode interposed therebetween.
A counter substrate having a counter electrode disposed to face the active matrix substrate, and a liquid crystal layer formed on the counter electrode side of the counter substrate and disposed on the active matrix substrate side,
Using an inspection device having a scanning line, a signal line, and a connection terminal for connecting to each of the counter electrodes, the inspection device is arranged to face the active matrix substrate, and the connection terminal is scanned. Connecting to each of the lines, the signal lines and the counter electrode, and alternately giving an ON signal defining a period of one frame and an OFF signal following the ON signal to the scanning line of the active matrix substrate, A first pattern for changing the level of the voltage applied to the signal line before the application of the ON signal to each of the two frames to be applied, and the level of the voltage applied to the signal line before and after the application of the ON signal to each of the two adjacent frames. and the second pattern to be changed, a third pattern for changing the level of the voltage applied to the signal line after the two frames each oN signal applied to tandem At least two patterns of out
Performing the step of identifying a plurality of types of defect modes, thereby achieving the above object.

Further, according to the active matrix substrate inspection method of the present invention, a plurality of picture element electrodes and thin film transistors for driving the picture element electrodes are arranged in a matrix on an insulating substrate, and each of the picture element electrodes is connected to the thin film transistor. In addition, a pixel electrode constituting each pixel is connected to the scanning line and the signal line formed crossing each other through the thin film transistor, and formed in relation to the pixel electrode. In a method for testing an active matrix substrate in which a storage capacitor is connected to another scanning line adjacent to a scanning line to which the pixel electrode is connected with the pixel electrode interposed therebetween, the auxiliary capacitance is provided to face the active matrix substrate. A counter electrode having a counter electrode to be formed, a liquid crystal layer formed on the counter electrode side of the counter substrate and disposed on the active matrix substrate side, a scanning line, a signal line, and the counter electrode. And an inspection device having connection terminals for connecting to the active matrix substrate, and the inspection device is arranged to face the active matrix substrate, and the connection terminals are connected to the scanning lines, the signal lines, and the counter electrodes. Connecting them to each other, and alternately applying an ON signal defining a period of one frame and an OFF signal subsequent to the ON signal to the scanning lines of the active matrix substrate,
A first pattern for changing the level of the voltage applied to the signal line before the on signal is applied to each of the two frames, and a first pattern for changing the level of the voltage applied to the signal line before and after the on signal is applied to each of the two consecutive frames Performing at least two patterns of a second pattern and a third pattern for changing a level of a voltage applied to a signal line after the on-signal is applied to each of two successive frames; The applied voltage is set to the on-voltage of the thin film transistor applied to the scanning line. The voltage applied to the counter electrode is set to the off voltage of the thin film transistor applied to the scanning line. Performing a step of selectively performing a change between the on-voltage and the off-state voltage in a state of being connected to the electrode to detect a defect mode. The above-mentioned object can be achieved by the.

According to the inspection apparatus for an active matrix substrate of the present invention, a plurality of pixel electrodes and thin film transistors for driving each of the pixel electrodes are arranged in a matrix on an insulating substrate, and are connected to the thin film transistors, respectively. In addition, a picture element electrode constituting each picture element is connected to the scanning line and the signal line formed crossing each other through the thin film transistor, and an auxiliary capacitance formed in relation to the picture element electrode However, a scanning line to which the picture element electrode is connected is an active matrix substrate inspection apparatus connected to another scanning line adjacent to the picture element electrode, and is opposed to the active matrix substrate. A counter substrate having a counter electrode disposed thereon, a liquid crystal layer formed on the counter electrode side of the counter substrate and disposed on the active matrix substrate side,
A connection terminal for connecting to each of the signal line and the counter electrode, and detection means for detecting a defect mode of the active matrix substrate via the connection terminal, wherein the detection means is connected to a scanning line of the active matrix substrate. A first signal for alternately supplying an ON signal for defining a period of one frame and an OFF signal subsequent to the ON signal, and changing a level of a voltage applied to a signal line before the application of the ON signal for each of two successive frames. And a second pattern for changing the level of the voltage applied to the signal line before and after the on signal is applied to each of the two successive frames,
And a third pattern for changing the level of the voltage applied to the signal line after the application of the ON signal for each of the three frames.
By performing at least two patterns, multiple types of defect models
Since the configuration is such that the code is identified , the above object is achieved.

In the inspection apparatus for an active matrix substrate according to the present invention, a plurality of pixel electrodes and thin film transistors for driving the respective pixel electrodes are arranged in a matrix on an insulating substrate, and are connected to the thin film transistors. In addition, a pixel electrode constituting each pixel is connected to the scanning line and the signal line formed crossing each other through the thin film transistor, and formed in association with the pixel electrode. An auxiliary capacitor is an inspection apparatus for an active matrix substrate connected to another scanning line adjacent to the scanning line to which the pixel electrode is connected with the pixel electrode interposed therebetween, and the storage capacitor is opposed to the active matrix substrate. A counter substrate having a counter electrode disposed in a state, and formed on the counter electrode side of the counter substrate;
A liquid crystal layer disposed on the active matrix substrate side, connection terminals for connecting to the scanning lines, the signal lines, and the counter electrode, and detection means for detecting a defect mode of the active matrix substrate via the connection terminals Wherein the detection means alternately supplies an ON signal defining a period of one frame and an OFF signal subsequent to the ON signal to the scanning line of the active matrix substrate, and also outputs ON signals of two successive frames. A first pattern for changing the level of the voltage applied to the signal line before the application, and a second pattern for changing the level of the voltage applied to the signal line before and after the application of the ON signal of each of two successive frames, A third pattern for changing the level of the voltage applied to the signal line after the application of the ON signal to each of the two preceding and succeeding frames ;
Performing at least two of the patterns , further setting the voltage applied to the counter electrode to the on-voltage of the thin film transistor applied to the scanning line, and changing the voltage applied to the counter electrode to the scanning line A defect mode is detected by selectively performing the off voltage of the thin film transistor and changing the auxiliary capacitance between the on voltage and the off voltage in a state where the auxiliary capacitance is connected to the counter electrode. Therefore, the above object is achieved.

According to the defect repair method for an active matrix substrate of the present invention, a plurality of picture element electrodes and thin film transistors for driving each picture element electrode are arranged in a matrix on an insulating substrate, and each of the picture element electrodes is connected to the thin film transistor. A pixel electrode constituting each pixel is connected to the scanning line and the signal line formed crossing each other through the thin film transistor, and an auxiliary electrode formed in relation to the pixel electrode is formed. In the method for repairing a defect of an active matrix substrate, a capacitor is connected to another scanning line adjacent to the scanning line to which the pixel electrode is connected, with the pixel electrode interposed therebetween. A counter substrate having a counter electrode to be formed, a liquid crystal layer formed on the counter electrode side of the counter substrate and disposed on the active matrix substrate side,
Using an inspection device having a signal line and a connection terminal for connecting to the counter electrode, respectively, the inspection device is disposed to face the active matrix substrate, and the connection terminal is connected to a scanning line and a signal. Connecting the scan line of the active matrix substrate with an ON signal for defining a period of one frame and an OFF signal following the ON signal alternately. A first pattern for changing the level of the voltage applied to the signal line before the on signal is applied to each of the two frames, and a first pattern for changing the level of the voltage applied to the signal line before and after the on signal is applied to each of the two consecutive frames and the second pattern, of the third pattern of changing the level of the voltage applied to the signal line after the two frames each oN signal applied to tandem Carried out at least two patterns
Thus, the step of identifying a plurality of types of defect modes and the step of correcting a defect according to the detected defect mode are performed, thereby achieving the above object.

Further, according to the defect correcting method for an active matrix substrate of the present invention, a plurality of pixel electrodes and thin film transistors for driving the respective pixel electrodes are arranged in a matrix on an insulating substrate, and the thin film transistors and connection,
In addition, a picture element electrode constituting each picture element is connected to the scanning line and the signal line formed crossing each other through the thin film transistor, and an auxiliary capacitance formed in relation to the picture element electrode However, in a method for correcting a defect of an active matrix substrate connected to another scanning line adjacent to the scanning line to which the pixel electrode is connected with the pixel electrode interposed therebetween, the active matrix substrate is disposed to face the active matrix substrate. A counter substrate having a counter electrode, a liquid crystal layer formed on the counter electrode side of the counter substrate and disposed on the active matrix substrate side,
Using an inspection device having a scanning line, a signal line, and a connection terminal for connecting to the counter electrode, respectively, disposing the inspection device in opposition to the active matrix substrate, and scanning the connection terminal. A line, a signal line, and a step of connecting to each of the counter electrodes; and alternately applying an ON signal defining a period of one frame to a scan line of the active matrix substrate, and an OFF signal subsequent to the ON signal.
A first pattern for changing the level of the voltage applied to the signal line before the on-signal is applied to each of the two consecutive frames; and a first pattern for changing the voltage applied to the signal line before and after the on-signal is applied to each of the two consecutive frames. 2nd level change
At least two of the following patterns, and a third pattern for changing the level of the voltage applied to the signal line after the on-signal is applied to each of the two successive frames.
Performing , further, the voltage to be applied to the counter electrode, the on-voltage of the thin film transistor applied to the scanning line,
Changing the voltage applied to the counter electrode to an off voltage of the thin film transistor applied to a scanning line; and changing the auxiliary capacitance between the on voltage and the off voltage in a state where the auxiliary capacitance is connected to the counter electrode. And the step of selectively correcting the defect mode, and the step of correcting the defect in accordance with the detected defect mode, thereby achieving the above object.

The inspection method, the inspection apparatus and the defect correction method for an active matrix substrate according to the present invention are the same as those described above for an active matrix substrate having a Cs-On-Common structure in which an auxiliary capacitor is connected to a common wiring. By doing so, the above object can be achieved.

[0020]

According to the present invention, a plurality of picture element electrodes and thin film transistors for driving the picture element electrodes are arranged in a matrix on an insulating substrate, connected to the thin film transistors and crossed with each other. Each pixel electrode is connected to the scanning line and signal line formed through the thin film transistor, and an auxiliary capacitor formed in connection with the pixel electrode is connected to the pixel electrode. The following inspection may be performed on another scanning line adjacent to the scanning line sandwiched by the pixel electrode or on an active matrix substrate connected to a common wiring. That is, the opposite substrate to be inspected is disposed opposite to the active matrix substrate, and the connection terminals are connected to the scanning lines, the signal lines, and the counter electrodes, respectively. , An ON signal defining a period of one frame and an OFF signal subsequent to the ON signal are alternately applied, and the level of a voltage applied to a signal line is changed before the ON signals are applied to two successive frames. A first pattern, a second pattern for changing the level of the voltage applied to the signal line before and after the on-signal application for each of the two consecutive frames, and a signal after the on-signal application for each of the two consecutive frames. At least two of the third pattern for changing the level of the voltage applied to the line ;
Do. As a result, a dark display occurs in the display portion corresponding to the defective portion, and the defect mode is detected.

Further, in the case where the target of the defect mode to be detected is expanded, the following may be performed. That is, the opposite substrate to be inspected is disposed opposite to the active matrix substrate, and the connection terminals are connected to the scanning line, the signal line, and the opposite electrode, and in this state, one frame is connected to the scanning line of the active matrix substrate. A first signal that alternately supplies an ON signal that determines the period of the ON signal and an OFF signal that follows the ON signal, and changes the level of the voltage applied to the signal line before the application of the ON signal to each of two consecutive frames. A pattern, a second pattern for changing the level of the voltage applied to the signal line before and after the on-signal is applied to each of the two successive frames, and a second pattern for changing the level of the voltage applied to the signal line before and after the on-signal is applied to each of the two successive frames At least two patterns of the third pattern for changing the voltage level;
And turning the voltage applied to the counter electrode to the on voltage of the thin film transistor applied to the scanning line, and changing the voltage applied to the counter electrode to the off voltage of the thin film transistor applied to the scanning line. And changing between the on-voltage and the off-voltage while the storage capacitor is connected to the counter electrode is selectively performed. As a result, detection can be performed with a wider target in the defect mode.

Further, the defect is corrected by correcting the detected defective portion.

The above is the case of the Cs-On-Gate structure, but the same applies to the case of the Cs-On-Common structure.

[0024]

Embodiments of the present invention will be described below.

(Embodiment 1) FIG. 1 shows the whole structure of an active matrix substrate using TFTs as switching elements, and FIG. 2 shows a part thereof. In this substrate, a plurality of gate bus lines 1 functioning as scanning lines are wired in parallel, and a large number of source bus lines 2 functioning as signal lines are wired in parallel with the gate bus lines 1. In the vicinity of the position where both bus lines 1 and 2 intersect, TF
T3 is provided, and a picture element electrode 4 is connected to the TFT3. The gate bus line 1 and the source bus line 2 are provided along the periphery of the picture element electrode 4. A storage capacitor (CS) 6 is provided between the drain electrode of the TFT 3 and the gate bus line 1 which is adjacent to the gate bus line 1 to which the TFT 3 is connected by being shifted by one position. In other words, this active matrix substrate
It has a so-called Cs-On-Gate structure.

Further, the odd-numbered gate bus lines 1 are connected to each other by a common wiring 7, and terminals 7 a are provided at both ends of the common wiring 7. Further, the even-numbered ones are connected by a common wiring 8, and terminals 8 a are provided at both ends of the common wiring 8. One end of the source bus line 2 has a common wiring 9
, And terminals 9 a are provided at both ends of the wiring 9.

When an opposing substrate on which a liquid crystal layer and an opposing electrode are formed in advance on the active matrix substrate having such a configuration is disposed facing the liquid crystal layer on the side of the active matrix substrate, the opposing substrate is formed in advance on the liquid crystal layer side of the opposing substrate. Some counter electrode 5
A pixel capacitor (CLC) 4 is formed between the pixel electrode 4 and the pixel electrode 4.

On the other hand, an inspection apparatus for an active matrix substrate according to the present invention in which such an active matrix substrate is inspected will be described. This inspection apparatus is composed of a liquid crystal layer and a counter electrode 5 bonded to the liquid crystal layer as described above.
Has a counter substrate formed in advance, and the liquid crystal layer and the counter substrate are used by bringing the liquid crystal layer into contact with the active matrix substrate. As shown in FIG. 3, a reference signal generating circuit 11, a frequency dividing circuit 12 for dividing the output signal from the reference signal generating circuit 11, and seven inputting signals from the frequency dividing circuit 12 Signal generation circuits 13 to 19;
Four switches 20 to 23 and four inspection terminals 24 to
27.

The B1 signal generation circuit 13 generates the signal B1 shown in FIG. B2
The signal generation circuit 14 generates a signal B2 and supplies it to the source bus line 2. The B3 signal generation circuit 15 generates a signal B3 and supplies it to the source bus line 2. The odd-numbered gate line signal generation circuit 16 generates an on / off control signal A1 for the gate bus line, and outputs the odd-numbered gate bus line 1
Give to. The even-numbered gate line signal generation circuit 17 generates a gate bus line ON / OFF control signal A2 and supplies it to the even-numbered gate bus line 1.

The counter electrode signal generating circuit 18 generates a signal C 1 fixed to a counter voltage value which is optimally adjusted so as to eliminate flicker, and supplies the signal C 1 to the counter electrode 5. The counter electrode signal generation circuit 19 generates a signal (not shown) that changes between a voltage at which the TFT 3 is turned on and a voltage at which the TFT 3 is turned off (hereinafter, this signal is referred to as C2), and supplies the signal to the counter electrode 5.
The waveform of the on / off control signal A1 applied to the odd-numbered gate bus line 1 and the waveform of the on / off control signal A2 applied to the even-numbered gate bus line 1 are the same. The timing is applied to the corresponding gate bus line 1 with a slight shift in timing. This is shown in FIG. 6, FIG. 9, FIG. 11, FIG.
The same applies to No. 6.

The signal B1 is a signal which remains at a constant level even after writing to each picture element by the TFT 3 until the next frame is written. A signal B2 is obtained by applying a picture element write signal to each picture element. A signal that changes to a voltage different from the signal voltage when the voltage of the signal is written until the picture element write signal of the next frame is applied, and the signal B
Reference numeral 3 denotes a signal that changes to a voltage different from the signal voltage when the signal voltage is written between the time when the picture element write signal is applied to each picture element and the time when the picture element write signal of the next frame is applied. is there.

The signal B1 from the B1 signal generation circuit 13
The signal B2 from the B2 signal generation circuit 14 and the signal B3 from the B3 signal generation circuit 15 are output to three terminals 20a, 20b, and 20c of the switch 20. The switch 20 selects one of the three terminals 20a, 20b, and 20c and supplies it to the inspection terminal 24. The inspection terminal 24 is in contact with the terminal 9a of the source bus line 2.

The ON / OFF control signal A1 from the odd gate line signal generating circuit 16 is output to two terminals 21a and 21b of three terminals 21a, 21b and 21c of the switch 21 and is opposed to the remaining one terminal 21c. The signal C2 from the electrode signal generation circuit 19 is output. Switch 21
Selects one of the three terminals 21a, 21b, 21c and gives it to the inspection terminal 25. The inspection terminal 25 is in contact with the terminal 7a of the odd-numbered gate bus line 1. The on / off control signal A2 from the even-numbered gate line signal generation circuit 17 is supplied to three terminals 22a and 22
b and 22c are output to two terminals 22a and 22c.
The signal C2 from the counter electrode signal generation circuit 19 is output to the two terminals 22b. The switch 22 has three terminals 2
2a, 22b, and 22c to select one of the inspection terminals 26
Give to. The inspection terminal 26 is in contact with the terminal 8a of the even-numbered gate bus line 1.

Signal C from counter electrode signal generation circuit 18
1 and the signal C2 from the counter electrode signal generation circuit 19 are output to the two terminals 21a and 21b of the switch 23. The switch 23 selects one of the two terminals 21a and 21b, and Give to 27. This inspection terminal 2
Reference numeral 7 contacts a terminal (not shown) of the counter electrode 5. The switches 20 to 23 are controlled by a control circuit (not shown), and the switches 21 and 22 are operated in conjunction with each other.

Next, a description will be given of a method of inspecting the above-described active matrix substrate by the above-described inspection apparatus. First,
The liquid crystal layer is brought into contact with the active matrix substrate to be inspected. At this time, the inspection terminal 24 is connected to the terminal 9a of the source bus line 2 and the inspection terminal 25 is connected to the terminal 7a provided at the end of the odd-numbered gate bus line 1.
The inspection terminal 26 is brought into contact with a terminal 8 a provided at the end of the even-numbered gate bus line 1, and the inspection terminal 27 is brought into contact with a terminal (not shown) provided on the counter electrode 5. After that, the switches 20 to 23 are switched so that the terminal 9a of the source bus line 2, the terminals 7a and 8a of the gate bus line 1,
A signal to be supplied to the terminal of the counter electrode 5 is selected. In this embodiment, the following six choices are adopted as shown in Table 1.

[0036]

[Table 1]

The switch 20 is selected as the terminal 20a, the switches 21 and 22 are connected to the terminals 21a and 22a, and the switch 23
Is selected as the terminal 23a, and the signal A1 (or A2) -B1
Inspection signal No1 performed at −C1 and switch 20 is connected to terminal 2
0b, and switches 21 and 22 are connected to terminals 21a and 22
a, the switch 23 is selected as the terminal 23a, and the signal A1
(Or A2) -Select the test signal No2 performed at -B2-C1 and the switch 20 as the terminal 20c, and select the switches 21 and 22.
To the terminals 21a and 22a, the switch 23 to the terminal 23a, the inspection signal No3 performed by the signal A1 (or A2) -B3-C1, and the switch 20 to the terminal 20a,
When the switches 21 and 22 are selected as the terminals 21a and 22a and the switch 23 is selected as the terminal 23b, the signal A1 (or A2)-
Inspection signal No4 performed in B1-C2, switch 20 is selected as terminal 20a, and switches 21 and 22 are selected as terminals 21a,
22a, the switch 23 is selected as the terminal 23b, and the inspection signal No5 performed by the signal A1 (or A2) -B1-C2
And the switch 20 is selected as the terminal 20a.
Is selected as the terminal 21b or 21c, the switch 22 is selected as the terminal 22b or 22c, and the switch 23 is selected as the terminal 23b. doing. In this embodiment, the case where the display mode is the normally white mode is taken as an example.

(Off Characteristic Defect Mode) First, the case of the off characteristic defect mode will be described. This off-characteristic defect mode is caused by a weak leak between the source electrode and the drain electrode of the TFT 3, as shown in FIG. In this case, as shown in FIG. 6, the inspection signal N is applied to the gate bus line 1, the source bus line 2, and the counter electrode 5.
Inspection is performed by giving signals o1, 2, and 3. At this time, T
In the portion of the defective picture element where the off characteristic of the FT3 is poor, as shown in Table 1 and (a) the weak leak portion in FIG. And the inspection signal No. 3 indicates a bright spot. As shown in Table 1, since the pattern of black display and the pattern of bright spot display are different from those of other defect detections as shown in Table 1, the display state is visually inspected to determine that the TFT 3 is in the off characteristic defect mode. You.

In this case, the correction is performed by disconnecting the gate bus line 1 from the gate electrode of the TFT 3 and connecting the source electrode and the drain electrode of the TFT 3 as shown in FIG. Fix it. For this correction, a laser beam or the like can be used. Also, laser light or the like is applied in the correction described below. In the case of the test signals Nos. 1, 2, and 3, the potential of the drain waveform D is different as shown in FIGS. 6A, 6B, and 6C.
If the potential is measured electrically, an inspection can be performed instead of a visual inspection.

(Leak Between Pixel Electrode and Source Bus Line) This defect is caused by strong leakage occurring between the pixel electrode 4 and the source bus line 2 as shown in FIG. In this case as well, the inspection signals No1,
Perform a few steps. At this time, in the above-described defective picture element portion, as shown in Table 1 and FIG.
o1 and the inspection signal No. 3 are displayed in black, and the inspection signal N
In o2, a bright spot is displayed. In this display state, as shown in Table 1, the pattern of the black display and the pattern of the bright spot display are different from those in the case of the other defect detection, so that the leak defect mode is determined. In this case, the correction is not performed because it is hardly seen as a defect in actual driving. Also in this case, since the potential in the drain waveform D is different as shown in FIGS. 9A, 9B, and 9C, it is possible to perform an inspection instead of a visual inspection by electrically measuring the potential. it can.

(Picture Defect Due to Leakage Between Auxiliary Capacitance Electrodes) As shown in FIG. 10A, this defect is caused by the pixel electrode 4 connected to a certain gate bus line 1 and the pixel electrode 4 This occurs due to a leakage that occurs between the storage capacitor 6 and the storage capacitor electrode connected to the next gate bus line 1. In this case, the inspection signal No.
Inspection cannot be performed in 1, 2, and 3, and the inspection signal No.
Perform steps 4 and 6. In the inspection signal No. 4, when the voltage of the counter electrode 5 is set to the gate voltage for turning off the TFT 3, the bright spot display is performed. In the inspection signal No. 6, when the gate bus line 1 on the storage capacitor electrode side is connected to the counter electrode and the gate voltage for turning off the TFT 3 to the gate voltage for turning on the TFT 3 is varied, bright points are displayed at all voltages. In this display state, as shown in Table 1, the pattern of the black display and the pattern of the bright spot display are different from those of the other defect detections. .

In this case, the correction is performed as shown in FIG.
T3 is cut off, and the source and drain electrodes of TFT3 are connected. In addition, the storage capacitor electrode is separated from the gate bus line 1.

Also in this case, the potential of the drain waveform D becomes
Since the potentials are different as shown in FIGS. 11A, 11B, and 11C, the potential can be electrically measured to perform an inspection instead of a visual inspection.

For reference, as shown in FIG. 12 (the voltage applied to the counter electrode is taken on the horizontal axis and the effective value voltage applied between the liquid crystals is taken on the vertical axis), Even if the inspection signal No. is variously changed, it will be within the range of black display as shown by the curve L1. , And has a range in which a bright point is displayed. In the case of a pixel defect due to a leak between the auxiliary capacitance electrodes, the above-described curve L2
Is detected based on Further, a pixel defect due to a leak between a gate and a drain of a TFT described later is also detected for the same reason.

(Picture Defects Due to Leakage Between Counter Electrode and Pixel Electrode) This defect is caused by the state in which the counter electrode and the pixel electrode are electrically connected. As shown in FIG. 1, bright spots are displayed regardless of any of the inspection signals No. 1 to No. 6, and a display state different from other defects is obtained. This makes it possible to detect a pixel defect due to a leak between the counter electrode and the pixel electrode. The correction in this case can be performed by finding a defective portion by visual observation or the like when a conductive foreign matter is sandwiched between the electrodes, and performing processing according to the defect state.

(Picture Defect Due to Leak Between TFT Gate and Drain) This defect is caused by leakage between the gate electrode and the drain electrode of the pixel driving TFT 3 as shown in FIG. Caused by When this defect has occurred, the inspection cannot be performed with the inspection signals Nos. 1, 2 and 3, and the inspection signals Nos. 4 and 6 are performed. In the inspection signal No. 4, when the voltage of the counter electrode 5 is set to the gate voltage for turning off the TFT 3, the bright spot display is performed. In the inspection signal No. 6, the gate bus line 1 on the storage capacitor electrode side
Is connected to the opposing electrode and the gate voltage for turning off the TFT3 is varied from the gate voltage for turning on the TFT3. Unlike the case of the picture element defect due to the leak between the auxiliary capacitance electrodes, the voltage of the opposing electrode is changed to the gate for turning off the TFT3. Only when the voltage is set, the bright spot is displayed. In this display state, as shown in Table 1, the patterns of black display and bright spot display are different from those of other defect detections.
A pixel defect due to a leak between the gate and the drain is determined. In this case, as shown in FIG. 13B, the connection between the gate bus line 1 and the TFT 3 and the connection between the source electrode and the drain electrode of the TFT 3 are made as shown in FIG.

Also in this case, the potential of the drain waveform D becomes
Since the potentials are different as shown in FIGS. 14 (a), (b), and (c), the potential can be electrically measured to perform an inspection instead of a visual inspection.

(Line defect due to leakage between gate bus line and source bus line) This defect is shown in FIG.
As shown in FIG. 2, the leakage occurs between the gate bus line 1 and the source bus line 2, and the picture element electrodes arranged in a horizontal line connected to the gate bus line 1 where the leakage occurs and the leakage occur. A display defect occurs with the vertically aligned picture element electrodes connected to the source bus line 2, that is, displayed as a cross-shaped line defect.

When the above-mentioned defect occurs, the amplitude of the gate voltage for turning off the TFT from the gate voltage for turning off the TFT becomes smaller than the normal state due to the influence of the signal on the source bus line 2, so that the on-resistance of the TFT 3 also decreases. The off resistance cannot be maintained sufficiently. Therefore, the TFT 3 connected to the source bus line 2 and the leaking gate bus line 1 has a TFT 3 with an apparently poor off characteristic.
It shows the same behavior as. Therefore, the detection of this defect
This is performed based on the inspection signals No. 1 and No. 3. At this time, the inspection signal N
Inspection signal No3
In the case where the inspection is performed, the state of the horizontal line displayed as the line defect is clearly visually observed. At this time, the vertical lines based on the picture element electrodes connected to the source bus line 2 are also clearly visible. Therefore, a defective portion is determined based on the cross-shaped cross portion clearly shown. In this case, as shown in FIG. 15 (b), both sides of the source bus line 2 where the leak occurs are cut and the corresponding source bus line 2 is cut.
Signal from both ends.

Also in this case, the potential of the gate signal waveform E at the time of leakage between the gate bus line 1 and the source bus line 2 is different as shown in FIGS. 16 (a), (b) and (c). By electrically measuring the potential, an inspection can be performed instead of a visual inspection.

Embodiment 2 FIG. 17 shows the whole structure of an active matrix substrate using TFTs as switching elements, and FIG. 18 shows a part thereof. In this substrate, a plurality of gate bus lines 1 functioning as scanning lines are wired in parallel, and a large number of source bus lines 2 functioning as signal lines are wired in parallel with the gate bus lines 1. In the vicinity of the position where both bus lines 1 and 2 intersect, TF
T3 is provided, and a picture element electrode 4 is connected to the TFT3. The gate bus line 1 and the source bus line 2 are provided along the periphery of the picture element electrode 4. An auxiliary capacitance (CS) 6 is provided between the drain electrode of the TFT 3 and an auxiliary capacitance common line 29 provided in parallel with the gate bus line 1 to which the TFT 3 is connected. That is, this active matrix substrate is a so-called CS-O
It has an N-Common structure.

Further, the gate bus lines 1 are connected by a common wiring 28, and terminals 28a are provided at both ends of the common wiring 28. The auxiliary capacitance common wirings 29 are connected to a common wiring 8, and auxiliary capacitance terminals 8 a are provided at both ends of the common wiring 8. One end of the source bus line 2 is connected to a common wiring 9, and terminals 9 a are provided at both ends of the wiring 9.

When an opposing substrate on which a liquid crystal layer and an opposing electrode are formed in advance on the active matrix substrate having such a configuration is disposed so as to face the liquid crystal layer on the active matrix substrate side, the opposing substrate is formed in advance on the liquid crystal layer side of the opposing substrate. Some counter electrode 5
A pixel capacitor (CLC) 4 is formed between the pixel electrode 4 and the pixel electrode 4.

On the other hand, a description will be given of an active matrix substrate inspection apparatus of the present invention in which such an active matrix substrate is inspected. This inspection apparatus is composed of a liquid crystal layer and a counter electrode 5 bonded to the liquid crystal layer as described above.
Has a counter substrate formed in advance, and the liquid crystal layer and the counter substrate are used by bringing the liquid crystal layer into contact with the active matrix substrate. As shown in FIG. 19, a reference signal generating circuit 31, a frequency dividing circuit 32 for dividing the output signal from the reference signal generating circuit 31, and seven inputting signals from the frequency dividing circuit 32. Signal generation circuits 33 to 39
, Three switches 40 to 42 and four inspection terminals 4
3 to 46.

The B1 signal generation circuit 33 generates the signal B1 shown in FIG. B
Two-signal generation circuit 34 generates signal B2 and supplies it to source bus line 2. The B3 signal generation circuit 35 outputs the signal B3
Is generated and applied to the source bus line 2. The gate line signal generation circuit 36 generates an on / off control signal A3 for the gate bus line and supplies it to the gate bus line 1. The gate-off voltage signal generation circuit 37 generates an off-control signal A4 (not shown) for the gate bus line,
Is supplied to the auxiliary capacitance common line 29 when the data is switched. The counter electrode signal generation circuit 38 generates a signal C 1 fixed to a counter voltage value that is optimally adjusted so as to eliminate flicker, and supplies the generated signal C 1 to the counter electrode 5. Counter electrode signal generating circuit 39
Is a signal (not shown) that varies between a voltage for turning on the TFT 3 and a voltage for turning off the TFT 3
) Is given to the counter electrode 5.

The signal B1 is a signal which remains unchanged after writing to each picture element by the TFT 3 until the next frame is written. A signal B2 is obtained by applying a picture element write signal to each picture element. A signal that changes to a voltage different from the signal voltage when the voltage of the signal is written until the picture element write signal of the next frame is applied, and the signal B
Reference numeral 3 denotes a signal that changes to a voltage different from the signal voltage when the signal voltage is written between the time when the picture element write signal is applied to each picture element and the time when the picture element write signal of the next frame is applied. is there.

The signal B1 from the B1 signal generation circuit 33
The signal B2 from the B2 signal generation circuit 34 and the signal B3 from the B3 signal generation circuit 35 are output to three terminals 40a, 40b, and 40c of the switch 40. The switch 40 selects one of the three terminals 40 a, 40 b, and 40 c and supplies the selected terminal to the inspection terminal 43. The inspection terminal 43 is connected to the terminal 9a of the source bus line 2.

The on / off control signal A 3 from the gate line signal generation circuit 36 is applied to the inspection terminal 44. The inspection terminal 44 is connected to the terminal 2 of the gate bus line 1.
8a. The off-control signal A4 from the gate-off voltage signal generation circuit 37 is output to one terminal 41b of three terminals 41a, 41b, and 41c of the switch 41.
The remaining two terminals 41a and 41c are supplied with a signal C1 from the counter electrode signal generation circuit 38 and a signal C2 from the counter electrode signal generation circuit 39. Switch 41
Selects one of the three terminals 41 a, 41 b, 41 c and applies a corresponding signal to the inspection terminal 45. The inspection terminal 45 is connected to the auxiliary capacitance terminal 8a. The signals C1 and C2 described above are connected to the switch 4
2 terminal 42a and terminals 42b and 42c. The switch 42 has three terminals 42a, 42b, 42
c is selected and a corresponding signal is given to the inspection terminal 46. The inspection terminal 46 is connected to a terminal (not shown) provided on the counter electrode. Note that the switches 40 to
The control 42 is controlled by a control circuit (not shown) and operates in conjunction with each other.

Next, a method for inspecting the above-described active matrix substrate by the above-described inspection apparatus will be described. First,
The liquid crystal layer is brought into contact with the active matrix substrate to be inspected. At this time, the inspection terminal 43 is connected to the terminal 9 a of the source bus line 2, the inspection terminal 44 is connected to the terminal 28 a of the gate bus line 1, and the inspection terminal 45 is connected to a common wiring in which the auxiliary capacitance common wiring 29 is connected. The inspection terminal 46 is brought into contact with a terminal (not shown) provided on the counter electrode 5 with the auxiliary capacitance terminal 8 a provided at the end of the counter electrode 8. Thereafter, the switches 40 to 42 are switched to connect the terminal 9 a of the source bus line 2 and the terminal 28 of the gate bus line 1.
a, a signal to be given to the terminal 8a for the auxiliary capacitance and the terminal of the counter electrode 5 are selected. This selection employs the following six types in this embodiment as shown in Table 2.

[0060]

[Table 2]

The switch 40 is selected as the terminal 40a, and the switches 41 and 42 are selected as the terminals 41a and 42a.
0 is selected as the terminal 40b, and the switches 41 and 42 are connected to the terminal 4b.
1a, 42a, the inspection signal No2 performed by the signal A3-B2-C1, the switch 40 is selected as the terminal 40c, the switches 41, 42 are selected as the terminals 41a, 42a, and the signal A3-B3-C1 is selected. And the switch 40 is selected as the terminal 40a, and the switches 41 and 42 are selected.
Are selected as terminals 41b and 42b, and signals A3-A4-B
Inspection signal No. 4 performed in 1-C2, switch 40 is selected as terminal 40a, and switches 41 and 42 are selected as terminals 41b and 4b.
2b, the inspection signal No5 performed by the signal A3-A4-B1-C2, and the switch 40 are selected as the terminal 40a,
Select the switches 41 and 42 to the terminals 41c and 42c,
Inspection signals No. 6 performed with signals A3-B1-C2 are employed. In this embodiment, the case where the display mode is the normally white mode is taken as an example.

(Off Characteristic Defect Mode) First, the case of the off characteristic defect mode will be described. This off-characteristic defect mode is caused by a weak leak between the source electrode and the drain electrode of the TFT 3, as shown in FIG. In this case, as shown in FIG. 22, inspection is performed by applying inspection signals No. 1, 2, and 3 to the gate bus line 1, the source bus line 2, and the counter electrode 5. At this time, in the defective picture element portion where the off-characteristics of the TFT 3 are poor, the signal C1 of the optimum counter voltage is used in Table 2 and FIG.
(A) As shown in the weak leak portion, the inspection signal No.
1, the black signal is displayed, and the inspection signal No. 2 and the inspection signal No.
In the case of 3, a bright spot is displayed. As shown in Table 2, since the pattern of black display and the pattern of bright spot display are different from those of the other defect detections as shown in Table 2, the display is visually inspected to determine that the TFT 3 is in the off characteristic defect mode. You.

In this case, the correction is performed by disconnecting the gate bus line 1 from the gate electrode of the TFT 3 and connecting the source electrode and the drain electrode of the TFT 3 as shown in FIG. Fix it. For this correction, a laser beam or the like can be used. Also, laser light or the like is applied in the correction described below. In the case of the test signals Nos. 1, 2, and 3, the potentials of the drain waveform D are different as shown in FIGS. 22A, 22B, and 22C. Can be tested instead of

(Leak Between Pixel Electrode and Source Bus Line) As shown in FIG. 23, this defect is caused by strong leakage occurring between the pixel electrode 4 and the source bus line 2. In this case as well, the inspection signals No1,
Perform a few steps. At this time, in the above-described defective picture element portion, as shown in Table 2 and the strong leak portion of FIG. 7B, the inspection signal No. 1 and inspection signal No. The display is black, and the inspection signal No. 2 is a bright spot display. This display state is shown in Table 2.
As shown in FIG. 7, since the pattern of black display and the pattern of bright spot display are different from those of the other defect detections, the leak failure defect mode is determined. In this case, the correction is not performed because it is hardly seen as a defect in actual driving. Also in this case, since the potential in the drain waveform D is different as shown in FIGS. it can.

(Picture Defect Due to Leakage Between Auxiliary Capacitance Electrodes) As shown in FIG. 25A, this defect is caused by the pixel electrode 4 connected to a certain gate bus line 1 and the pixel electrode 4 The storage capacitor 6 is configured to face the common wiring 29
Occurs due to leakage occurring between the storage capacitor electrode connected to the storage capacitor and the storage capacitor. In this case, the inspection signals No. 1, 2, 3
Inspection cannot be performed, and inspection signals No. 4, 5, 6
I do. In the inspection signals Nos. 4 and 5, the common line 29 for the auxiliary capacitance is connected to the gate-off voltage, and the voltage of the counter electrode 5 is set to T.
When the gate voltage for turning off FT3 is set, a bright spot is displayed. When the gate voltage is turned on, a black point occurs.
In the inspection signal No. 6, when the common line 29 for the auxiliary capacitance on the electrode side for the auxiliary capacitance is connected to the counter electrode and the gate voltage for turning off the TFT 3 to the gate voltage for turning on the TFT 3 is varied, bright spots are displayed at all voltages. . This display state
As shown in Table 2, since the pattern of black display and the pattern of bright spot display are different from those of other defect detections, a pixel defect due to a leak between the auxiliary capacitance electrodes is determined.

In this case, the correction is made by the gate bus line 1 and the defective picture element TF as shown in FIG.
T3 is cut off, and the source and drain electrodes of TFT3 are connected. In addition, the storage capacitor electrode is separated from the gate bus line 1.

Also in this case, the potential of the drain waveform D becomes
As shown in FIGS. 26A, 26B, and 26C, the potential can be inspected instead of the visual inspection by electrically measuring the potential.

For reference, as shown in FIG. 12, in the case of a normal picture element, even if the inspection signal No. is variously changed, the inspection signal No is within the range of black display as shown by a curve L1. When the signal No. is variously changed in 4 to 6, the curve L2
As shown in FIG. 2, the display area has a range in which bright spots are displayed, as well as in the range of black display. In the case of a picture element defect due to a leak between the auxiliary capacitance electrodes, it is detected based on the above-described curve L2. Further, a pixel defect due to a leak between a gate and a drain of a TFT described later is also detected for the same reason.

(Picture Defect Due to Leak Between Counter Electrode and Pixel Electrode) This defect is caused by the state where the counter electrode and the pixel electrode are electrically connected to each other. As shown in FIG. 2, a bright spot is displayed regardless of any of the inspection signals No. 1 to No. 6, and a display state different from other defects is obtained. This makes it possible to detect a pixel defect due to a leak between the counter electrode and the pixel electrode. The correction in this case can be performed by finding a defective portion by visual observation or the like when a conductive foreign matter is sandwiched between the electrodes, and performing processing according to the defect state.

(Picture Defect Due to Leak Between TFT Gate and Drain) This defect is caused by leakage between the gate electrode and the drain electrode of the pixel driving TFT 3 as shown in FIG. Caused by When this defect has occurred, the inspection cannot be performed with the inspection signals Nos. 1, 2 and 3, and the inspection signals Nos. 4 and 6 are performed. In the inspection signal No. 4, when the common line 29 for the auxiliary capacitance is connected to the gate-off voltage and the voltage of the counter electrode 5 is set to the gate voltage for turning off the TFT 3, a bright spot is displayed. Inspection signal N
In o6, when the gate bus line 1 on the storage capacitor electrode side is connected to the counter electrode and the gate voltage for turning off the TFT 3 to the gate voltage for turning on the TFT 3 is varied, the above-mentioned pixel defect due to the leak between the storage capacitor electrodes Unlike,
Only when the voltage of the counter electrode is set to the gate voltage for turning off the TFT 3 is a bright spot display. As shown in Table 2, since the pattern of black display and the pattern of bright spot display are different from those of the other defect detections, as shown in Table 2, the pixel defect caused by the leak between the gate and the drain of the TFT is thereby reduced. Is determined.

In this case, as shown in FIG. 27B, the connection between the gate bus line 1 and the TFT 3 is cut and the connection between the source electrode and the drain electrode of the TFT 3 is made.

Also in this case, the potential of the drain waveform D becomes
As shown in FIGS. 28 (a), (b), and (c), the potential can be inspected instead of the visual inspection by electrically measuring the potential.

(Line defect due to leakage between gate bus line and source bus line) This defect is shown in FIG.
As shown in FIG. 2, the leakage occurs between the gate bus line 1 and the source bus line 2, and the picture element electrodes arranged in a horizontal line connected to the gate bus line 1 where the leakage occurs and the leakage occur. A display defect occurs with the vertically aligned picture element electrodes connected to the source bus line 2, that is, displayed as a cross-shaped line defect.

When the above defect occurs, the amplitude of the gate voltage for turning off the TFT from the gate voltage for turning off the TFT becomes smaller than that in the normal state due to the influence of the signal on the source bus line 2. The off resistance cannot be maintained sufficiently. Therefore, the TFT 3 connected to the source bus line 2 and the leaking gate bus line 1 has a TFT 3 with an apparently poor off characteristic.
It shows the same behavior as. Therefore, the detection of this defect
This is performed based on the inspection signals No. 1 and No. 3. At this time, the inspection signal N
Inspection signal No3
In the case where the inspection is performed, the state of the horizontal line displayed as the line defect is clearly visually observed. At this time, the vertical lines based on the picture element electrodes connected to the source bus line 2 are also clearly visible. Therefore, a defective portion is determined based on the cross-shaped cross portion clearly shown. In this case, as shown in FIG. 29 (b), both sides of the leak location of the source bus line 2 are cut and the corresponding source bus line 2 is cut.
Signal from both ends.

Also in this case, the potentials of the gate signal waveform E at the time of leakage between the gate bus line 1 and the source bus line 2 are different as shown in FIGS. By electrically measuring the potential, an inspection can be performed instead of a visual inspection.

Therefore, according to the present invention, a defect mode which cannot be detected conventionally can be inspected, and a defect can be corrected based on the inspection result. This allows
The yield rate of the active matrix substrate can be improved by improving the yield rate of the active matrix substrate. In addition,
In the present invention, it is a matter of course that the ON failure defect mode can be detected.

[0077]

According to the present invention, it is possible to detect a TFT off-characteristic defect or a pixel defect due to a leak or the like which could not be detected until a gate driver IC for actually driving is mounted. Further, the detected defect can be corrected.

[Brief description of the drawings]

FIG. 1 is a plan view showing an entire active matrix substrate to which an active matrix substrate inspection method according to a first embodiment is applied.

FIG. 2 is a plan view showing a part of the active matrix substrate of FIG.

FIG. 3 is a block diagram illustrating an active matrix substrate inspection apparatus according to the first embodiment.

FIG. 4 is a signal waveform diagram used in the active matrix substrate inspection method according to the first embodiment.

FIG. 5A is a schematic diagram illustrating a defect state in an off-characteristic defect mode detected according to the first embodiment, and FIG. 5B is a schematic diagram illustrating a repaired part.

6A and 6B show a voltage when detecting an off-characteristic defect mode. FIG. 6A is a diagram showing a potential at a drain electrode in the case of an inspection signal No. 1, and FIG. 6B is a diagram showing a drain electrode in a case of an inspection signal No. FIG. 7C is a diagram showing the potential at the drain electrode when the test signal No. 3 is used.

FIG. 7 is a graph showing the relationship between the leakage resistance between the source / drain or source bus line of the TFT and the pixel electrode on the horizontal axis and the effective voltage applied between the liquid crystals on the vertical axis. .

FIG. 8 is a schematic diagram showing a defect state in the case of a leak between a picture element electrode and a source bus line detected according to the first embodiment.

FIG. 9 shows a voltage for detecting a leak between a picture element electrode and a source bus line.
FIG. 3B is a diagram showing the potential at the drain electrode in the case of FIG.
FIG. 4 is a diagram showing a potential at the drain electrode when the test signal No. 2 is used, and FIG. 4C is a diagram showing a potential at the drain electrode when the test signal No. 3 is used.

FIG. 10A is a schematic diagram showing a defect state in the case of a picture element defect due to a leak between auxiliary capacitance electrodes detected according to the first embodiment, and FIG. 10B is a schematic diagram showing a repaired part.

FIGS. 11A and 11B show voltages for detecting a picture element defect due to a leak between auxiliary capacitance electrodes, and FIG.
FIG. 7B is a diagram showing a potential at the drain electrode when the test signal No. 2 is used, FIG. 7B is a diagram showing a potential at the drain electrode when the test signal No. 2 is used, and FIG. is there.

FIG. 12 is a graph showing the relationship between the voltage applied to the counter electrode on the horizontal axis and the effective voltage applied between the liquid crystals on the vertical axis.

13A is a schematic diagram showing a defect state in the case of a picture element defect due to a leak between a gate and a source of a TFT detected according to the first embodiment, and FIG. 13B is a schematic diagram showing a repaired portion. .

14A and 14B show a voltage when detecting a picture element defect due to a leak between a gate and a source of a TFT, and FIG. 14A is a diagram showing a potential at a drain electrode according to a test signal No. 1; () Is a diagram showing the potential at the drain electrode when the test signal No. 2 is used, and (c) is a diagram showing the potential at the drain electrode when the test signal No. 3 is used.

15A is a schematic diagram showing a defect state in the case of a line defect due to a leak between a gate bus line and a source bus line detected according to the first embodiment, and FIG. 15B is a schematic diagram showing a repaired part; is there.

16A and 16B show voltages when detecting a line defect due to a leak between a gate bus line and a source bus line, and FIG. 16A shows the voltage between the gate bus line and the source bus line when the inspection signal No1 is used. FIG. 7B shows a gate signal waveform E at the time of leakage, FIG. 7B shows a gate signal waveform E at the time of normal operation when the inspection signal No. 2 is used, and FIG. FIG. 9 is a diagram showing a gate signal waveform E at the time of leakage between the gate signal waveform E and the gate signal waveform E.

FIG. 17 is a plan view showing the entire active matrix substrate to which the active matrix substrate inspection method according to the second embodiment is applied.

18 is a plan view showing a part of the active matrix substrate of FIG.

FIG. 19 is a block diagram illustrating an active matrix substrate inspection apparatus according to a second embodiment.

FIG. 20 is a signal waveform diagram used in the active matrix substrate inspection method according to the second embodiment.

21A is a schematic diagram illustrating a defect state in the off-characteristic defect mode detected according to the second embodiment, and FIG. 21B is a schematic diagram illustrating a repaired part.

FIGS. 22A and 22B show voltages at the time of detecting an off-characteristic defect mode. FIG. 22A shows the potential at the drain electrode in the case of the inspection signal No. 1, and FIG. 22B shows the drain electrode in the case of the inspection signal No. FIG. 7C is a diagram showing the potential at the drain electrode when the test signal No. 3 is used.

FIG. 23 is a schematic diagram showing a defect state in the case of a leak between a picture element electrode and a source bus line detected according to the second embodiment.

FIG. 24 shows a voltage for detecting a leak between a picture element electrode and a source bus line, and FIG.
FIG. 6 is a diagram showing a potential at a drain electrode in the case of o1;
(B) is a diagram showing the potential at the drain electrode when the test signal No. 2 is used, and (c) is a diagram showing the potential at the drain electrode when the test signal No. 3 is used.

FIG. 25A is a schematic diagram showing a defect state in the case of a picture element defect due to a leak between auxiliary capacitance electrodes detected according to the second embodiment, and FIG. 25B is a schematic diagram showing a repaired part.

26A and 26B show voltages for detecting a picture element defect due to a leak between storage capacitor electrodes, and FIG.
FIG. 7B is a diagram showing a potential at the drain electrode when the test signal No. 2 is used, FIG. 7B is a diagram showing a potential at the drain electrode when the test signal No. 2 is used, and FIG. is there.

FIG. 27A is a schematic diagram showing a defect state in the case of a picture element defect due to a leak between a gate and a source of a TFT detected according to the second embodiment, and FIG. .

28A and 28B show voltages when detecting a pixel defect due to a leak between a gate and a source of a TFT. FIG. () Is a diagram showing the potential at the drain electrode when the test signal No. 2 is used, and (c) is a diagram showing the potential at the drain electrode when the test signal No. 3 is used.

FIG. 29A is a schematic diagram illustrating a defect state in the case of a line defect due to a leak between a gate bus line and a source bus line detected according to the second embodiment, and FIG. is there.

30A and 30B show voltages when detecting a line defect due to a leak between a gate bus line and a source bus line, and FIG. 30A shows a voltage between the gate bus line and the source bus line when the inspection signal No1 is used; FIG. 7B shows a gate signal waveform E at the time of leakage, FIG. 7B shows a gate signal waveform E at the time of normal operation when the inspection signal No. 2 is used, and FIG. FIG. 9 is a diagram showing a gate signal waveform E at the time of leakage between the gate signal waveform E and the gate signal waveform E.

FIG. 31 shows a signal application state by a conventional inspection method, Cs
It is a schematic diagram shown with an active matrix substrate having an -On-Gate structure.

FIG. 32 is a partially enlarged plan view showing an active matrix substrate having a Cs-On-Gate structure in FIG. 31;

FIG. 33 is a waveform diagram of a signal used in a conventional inspection method performed on an active matrix substrate having a Cs-On-Gate structure.

FIG. 34 shows a signal application state according to the conventional inspection method as Cs
It is a schematic diagram shown with an active matrix substrate having an -On-Common structure.

FIG. 35 is a partially enlarged plan view of the active matrix substrate having the Cs-On-Common structure of FIG. 34;

FIG. 36 is a waveform diagram of a signal used in a conventional inspection method performed on an active matrix substrate having a Cs-On-Common structure.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Gate bus line 2 Source bus line 3 TFT 4 Picture element electrode 5 Counter electrode 6 Auxiliary capacitance 7 Wiring 7a Terminal 8 Wiring 8a Terminal 9 Wiring 9a Terminal 11 Reference signal generation circuit 12 Divider circuit 13 B1 signal generation circuit 14 B2 signal generation Circuit 15 B3 signal generation circuit 16 Odd gate line signal generation circuit 17 Even gate line signal generation circuit 18 Counter electrode signal generation circuit 19 Counter electrode signal generation circuit 20 Switch 21 Switch 22 Switch 23 Switch 24 Inspection terminal 25 Inspection terminal 26 inspection terminal 27 inspection terminal 28 common wiring 28a terminal 29 auxiliary capacitance common wiring 31 reference signal generation circuit 32 divider circuit 33 B1 signal generation circuit 34 B2 signal generation circuit 35 B3 signal generation circuit 36 gate line signal generation circuit 37 Gate-off voltage signal Generating circuit 38 the counter electrode signal generating circuit 39 the counter electrode signal generating circuit 40 switch 41 switch 42 switch 43 inspection terminal 44 inspection terminal 45 inspection terminal 46 inspection terminal

──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Kiyoshi Nakazawa 22-22 Nagaikecho, Abeno-ku, Osaka-shi, Osaka Inside Sharp Corporation (72) Inventor Makoto Miyago 22-22 Nagaikecho, Abeno-ku, Osaka-shi, Osaka Sharp Corporation (72) Inventor Makoto Tachibana 22-22 Nagaike-cho, Abeno-ku, Osaka-shi, Osaka Inside Sharp Corporation (72) Inventor Ken Kanamori 22-22 Nagaike-cho, Abeno-ku, Osaka-shi, Osaka Sharp Corporation (56) References JP-A-5-313134 (JP, A) European Patent Application Publication 493025 (EP, A1) (58) Fields investigated (Int. Cl. ⁶ , DB name) G02F 1/13 101 G02F 1/136 G02F 1 / 1343 G02F 1/133 G02F 9/30 G09G 3/36 G01R 31/00 H01L 29/78

Claims (12)

(57) [Claims] 1. A plurality of picture element electrodes and thin film transistors for driving each picture element electrode are arranged in a matrix on an insulating substrate, are connected to the thin film transistors, and are formed so as to cross each other. Each pixel electrode is connected to the scanning line and the signal line via the thin film transistor, and an auxiliary capacitor formed in relation to the pixel electrode is connected to the scanning line to which the pixel electrode is connected. Is a method for inspecting an active matrix substrate connected to another scanning line adjacent to a picture element electrode, comprising: a counter substrate having a counter electrode disposed to face the active matrix substrate; A liquid crystal layer formed and arranged on the active matrix substrate side;
Using an inspection device having a scanning line, a signal line, and a connection terminal for connecting to the counter electrode, respectively, disposing the inspection device in opposition to the active matrix substrate, and scanning the connection terminal. Connecting to each of the line, the signal line and the counter electrode; and alternately applying an ON signal defining a period of one frame and an OFF signal following the ON signal to the scanning line of the active matrix substrate, A first pattern for changing the level of the voltage applied to the signal line before the application of the ON signal to each of the two frames to be applied, and the level of the voltage applied to the signal line before and after the application of the ON signal to each of the two adjacent frames. A second pattern for changing, and a third pattern for changing the level of the voltage applied to the signal line after the application of the ON signal to each of the two consecutive frames. Small of
By performing at least two patterns, multiple types of defect modes
A method for inspecting an active matrix substrate, the method comprising: 2. A plurality of picture element electrodes and thin film transistors for driving the picture element electrodes are arranged in a matrix on an insulating substrate, are connected to the thin film transistors, and are formed so as to cross each other. Each pixel electrode is connected to the scanning line and the signal line via the thin film transistor, and an auxiliary capacitor formed in relation to the pixel electrode is connected to the scanning line to which the pixel electrode is connected. Is a method for inspecting an active matrix substrate connected to another scanning line adjacent to a picture element electrode, comprising: a counter substrate having a counter electrode disposed to face the active matrix substrate; A liquid crystal layer formed and arranged on the active matrix substrate side;
Using an inspection device having a scanning line, a signal line, and a connection terminal for connecting to the counter electrode, respectively, disposing the inspection device in opposition to the active matrix substrate, and scanning the connection terminal. Connecting to each of the line, the signal line and the counter electrode; and alternately applying an ON signal defining a period of one frame and an OFF signal following the ON signal to the scanning line of the active matrix substrate, A first pattern for changing the level of the voltage applied to the signal line before the application of the ON signal to each of the two frames to be applied, and the level of the voltage applied to the signal line before and after the application of the ON signal to each of the two adjacent frames. A second pattern for changing, and a third pattern for changing the level of the voltage applied to the signal line after the application of the ON signal to each of the two consecutive frames. Small of
Performing at least two patterns , further setting the voltage applied to the counter electrode to an on-voltage of the thin film transistor applied to a scanning line, and changing the voltage applied to the counter electrode to the thin film transistor applied to a scanning line. And selectively detecting the defect mode by changing between the on-voltage and the off-voltage while the storage capacitor is connected to the counter electrode. Inspection method for active matrix substrates. 3. A plurality of picture element electrodes and thin film transistors for driving each picture element electrode are arranged in a matrix on an insulating substrate, are connected to the thin film transistors, and are formed so as to cross each other. Each pixel electrode is connected to the scanning line and the signal line via the thin film transistor, and an auxiliary capacitor formed in relation to the pixel electrode is connected to the scanning line to which the pixel electrode is connected. An inspection apparatus for an active matrix substrate connected to another scanning line adjacent to the picture element electrode, comprising: a counter substrate having a counter electrode disposed in a state facing the active matrix substrate; A liquid crystal layer formed on the side of the counter electrode and disposed on the side of the active matrix substrate; connection terminals for connecting to the scanning line, the signal line and the counter electrode, respectively; And detecting means for detecting a defect mode active matrix substrate, the detecting means, 1 to the scanning line of the active matrix substrate
A first method of alternately providing an ON signal for defining a frame period and an OFF signal subsequent to the ON signal, and changing a level of a voltage applied to a signal line before applying an ON signal to each of two successive frames. A pattern, a second pattern for changing the level of the voltage applied to the signal line before and after the on-signal is applied to each of the two successive frames, and a second pattern for changing the level of the voltage applied to the signal line before and after each of the two successive frames By performing at least two patterns of the third pattern for changing the voltage level,
An inspection apparatus for an active matrix substrate configured to identify a kind of defect mode . 4. A plurality of pixel electrodes and thin film transistors for driving each of the pixel electrodes are arranged in a matrix on an insulating substrate, and are formed so as to be connected to the thin film transistors and to cross each other. Each pixel electrode is connected to the scanning line and the signal line via the thin film transistor, and an auxiliary capacitor formed in relation to the pixel electrode is connected to the scanning line to which the pixel electrode is connected. An inspection apparatus for an active matrix substrate connected to another scanning line adjacent to the picture element electrode, comprising: a counter substrate having a counter electrode disposed in a state facing the active matrix substrate; A liquid crystal layer formed on the side of the counter electrode and disposed on the side of the active matrix substrate; connection terminals for connecting to the scanning lines, signal lines and the counter electrode, respectively; And detecting means for detecting a defect mode active matrix substrate, the detecting means, 1 to the scanning line of the active matrix substrate
A first method of alternately providing an ON signal for defining a frame period and an OFF signal subsequent to the ON signal, and changing a level of a voltage applied to a signal line before applying an ON signal to each of two successive frames. A pattern, a second pattern for changing the level of the voltage applied to the signal line before and after the on-signal is applied to each of the two successive frames, and a second pattern for changing the voltage level applied to the signal line before and after the on-signal is applied to each of the two successive frames Performing at least two of the third pattern for changing the voltage level, further setting a voltage applied to the counter electrode to an on-voltage of the thin film transistor applied to a scanning line; To the off-voltage of the thin film transistor applied to the scanning line, and the on-state voltage with the storage capacitor connected to the counter electrode. With the off-voltage testing device of the active matrix substrate has a configuration to detect a defect mode performed selectively and be varied between. 5. A plurality of pixel electrodes and thin film transistors for driving each of the pixel electrodes are arranged in a matrix on an insulating substrate, and are formed so as to be connected to the thin film transistors and to intersect each other. Each pixel electrode is connected to the scanning line and the signal line via the thin film transistor, and an auxiliary capacitor formed in relation to the pixel electrode is connected to the scanning line to which the pixel electrode is connected. A method for repairing a defect of an active matrix substrate connected to another scanning line adjacent to a pixel electrode therebetween, comprising: a counter substrate having a counter electrode disposed to face the active matrix substrate; and a counter electrode side of the counter substrate. A liquid crystal layer formed on the active matrix substrate side,
Using an inspection device having a scanning line, a signal line, and a connection terminal for connecting to the counter electrode, respectively, disposing the inspection device in opposition to the active matrix substrate, and scanning the connection terminal. Connecting to each of the line, the signal line and the counter electrode; alternately applying an ON signal defining a period of one frame and an OFF signal following the ON signal to the scanning line of the active matrix substrate; A first pattern for changing the level of a voltage applied to a signal line before applying an ON signal to each of two preceding and succeeding frames, and a voltage level applied to a signal line before and after applying an ON signal to each of two preceding and succeeding frames The second pattern that changes
And a third pattern for changing the level of the voltage applied to the signal line after the application of the ON signal for each of the three frames.
By performing at least two patterns, multiple types of defect models
A method for repairing a defect in an active matrix substrate, comprising the steps of: identifying a memory card; and repairing a defect according to a detected defect mode. 6. A plurality of picture element electrodes and thin film transistors for driving each picture element electrode are arranged in a matrix on an insulating substrate, and are connected to the thin film transistors and formed so as to cross each other. Each pixel electrode is connected to the scanning line and the signal line via the thin film transistor, and an auxiliary capacitance formed in relation to the pixel electrode is a scanning line to which the pixel electrode is connected. In a method for repairing a defect of an active matrix substrate connected to another scanning line adjacent to a pixel electrode, a counter substrate having a counter electrode disposed to face the active matrix substrate, and a counter electrode side of the counter substrate A liquid crystal layer formed on the active matrix substrate side,
Using an inspection device having a scanning line, a signal line, and a connection terminal for connecting to the counter electrode, respectively, disposing the inspection device in opposition to the active matrix substrate, and scanning the connection terminal. Connecting to each of the line, the signal line and the counter electrode; alternately applying an ON signal defining a period of one frame and an OFF signal following the ON signal to the scanning line of the active matrix substrate; A first pattern for changing the level of a voltage applied to a signal line before applying an ON signal to each of two preceding and succeeding frames, and a voltage level applied to a signal line before and after applying an ON signal to each of two preceding and succeeding frames The second pattern that changes
And a third pattern for changing the level of the voltage applied to the signal line after the application of the ON signal for each of the three frames.
At least two patterns are performed , and further, the voltage applied to the counter electrode is set to an ON voltage of the thin film transistor applied to a scanning line, and the voltage applied to the counter electrode is
The defect mode is selectively performed by setting an off voltage of the thin film transistor applied to a scanning line and changing the auxiliary capacitance between the on voltage and the off voltage in a state where the auxiliary capacitance is connected to the counter electrode. A defect repair method for an active matrix substrate, comprising the steps of: detecting a defect; and correcting the defect according to the detected defect mode. 7. A plurality of picture element electrodes and thin film transistors for driving each picture element electrode are arranged in a matrix on an insulating substrate, and are formed so as to be connected to the thin film transistors and to cross each other. Inspection method for an active matrix substrate in which each pixel electrode is connected to a scanning line and a signal line via the thin film transistor, and an auxiliary capacitor formed in connection with the pixel electrode is connected to a common line A counter substrate having a counter electrode disposed to face the active matrix substrate; and a liquid crystal layer formed on the counter electrode side of the counter substrate and disposed on the active matrix substrate side;
Using an inspection device having a scanning line, a signal line, and a connection terminal for connecting to the counter electrode, respectively, disposing the inspection device in opposition to the active matrix substrate, and scanning the connection terminal. Connecting to each of the line, the signal line and the counter electrode; and alternately applying an ON signal defining a period of one frame and an OFF signal following the ON signal to the scanning line of the active matrix substrate, A first pattern for changing the level of the voltage applied to the signal line before the application of the ON signal to each of the two frames to be applied, and the level of the voltage applied to the signal line before and after the application of the ON signal to each of the two adjacent frames. A second pattern for changing, and a third pattern for changing the level of the voltage applied to the signal line after the application of the ON signal to each of the two consecutive frames. Small of
By performing at least two patterns, multiple types of defect modes
A method for inspecting an active matrix substrate, the method comprising: 8. A plurality of pixel electrodes and thin film transistors for driving each of the pixel electrodes are arranged in a matrix on an insulating substrate, and are formed so as to be connected to the thin film transistors and to intersect each other. Inspection method for an active matrix substrate in which each pixel electrode is connected to a scanning line and a signal line via the thin film transistor, and an auxiliary capacitor formed in connection with the pixel electrode is connected to a common line A counter substrate having a counter electrode disposed to face the active matrix substrate; and a liquid crystal layer formed on the counter electrode side of the counter substrate and disposed on the active matrix substrate side;
Using an inspection device having a scanning line, a signal line, and a connection terminal for connecting to the counter electrode, respectively, disposing the inspection device in opposition to the active matrix substrate, and scanning the connection terminal. Connecting to each of the line, the signal line and the counter electrode; and alternately applying an ON signal defining a period of one frame and an OFF signal following the ON signal to the scanning line of the active matrix substrate, A first pattern for changing the level of the voltage applied to the signal line before the application of the ON signal to each of the two frames to be applied, and the level of the voltage applied to the signal line before and after the application of the ON signal to each of the two adjacent frames. A second pattern for changing, and a third pattern for changing the level of the voltage applied to the signal line after the application of the ON signal to each of the two consecutive frames. Small of
Performing at least two patterns , further setting the voltage applied to the counter electrode to an on-voltage of the thin film transistor applied to a scanning line, and changing the voltage applied to the counter electrode to the thin film transistor applied to a scanning line. And selectively detecting the defect mode by changing between the on-voltage and the off-voltage while the storage capacitor is connected to the counter electrode. Inspection method for active matrix substrates. 9. A plurality of pixel electrodes and thin film transistors for driving each of the pixel electrodes are arranged in a matrix on an insulating substrate, and are formed so as to be connected to the thin film transistors and to intersect each other. Inspection apparatus for an active matrix substrate in which each pixel electrode is connected to a scanning line and a signal line through the thin film transistor, and an auxiliary capacitor formed in connection with the pixel electrode is connected to a common line. A counter substrate having a counter electrode disposed in a state facing the active matrix substrate; a liquid crystal layer formed on the counter electrode side of the counter substrate and disposed on the active matrix substrate side; A connection terminal for connecting to each of the signal line and the counter electrode, and detection means for detecting a defect mode of the active matrix substrate via the connection terminal. And detecting means, 1 to the scanning line of the active matrix substrate
A first method of alternately providing an ON signal for defining a frame period and an OFF signal subsequent to the ON signal, and changing a level of a voltage applied to a signal line before applying an ON signal to each of two successive frames. A pattern, a second pattern for changing the level of the voltage applied to the signal line before and after the on-signal is applied to each of the two successive frames, and a second pattern for changing the level of the voltage applied to the signal line before and after each of the two successive frames By performing at least two patterns of the third pattern for changing the voltage level,
An inspection apparatus for an active matrix substrate configured to identify a kind of defect mode . 10. A plurality of picture element electrodes and thin film transistors for driving the picture element electrodes are arranged in a matrix on an insulating substrate, and are formed so as to be connected to the thin film transistors and to intersect each other. Inspection apparatus for an active matrix substrate in which each pixel electrode is connected to a scanning line and a signal line through the thin film transistor, and an auxiliary capacitor formed in connection with the pixel electrode is connected to a common line. A counter substrate having a counter electrode disposed in a state facing the active matrix substrate; a liquid crystal layer formed on the counter electrode side of the counter substrate and disposed on the active matrix substrate side; A connection terminal for connecting to each of the signal line and the counter electrode; and detection means for detecting a defect mode of the active matrix substrate via the connection terminal. For example, the detection means, to the scanning lines of the active matrix substrate 1
A first method of alternately providing an ON signal for defining a frame period and an OFF signal subsequent to the ON signal, and changing a level of a voltage applied to a signal line before applying an ON signal to each of two successive frames. A pattern, a second pattern for changing the level of the voltage applied to the signal line before and after the on-signal is applied to each of the two successive frames, and a second pattern for changing the voltage level applied to the signal line before and after the on-signal is applied to each of the two successive frames Performing at least two of the third pattern for changing the voltage level, further setting a voltage applied to the counter electrode to an on-voltage of the thin film transistor applied to a scanning line; To the off-voltage of the thin film transistor applied to the scanning line, and the on-state voltage with the storage capacitor connected to the counter electrode. With the off-voltage testing device of the active matrix substrate has a configuration to detect a defect mode performed selectively and be varied between. 11. A plurality of pixel electrodes and thin film transistors for driving each of the pixel electrodes are arranged in a matrix on an insulating substrate, and are formed so as to be connected to the thin film transistors and to intersect each other. Defect correction of an active matrix substrate in which each pixel electrode is connected to a scanning line and a signal line via the thin film transistor, and an auxiliary capacitor formed in connection with the pixel electrode is connected to a common line. A method, comprising: a counter substrate having a counter electrode disposed to face the active matrix substrate; a liquid crystal layer formed on the counter electrode side of the counter substrate and disposed on the active matrix substrate side;
Using an inspection device having a scanning line, a signal line, and a connection terminal for connecting to the counter electrode, respectively, disposing the inspection device in opposition to the active matrix substrate, and scanning the connection terminal. Connecting to each of the line, the signal line and the counter electrode; alternately applying an ON signal defining a period of one frame and an OFF signal following the ON signal to the scanning line of the active matrix substrate; A first pattern for changing the level of a voltage applied to a signal line before applying an ON signal to each of two preceding and succeeding frames, and a voltage level applied to a signal line before and after applying an ON signal to each of two preceding and succeeding frames The second pattern that changes
And a third pattern for changing the level of the voltage applied to the signal line after the application of the ON signal for each of the three frames.
By performing at least two patterns, multiple types of defect models
A method for repairing a defect in an active matrix substrate, comprising the steps of: identifying a memory card; and repairing a defect according to a detected defect mode. 12. A plurality of picture element electrodes and thin film transistors for driving each picture element electrode are arranged in a matrix on an insulating substrate, and are formed so as to be connected to the thin film transistors and to intersect each other. Defect correction of an active matrix substrate in which each pixel electrode is connected to a scanning line and a signal line via the thin film transistor, and an auxiliary capacitor formed in connection with the pixel electrode is connected to a common line. A method, comprising: a counter substrate having a counter electrode disposed to face the active matrix substrate; a liquid crystal layer formed on the counter electrode side of the counter substrate and disposed on the active matrix substrate side;
Using an inspection device having a scanning line, a signal line, and a connection terminal for connecting to the counter electrode, respectively, disposing the inspection device in opposition to the active matrix substrate, and scanning the connection terminal. Connecting to each of the line, the signal line and the counter electrode; alternately applying an ON signal defining a period of one frame and an OFF signal following the ON signal to the scanning line of the active matrix substrate; A first pattern for changing the level of a voltage applied to a signal line before applying an ON signal to each of two preceding and succeeding frames, and a voltage level applied to a signal line before and after applying an ON signal to each of two preceding and succeeding frames The second pattern that changes
And a third pattern for changing the level of the voltage applied to the signal line after the application of the ON signal for each of the three frames.
At least two patterns are performed , and further, the voltage applied to the counter electrode is set to an ON voltage of the thin film transistor applied to a scanning line, and the voltage applied to the counter electrode is
The defect mode is selectively performed by setting an off voltage of the thin film transistor applied to a scanning line and changing the auxiliary capacitance between the on voltage and the off voltage in a state where the auxiliary capacitance is connected to the counter electrode. A defect repair method for an active matrix substrate, comprising the steps of: detecting a defect; and correcting the defect according to the detected defect mode.