JP2915482B2 - Photoelectric conversion device - Google Patents

Description

The present invention relates to a photoelectric conversion device for reducing sensor noise.

2. Description of the Related Art An amplification type sensor is preferably used for a sensor used in a solid-state imaging device or the like in order to increase an output signal level.

The amplifying sensor is composed of MOS, SIT, FET, bipolar, etc. transistors, and amplifies the electric charge accumulated in the control electrode or amplifies the current and outputs it from the main electrode. . For example,
Japanese Patent No. 28456 discloses an example of an amplification type sensor. One of the problems of such an amplification type sensor is that the sensor noise is large.

The sensor noise generally includes fixed pattern noise (hereinafter, referred to as FPN) that appears fixedly, and random noise (noise whose amplitude changes at each reset) incorporated into the control electrode when the control electrode is reset.

Since FPN appears fixedly in the sensor noise, it can be completely removed by subtracting the dark output of the sensor from the optical signal output of the sensor. The dark output can be obtained by reading the storage time almost zero, that is, immediately after resetting the sensor.

On the other hand, in order to also remove the random noise incorporated in the control electrode, the sensor output (optical signal) after accumulation may be subtracted from the sensor output (sensor noise) immediately after the start of accumulation.

As a photoelectric conversion device capable of performing such subtraction processing, the present inventor has already proposed the following photoelectric conversion device in Japanese Patent Application No. 1-301819.

FIG. 5 is a circuit configuration diagram of the photoelectric conversion device disclosed in Japanese Patent Application No. 1-301819.

FIG. 6 is a schematic plan view of one pixel of the photoelectric conversion device.

In the description of the circuit configuration, portions common to the below-described embodiment of the photoelectric conversion device of the present invention are denoted by the same reference numerals except for portions necessary for the description, and description thereof will be omitted.

As shown in FIGS. 5 and 6, the pixels of the photoelectric conversion device disclosed in Japanese Patent Application No. 1-301819 have a photodiode D as a photoelectric conversion means for accumulating photo-excited charges, a capacitor C _OX , and an amplifying transistor. Tr, and a transfer element Ms for controlling transfer of electric charges generated in the photoelectric conversion unit of the photodiode D to a base, which is a control electrode of the amplifying transistor Tr.

The photoelectric conversion device having such a configuration is capable of independently reading out sensor noise regardless of the operation of the photodiode D by providing the transfer element Ms between the photodiode D and the amplifying transistor Tr. And FP
This makes it possible to remove not only N but also dark current components and random noise of the amplification transistor Tr.

Further, before transferring the charge accumulated in the photodiode D to the transistor for amplification Tr, reset means Mc for resetting the base of the transistor for amplification Tr is provided, and after the reset, the output of the transistor for amplification Tr is output to the first transistor. The output of the amplifying transistor Tr is read out as a second signal after reading as a signal and the transfer element Ms is turned on, and the charge of the photodiode D is transferred to the base of the amplifying transistor Tr. By removing the dark current component of the Tr before the transfer of the photocharge and setting the potential of the base of the amplifying transistor Tr lower than the accumulation potential of the photodiode D, the photocharge from the photodiode D to the amplifying transistor Tr is transferred. The transfer can be completely performed.

Furthermore, each amplification transistor adjacent in the sub-scanning direction
A reset transistor Mc is provided between the bases of the transistors Tr.
By resetting the base, the pixels arranged in the sub-scanning direction at the same time as the main-scanning direction can be reset, thereby reducing smear.

In this case, smear is too strong for light irradiation and so on.
When a signal corresponding to the stored electric charge is read, the potential of the control electrode of the unselected amplifying means rises and an output appears from the amplifying means.

The smear can be reduced because, before reading out the signal corresponding to the accumulated charge from the selected amplifying means, the unselected amplifying transistor Tr together with the control electrode of the selected amplifying transistor Tr is read. This is because the control electrode can also be reset, and no output appears from the unselected amplifying transistor Tr.

[Problems to be Solved by the Invention] However, when the photoelectric conversion device of Japanese Patent Application No. 1-301819 is applied to a gate separation type photoelectric conversion device in which an element isolation region has an insulated gate transistor configuration, the number of pixels is small. Since the reset time increases with the increase, an improvement has been desired.

The reason why the reset time becomes longer is that, as shown in FIGS. 5 and 6, since the reset transistor Mc is arranged in series, the series resistor (the ON resistance component of the reset transistor Mc, the base of the amplifying transistor Tr) is used. This is because a resistance component and the like and a capacitance (a base capacitance of the amplifying transistor Tr and a parasitic capacitance of the emitter and the like) increase and a time constant becomes longer.

Examples of applications in which the reset time is desired to be shortened include the following.

When an area sensor (in which a plurality of photoelectric conversion elements are arranged two-dimensionally) used in a solid-state imaging device or the like is operated in synchronization with television, reset is performed within one horizontal blanking (1HBLK), or A case where the horizontal scanning period is used is conceivable. In this case, in the case of a photoelectric conversion device in which the above-described element isolation region has an insulated gate transistor configuration, it is necessary to perform reset within one HBLK period.

However, if there is an application in which the pixel signals of two horizontal pixel columns are to be read out independently within one horizontal scanning period, Japanese Patent Application No. Hei.
With the photoelectric conversion device of 301819, it is difficult to cope with the long reset period.

When it is desired to obtain a luminance signal and a chrominance signal having a high vertical resolution with a color sensor, it is necessary to independently output pixel signals of two horizontal pixel rows. Therefore, a photoelectric conversion device that can be used for such a purpose has been desired.

[Means for Solving the Problems] The photoelectric conversion device of the present invention includes, as constituent elements, a photoelectric conversion unit that accumulates photo-excited charges, and a transfer element that controls transfer of the charges accumulated in the photoelectric conversion unit. A plurality of pixels in a vertical direction and a horizontal direction, wherein a plurality of photoelectric conversion means are commonly connected to a control electrode via respective transfer elements, and amplify the electric charge of the control electrode to output a vertical signal. An amplifying transistor that outputs a signal to a control line; a reset transistor provided on the control electrode; an output unit that simultaneously reads signals from a plurality of the amplifying transistors in a horizontal direction to a vertical output line; After resetting the electrodes, the output of the amplifying transistor is switched to the first
A first reading means for reading as a signal, and a transfer element for conducting the electric charge of the photoelectric conversion means to the control electrode, and after transferring the electric charge, reading an output of the amplifying transistor as a second signal. A second reading unit; and a subtraction processing circuit that performs a subtraction process between the first signal and the second signal.

In addition, the photoelectric conversion device of the present invention has a plurality of pixels in a vertical direction and a horizontal direction, each of which includes a photoelectric conversion unit that accumulates the photoexcited charge and a transfer element that transfers the charge accumulated in the photoelectric conversion unit. An amplifying transistor that is connected in common to two or more pixels and amplifies the charge transferred through the transfer element of each pixel of the two or more pixels and outputs the amplified charge to a vertical output line; And a common signal line for simultaneously outputting a signal from the amplifying transistor to the vertical output line.

[Operation] The present invention reduces the number of amplifying transistors by commonly connecting a plurality of photoelectric conversion means to one control electrode of the amplifying transistor via each transfer element, thereby reducing a resistance component of the amplifying transistor. , To reduce the capacitance component.

Further, according to the present invention, by providing a reset terminal of a reset transistor for each of a plurality of amplifying transistors, an additional increase in resistance and capacitance caused by series connection of the reset transistors is reduced.

Examples Hereinafter, examples of the present invention will be described in detail with reference to the drawings.

FIG. 1 is an equivalent circuit diagram of one embodiment of the photoelectric conversion device of the present invention.

Although the pixels of the photoelectric conversion device of this embodiment are arranged in a matrix of m rows × n columns, in FIG.
For simplicity, only the six pixels S _{1 to} S ₆ in the first column are shown.

As shown in FIG. 1, each of the pixels S _{1 to} S ₆ transfers a charge generated by a photodiode D, a capacitor C _OX , and a photoelectric conversion unit of the photodiode D, which are photoelectric conversion means for storing the photo-excited charge. It is composed of a transfer element Ms for controlling.

Two pixels in the vertical direction, pixel S ₁ and pixel S ₂ , pixel S ₃
And the pixel S ₄ , the pixel S ₅ and the pixel S ₆ are connected to the bipolar transistors Tr ₁ , Tr ₂ and Tr ₃ , respectively.

The bipolar transistors Tr ₁ and Tr _{2 in the} vertical direction are separated by two pMOS transistors Mc ₂ and Mc ₃ , and the two pMOS transistors M ₂ are separated between the bipolar transistors Tr ₂ and Tr _3.
c ₄ , separated by Mc ₅ . Bipolar transistor Tr ₁
PMOS transistor Mc ₁ is provided on one.

The emitter terminals of the bipolar transistors Tr ₁ , Tr ₂ , Tr ₃ are commonly connected to a vertical output line VL. Two pMOS transistor Mc _2, Mc _3, and Mc _4, Mc ₅ of drain are commonly connected to the drain of the pMOS transistor Mc _4, Mc ₅ is connected to the vertical output line VL. The drain of the pMOS transistor is connected to the vertical output line VL as required.

The gates of the pMOS transistors Mc ₁ , Mc ₂ , Mc ₃ , Mc ₄ , Mc ₅ are commonly connected to a reset gate line GL. A pulse φ _CL is applied to this gate line.

The vertical output line VL is connected to storage capacitors C _T1 and C _T2 via nMOS transistors M _T1 and M _T2 controlled by pulses φ _T1 and φ _T2 . Sensor noise and a signal are stored in the storage capacitors C _T1 and C _T2 , respectively, and the MOS is controlled by controlling the pulse φ _H1.
Through the transistors M _H1 and M _H2 , the sensor noise output (Sou
t), output to the horizontal output line as signal output (Nout),
The signal is subjected to subtraction processing by a subtraction processing circuit (not shown) and output to the horizontal common output line SL. Horizontal common output line SL is controlled by a pulse phi _HC. Reset by MOS transistor.

Vertical output line VL, MOS controlled by a pulse phi _VC
It is reset by transistor M _V, the storage capacitor C _T1, C
Transient refresh of the bipolar transistor Tr ₁ to Tr ₃ for removing and later of _T2 residual charge is possible.

Note that the vertical scanning circuit, nMOS transistor M _T1 , storage capacitance C
_T1 and the MOS transistor _MH1 constitute first reading means. Further, the vertical scanning circuit, the nMOS transistor M _T2 , the storage capacitor C _T2 , and the MOS transistor M _H2 constitute a second readout unit.

FIG. 2 is a schematic plan view of the photoelectric conversion device of the present invention.

In the same manner as in the first figure shows only six pixels S ₁ to S ₆ of the first column for simplicity.

In the figure, D ₁ to D ₆ is a photoelectric conversion means for accumulating photoexcited charge, a photodiode D of each pixel, signal photoelectrically converted by the photodiode D ₁ and D _2, the transfer device M (in the figure, the broken line area M _{S) S} with f a, is transferred to the base of the bipolar transistor Tr _1. Capacitance C _OX (broken line in the figure shown) is formed using a part of the control electrodes of the transfer element M _S (gate electrode). Note that the photoelectric conversion signal by the photo diode D ₃ and D ₄ in the same manner is transferred to the base of the bipolar transistor Tr _2, also photodiode D ₅
And photoelectrically converted signal D ₆ is a bipolar transistor
It is transferred to the base of the Tr _3.

Note that the base regions of the bipolar transistors Tr ₁ , Tr ₂ , and Tr ₃ have a vertical pMOS
By conducting all the transistors Mc ₁ to MC ₆ is reset. In the figure, B and E are bipolar transistors Tr, respectively.
₁ (the same applies to other pixels) indicates a base and an emitter, and RC indicates a contact portion of a reset terminal for setting a reset potential.

The reset terminal is for reducing the reset time constant, and is provided between the pMOS transistors. Usually, about 10 reset terminals may be provided for one vertical output line VL. Since the reset voltage (here, GND) is supplied by these 10 reset terminals, the series resistance in the vertical direction and the parasitic capacitance are approximately 1/10 times each,
The reset time, which required 1H period, can be reset as fast as about 1/100 times.

In addition, since one bipolar transistor is provided for two pixels, the number of bipolar transistors connected to the vertical output line is reduced by about half, so that the resistance component and the capacitance component are reduced (mainly the parasitic capacitance of the emitter). The load capacity due to the capacity is reduced), and the driving capacity of the bipolar transistor has a margin.

FIG. 3 is a timing chart for explaining the operation of the photoelectric conversion device.

When reading pixel signals of two horizontal pixel columns, the operation described below may be performed on two pixel columns. Note the following description describes the operation of only the pixel S _1, it is the same operation of the other pixels.

First, in the period T _1, a high level pulse phi _VC, when the pulse phi _CL and the low level, MOS transistor M _V, pM
OS transistors M _{C1 to} M _C6 are turned on, and the vertical output line VL
And the bases of the bipolar transistors Tr ₁ , Tr ₂ , Tr ₃ are reset.

In a period T _2, while maintaining the MOS transistor M _V in the ON state, becomes a high level pulse phi _R from the middle level and a pulse phi _T1 to the high level, nMOS transistors M _T1 is an ON state storage with capacitance C _T1 is reset, the base potential rises bipolar transistor Tr _1, the charge remaining in the base is discharged (referred to transient refresh).

In a period T _3, while a high level pulse phi _R, a pulse phi _T1 to the high level, when the pulse phi _VC low level, the offset voltage of the bipolar transistor Tr ₁ is read out, the storage capacitor as sensor noise C _T1
Is forwarded to

After that, the pulse φ _{VC is set} to the high level and the pulse φ _{T2 is set} to the high level, so that the MOS transistor M _V and the nMOS transistor M _T2
Then reset the storage capacitor C _T2 as ON state, in the period T _4, when the low level pulse phi _R from the middle level, the transfer element M _S is turned ON,
Converted signal photoelectrically from the photo diode D is transferred to the base of the bipolar transistor Tr _1.

Next, in a period T _5, the high level pulse phi _R from the low level, the pulse phi _T2 to a high level, a signal corresponding to the electric charge transferred to the base of the bipolar transistor Tr ₁ is read out to the vertical output line VL The signal is transferred to the storage capacitor _CT2 .

Thereafter, in the period T _6, the pulse φ if _H1 to the high level, the storage capacitor C _T1, stored sensor noise C _T2,
The signal is output, subjected to subtraction processing by a subtraction processing circuit (not shown), and output as a noise correction signal.

In the above-described photoelectric conversion device, one amplifying transistor (bipolar transistor) is provided for two vertical pixels. However, one amplifying transistor may be provided for three or more pixels.

In the above-described photoelectric conversion device, the area sensor has been described. In the case of a line sensor, if one amplifying transistor is provided for each of a plurality of pixels, the pattern design of the amplifying transistor causes a margin for design, and A line sensor suitable for the present invention can be provided.

FIG. 4 is a schematic configuration diagram of a solid-state imaging device to which the present invention is applied.

In the figure, a vertical scanning unit 202 and a horizontal scanning unit 203 perform television scanning on an image sensor 201 in which optical sensors are arranged in an area.

The signal output from the horizontal scanning unit 203 is output as a standard television signal through the processing circuit 204.

Drive pulses φ _{HS of} the vertical and horizontal scanning units 202 and 203,
φ _H1 , φ _H2 , φ _VS , φ _V1 , φ _V2, etc. are supplied by the driver 205. The driver 205 is limited by the controller 206.

[Effects of the Invention] As described in detail above, according to the photoelectric conversion device of the present invention, a plurality of photoelectric conversion units are commonly connected to one control electrode of the amplification transistor via each transfer element. Therefore, the number of amplifying transistors can be reduced, and the resistance component and the capacitance component of the amplifying transistor can be reduced (when the amplifying transistor is a bipolar transistor, in particular, the parasitic capacitance of the emitter can be reduced). , The degree of signal destruction can be reduced, resetting can be performed at high speed, and pixel signals of a plurality of horizontal pixel columns can be read out independently. In addition to this effect, by providing a reset terminal of a reset transistor for each of a plurality of amplifying transistors, it is possible to reduce an additional increase in resistance and capacitance caused by series connection of the reset transistors, and to perform reset at a higher speed. Becomes possible.

Since the number of contacts for the reset potential is very small, the yield is improved by that amount.

[Brief description of the drawings]

FIG. 1 is an equivalent circuit diagram of one embodiment of the photoelectric conversion device of the present invention. FIG. 2 is a schematic plan view of one embodiment of the photoelectric conversion device of the present invention. FIG. 3 is a timing chart for explaining the operation of the photoelectric conversion device. FIG. 4 is a schematic configuration diagram of a solid-state imaging device to which the present invention is applied. FIG. 5 is a circuit configuration diagram of a photoelectric conversion device disclosed in Japanese Patent Application No. 1-301819. FIG. 6 is a schematic plan view of one pixel of the photoelectric conversion device disclosed in Japanese Patent Application No. 1-301819. S _{1 to} S ₆ : Pixel, D: Photo diode, C _OX : Capacitance, Ms: Transfer element, Tr ₁ , Tr ₂ , Tr ₃ : Bipolar transistor, Mc ₁ , Mc
₂ , Mc ₃ , Mc ₄ , Mc ₅ : pMOS transistor, SL: horizontal common output line, VL: vertical output line, GL: gate line, M _T1 , M _T2 : MOS transistor, C _T1 , C _T2 : storage capacitance, M _H1 , M _H2 , M _V : MOS transistors.

Claims (4)

(57) [Claims] A plurality of pixels are provided in a vertical direction and a horizontal direction, each of which includes a photoelectric conversion unit for storing charges excited by light and a transfer element for controlling transfer of the charges stored in the photoelectric conversion unit. A photoelectric conversion device, wherein a plurality of photoelectric conversion means are commonly connected to a control electrode via respective transfer elements, and an amplification transistor for amplifying a charge of the control electrode and outputting the amplified charge to a vertical output line; A reset transistor provided in a plurality of transistors; an output unit for simultaneously reading out signals from a plurality of the amplifying transistors in a horizontal direction to a vertical output line; and an output of the amplifying transistor after resetting the control electrode by the reset transistor. A first readout unit for reading out the control signal as a first signal; and conducting the transfer element to transfer the charge of the photoelectric conversion unit to the control signal. A second reading means for reading out the output of the amplifying transistor as a second signal after transferring the charge, and a subtraction processing circuit for performing a subtraction process between the first signal and the second signal. A photoelectric conversion device comprising: 2. The photoelectric conversion device according to claim 1, wherein the pixels are arranged in a vertical direction and a horizontal direction, and the reset transistor is provided between control electrodes of amplification transistors adjacent in the vertical direction. A photoelectric conversion device characterized by the above-mentioned. 3. The photoelectric conversion device according to claim 2, wherein a reset terminal of said reset transistor is provided for each of a plurality of amplification transistors. 4. A pixel comprising a plurality of pixels in a vertical direction and a horizontal direction each comprising a photoelectric conversion means for storing charges excited by photoexcitation and a transfer element for transferring charges stored in said photoelectric conversion means, and two or more adjacent pixels. And an amplifying transistor that is connected in common to the amplifying device and amplifies the electric charge transferred via the transfer element of each pixel of the two or more pixels and outputs the amplified electric charge to a vertical output line. A common signal line for simultaneously outputting a signal to the vertical output line.