JP2542413B2 - Photoelectric conversion device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a photoelectric conversion device having a storage unit that stores a signal from a photoelectric conversion element, and in particular removes unnecessary components such as variations in dark signals and drive noise. The present invention relates to a photoelectric conversion device intended to do so.

[Prior art]

FIG. 10 is a schematic configuration diagram showing an example of a conventional photoelectric conversion device.

In the figure, the read signals from the photosensors S _{1 to} S _n are stored in the storage capacitors C _{1 to} C _n . And the scanning circuit 101
Transistors Q _{h1 to} Q _hn are sequentially
By being turned on, each read signal is sequentially output to the output line 102.
And output to the outside through the amplifier 103.

[Problems to be Solved by the Invention]

However, in such a conventional example, there is a problem that an unnecessary component such as a dark signal of the optical sensor or driving noise is included in the read signal and is output.

Here, drive noise is noise that occurs when the optical sensor is driven to read out a signal, and noise that is caused by manufacturing variations in the element shape, etc., and smear that depends on the light irradiation amount due to element separation, etc. Etc.

The dark signal is a dark current of the optical sensor, and its variation largely depends on the storage time and the temperature of the optical sensor.

Such unnecessary signals such as driving noise and dark signals pose a problem particularly when capturing low-illuminance images. Since the information signal level due to imaging is low during low-illuminance imaging, the SN
This is because the ratio decreases and the image quality deteriorates. Therefore, in order to improve the image quality, it is necessary to reduce the unnecessary signal.

However, as described above, the dark signal has a large dependency on the temperature and the accumulation time, and the driving noise has a small dependency. Therefore, if these unnecessary signals are to be removed, both signals are separated and the correction coefficient is set. It needs to be defined, which requires a large amount of memory. As a result, there are problems that the signal processing is complicated, the cost is increased, and the image pickup apparatus is upsized.

[Means for solving the problem]

In the photoelectric conversion device according to the present invention, the first reset means and the first and second storage means are connected to the output terminal of the photoelectric conversion element, and the signal transfer means and the first storage means are connected via the second storage means. When two reset means are connected and the first signal is read from the photoelectric conversion element, the second reset means sets the second storage means to a reference potential, and the second signal is read. Is characterized in that the second storage means is brought into a floating state by the second reset means.

[Work]

By accumulating the first and second signals from the photoelectric conversion element in the first and second accumulating means, the first and second signals can be superposed and read, and noise and the like from the photoelectric conversion output can be obtained. Unnecessary components can be removed.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a schematic circuit diagram showing the basic configuration of the first embodiment of the photoelectric conversion device according to the present invention.

In the drawing, the emitter electrode of which is the output terminal of the optical sensor S transistor is grounded through a transistor Q _VC, pulse phi _VC is input to the gate electrode of the transistor Q _VC. Further, the emitter electrode is installed via the capacitor C _V and is also connected to the horizontal output line HL via the capacitor C ₁ and the transistor Q _h . Transistor
A horizontal scanning pulse φ _h is input to the gate electrode of Q _h from a shift register (not shown).

The horizontal output line HL is grounded via the reset transistor Q _hr , and the pulse φ _hr is input to the gate electrode of the transistor Q _hr .

3 and 4 are timing charts showing a first example and a second example of specific operation of the photoelectric conversion device according to the present invention.

The first example shown in FIG. 3 is an operation example in which noise is read first and then signals are read, and the second example shown in FIG.
This is an example of the operation of reading the signal first and then reading the noise.

In FIG. 3, the photosensor S is refreshed in the period a, and the pulse φ _hr and all scanning pulses φ _h1 ~
_Set φ _hn and high level to clear capacitor C ₁ .

Then, while keeping the pulses φ _hr and φ _{h1 to} φ _hn unchanged, the capacitor C ₁ is grounded through the transistors Q _h and Q _hr , and the pulse φ _{VC is set} to the low level to make the emitter of the sensor S floating. As a result, the noise component of the photosensor S after being refreshed is transferred and accumulated in the capacitors C _V and C ₁ (period b). Then, the drive pulse φ _r falls to the reference potential, and the photosensor S starts the accumulation operation (period c). In this accumulation period c, the pulse φ _VC rises and the capacitor C _V is cleared.

Then, when the accumulation period c ends, the pulse φ _r rises, a sensor signal corresponding to the amount of incident light is read out, transferred to the capacitor C _V and accumulated (period d). At this time, since the pulses φ _h1 to φ _hn and φ _hr are low level, the transistors Q _h and Q _hr are OFF, and the capacitor C ₁ is in a floating state.

Then, the horizontal scanning pulses φ _{h1 to} φ _hn sequentially become high level, and the signal S from which the noise component has been removed from the sensor signal is output.
_Out is sequentially output to the outside from the horizontal output line HL (Japanese Patent Application No. 62-194525). At that time, the transistor Q _hr is turned ON, the residual charge of the horizontal output line HL is cleared by the pulse phi _hr each time the signal of one pixel is output (signal読乱a period f).

FIG. 2 is a schematic circuit diagram showing the basic configuration of the second embodiment of the present invention.

In this embodiment, between the capacitor C ₁ and the transistor Q _h in the first embodiment, the transfer transistor Q _t and the capacitor C _t is provided, prior to the horizontal scanning, the signal removing a noise component capacitor C _t Accumulate in.

A case where the present embodiment is operated by the second operation example shown in FIG. 4 will be described.

First, when the accumulation period c ends, the pulses φ _{h1 to} φ _hn ,
φ _hr and φ _t are set to the high level to clear the capacitor C _t , and at the same time, the other end of the capacitor C ₁ is grounded. Then, the pulse φ _r is raised, the sensor signal is read from the optical sensor S, and is stored in the capacitors C _V and C ₁ (signal transfer period d).

Then, set the pulse φ _VC to high level
_QVC is turned on, the emitter of the photosensor S is grounded, and a refresh operation is performed, and the capacitor _CV is cleared (period a).

Then, with the pulse φ _r kept at the high level, the pulse φ _VC is made to fall to turn off the transistor Q _VC ,
The noise component of the optical sensor S is transferred to the capacitor C _V (period b). Then, the optical sensor S starts the accumulation operation (period c).

On the other hand, the signal from which the noise component is removed is transferred to and accumulated in the capacitor C _t when the pulse φ _t rises and the transistor Q _t is turned on (period e). Then, it is sequentially transferred to the horizontal output line HL by the horizontal scanning pulses φ _{h1 to} φ _hn and φ _hr , and is sent to the outside (period f).

Thus, in the first and second embodiments, the optical sensor S
Since the emitter of is directly connected to the capacitors C ₁ and C _V , the load capacity of the photosensor S can be reduced and the reading efficiency can be improved.

In addition, since fluctuations in _Vb of the transistor due to variations in temperature and manufacturing are removed at the same time as noise removal, a high S / N signal can be obtained even when amplified by an amplifier in the subsequent stage.

The first embodiment shown in FIG. 1 can be operated in the second operation example shown in FIG. 4, and the second embodiment can be operated in the first operation example.

Further, the system of the optical sensor S is not limited to the gate separation type sensor (Japanese Patent Application No. 62-17150) shown in the figure, and other base accumulation type sensor, SIT type sensor or the like may be used.

FIG. 5 is a schematic circuit diagram of an example of the solid-state imaging device according to the present invention.

In the figure, the emitter electrodes of photoelectric conversion cells S _{1 to} S _n are connected to vertical lines VL _{1 to} VL _n , respectively, and transfer transistors Q ₁ and capacitors C ₁ and C ₂ are connected to each vertical line. _Grounded through transistor Q _VC .

The gate electrodes of the transistors Q _{VC on} each vertical line are commonly connected and a pulse φ _VC is applied. Further, the gate electrodes of the respective transistors Q ₁ are also commonly connected, and the pulse φ ₁ is applied.

The gate electrode of Torajisuta Q _h corresponding to each photoelectric conversion cells are connected together to the parallel output terminals of the scanning circuit 1, respectively pulse phi _h1 to [phi] _hn is applied. Further, each transistor Q _h is connected to the output line HL, the output line HL is is connected to the amplifier 2 is grounded through a transistor Q _hr. A reset pulse φ _hr is applied to the gate electrode of the transistor Q _hr .

The operation of this embodiment having such a configuration will be briefly described with reference to FIG.

FIG. 6 is a timing chart for explaining the operation of this embodiment.

As already explained, to clear the capacitor C ₁ and C ₂ corresponding to each photoelectric conversion cell in the period T _1, the period T ₂
Accumulating the read signal of each photoelectric conversion cell to the capacitor C ₁ and C ₂ in. Capacitor Subsequently, in the period T ₃
C ₂ is cleared and each photoelectric conversion cell is refreshed, and the remaining signal of each photoelectric conversion cell after refresh is stored in each capacitor C ₂ in the period T ₄ .

After accumulating the read signal and the residual signal of each photoelectric conversion cell in this manner, the pulse φ from the scanning circuit 1 is supplied in the period T ₅ .
_h1 is applied to the gate electrode of the transistor Q _h, as described above, accumulated from the read signal of the photoelectric stored in the capacitor C ₁ conversion cell S ₁ by the connection state of the capacitor C ₁ and C ₂ to the capacitor C ₂ A signal obtained by subtracting the remaining signal appears on the output line HL as an information signal, and is output as an output signal S _out via the amplifier 2.

When the signal of the photoelectric conversion cell S ₁ is outputted, a pulse phi _hr by the transistor Q _hr is turned on, charges remaining in the output line HL is eliminated.

In the same manner, the pulse phi _h2 to [phi] _hn, information signals of the photoelectric conversion cell S ₂ to S _n is obtained from an output line HL, it is sequentially outputted as the signal S _out through amplifier 2.

Although the voltage reading method has been described in this embodiment,
As shown by the broken line in FIG. 5, the load resistance RL is connected to the output line HL.
The same applies to the case of the current reading method to which

Further, although the one-dimensional line sensor is described in the present embodiment, it may be applied to a two-dimensional area sensor.

Further, since the noise component can be removed from the sensor signal by one vertical line VL, the structure can be simplified and the manufacturing yield can be improved.

FIG. 7 is a schematic circuit diagram of an example of the scanning circuit used in this embodiment. This scanning circuit is disclosed in Japanese Patent Application No. 62-273185.
No.

In this example, the driving pulses φ _c1 and φ _c2, which are separate from the driving pulses φ _h1 and φ _h2 , are input, and the transistors M3, M4, and M
ON / OFF control of 7, M8, M11, M12 ...

Also, in a circuit that feeds back an arbitrary scanning pulse to the unit bottleneck two stages before and turns on each transistor M5, M9, M13 ...
Q _1, Q ₂ ... respectively provided, it is ON / OFF controlled by the transistors Q _1, Q ₂ ... drive pulse phi _c1 or phi _c2.

 Next, the operation of this embodiment will be described.

FIG. 8 is a timing chart for explaining the operation of this example.

First, in the previous unit circuit, start pulse φ _hs
Is input to the transistor M1 by the pulse φ _h1 .
Is made conductive, and the voltage V ₁ rises. Since the voltage V ₁ is the gate potential of the transistor M2, the transistor M2 exhibits a conductance corresponding to the potential V ₁ .

Subsequently, the pulse phi _h1 is falling pulse phi _h2 rises, the voltage V ₂ rises through the transistor M2, which is fed back to the gate of the transistor M2 through the capacitance C _1, further raising the voltage V _1. This further increases the conductance of the transistor M2 and the pulse φ _h2 appears as the voltage V ₂ without a voltage drop.

In this state, the drive pulse φ _c2 having a narrow pulse width is input. Thus, the transistor M3 is turned ON to raise the voltage V ₃ of the first stage unit circuit.

Then, the driving pulse _φh1 having a wide pulse width rises.
This causes the voltage V ₄ to rise through the transistor M6 and further increase the voltage V ₃ through the capacitor C ₂ . Therefore, the pulse φ _h1 appears as the voltage V ₄ as it is, and this is output as the scanning pulse φ ₁₁ .

At the same time, the pulse φ _h1 causes the transistor M1 to
When turned on, the potential V ₁ drops to the reference potential.

With the voltage V ₄ at the high level, the driving pulse φ _c1 with a narrow pulse width rises, and the transistor M7 of the first-stage unit circuit
Is turned on and the voltage V ₅ of the second-stage unit circuit rises.

Then, when the drive pulse φ _h2 rises, the voltage V ₆ rises due to the transistor M10 and the capacitor C ₃ , and the scan pulse φ ₂₁ is output. At this point, the transistor Q _{1 of the} feedback wiring is OFF, so the transistor M 5 remains OFF, and therefore the voltage V ₃ of the first stage is also at high level and the scan pulse φ ₁₁ is also maintained at high level. There is.

Subsequently, when the drive pulse φ _h1 falls, the voltage V ₄ (scanning pulse φ ₁₁ ) falls and the voltage V ₃ also drops.

Then, when the drive pulse φ _c2 rises, the transistor
At the same time that M11 is turned on and the voltage V ₇ is increased, the transistors M8, Q ₁ and M3 are turned on.

By turning on the transistor M8, the voltage V ₄ becomes the reference potential.
Reset to V _ns .

Further, when the transistor Q ₁ is turned on, the scan pulse φ ₂₁ turns on the transistor M 5 and the voltage V ₃ becomes the ground potential. Further, when the transistor M3 is turned on, the voltage V ₂ is also reset to the ground potential.

In this way, as shown in FIG.
Scan pulses φ ₁₁ , φ ₂₁ , φ at the timing of _h1 and φ _h2
12 ... are output sequentially while overlapping. That is, it is possible to obtain a scan pulse output having a wide pulse width with a duty ratio of 50% or more.

FIG. 9 (A) is a timing chart for explaining the collective reset operation in this example, and FIG. 9 (B) is a timing chart for explaining the collective high level setting operation.

As shown in (A) of the figure, the collective reset is performed by the reference voltage.
Drive pulses φ _c1 and φ with V _ns at low level
_This is done by making _c2 high level at the same time. In the case of period T ₁ , it is a batch reset during scan pulse output,
In the case of T ₂ , it is a batch reset at the start of scanning.

Such a collective reset function is useful for the enlargement reading operation in the image pickup apparatus described later.

Further, the collective high level setting is performed by setting the drive pulses φ _c1 and φ _c2 to the high level while the reference voltage V _ns is set to the high level as shown in FIG.
In the period T ₄ , since φ _c2 becomes high level, the transistors M8, M16, ... Are turned on, and the scan pulses φ ₁₁ , φ ₁₂ ,.
_1n is set to high level. In the period T ₅ , the scan pulses φ ₂₁ , φ ₂₂ , ... φ _2n are set to the high level.

The period T ₃ shows the case of the above-mentioned collective reset.

FIG. 11 is a schematic configuration diagram of an example of an imaging system using a two-dimensional imaging device.

In the figure, the image pickup device 301 is the same as the device shown in FIG.
Corresponds to the dimensionality. Output signal S of image sensor 301
_Out is subjected to processing such as gain adjustment by the signal processing circuit 302 and output as a standard television signal such as an NTSC signal.

Further, each pulse for driving the image pickup device 301 is supplied by the driver 303, and the driver 303 controls the control unit 30.
Operates under the control of 4. The control unit 304 is an image sensor.
Based on the output of 301, the gain of the signal processing circuit 302 and the like are adjusted, and the exposure control unit 305 is controlled to adjust the amount of light incident on the image sensor 301.

〔The invention's effect〕

As described in detail above, the photoelectric conversion device according to the present invention accumulates the first and second signals from the photoelectric conversion element in the first and second accumulating means to obtain the first and second signals. Can be superimposed and read, and unnecessary components such as noise can be removed from the photoelectric conversion output.

[Brief description of drawings]

FIG. 1 is a schematic circuit diagram showing a basic configuration of a first embodiment of a photoelectric conversion device according to the present invention, and FIG. 2 is a schematic circuit diagram showing a basic configuration of a second embodiment of the present invention. 4 and 5 are timing charts showing first and second examples of specific operation of the photoelectric conversion device according to the present invention, and FIG. 5 is a schematic circuit diagram of one embodiment of the solid-state image pickup device according to the present invention. FIG. 6 is a timing chart for explaining the operation of this embodiment, FIG. 7 is a schematic circuit diagram of an example of a scanning circuit used in this embodiment, and FIG. 8 is a description of the operation of this embodiment. 9A is a timing chart for explaining the collective reset operation in this example, and FIG. 9B is a timing chart for explaining the collective high-level setting operation. Figure 10 shows an example of a conventional photoelectric conversion device. FIG. 11 is a schematic configuration diagram of an example of an imaging system using a two-dimensional imaging device. S ... Optical sensor, C _V and C ₁ ... Storage capacitor

Claims (2)

(57) [Claims] 1. A first reset means and first and second accumulating means are connected to an output terminal of a photoelectric conversion element, and a signal transfer means and a second resetting means are further connected through the second accumulating means. Means is connected, when the first signal is read from the photoelectric conversion element, the second storage means is set to the reference potential by the second reset means, and when the second signal is read, the second signal is read by the first reset signal. A photoelectric conversion device, characterized in that the second storage means is brought into a floating state by a second reset means. 2. The signal transfer means has a third accumulating means, and accumulates a signal obtained by superimposing the first and second signals accumulated in the first and second accumulating means. The photoelectric conversion device according to claim 1.