JP2915198B2 - Capacitive load drive circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving circuit for applying a high-voltage pulse voltage to a capacitive load, and more particularly, to a driving circuit which is stored in a capacitive load by utilizing resonance of an LC circuit utilizing inductance. The present invention relates to a capacitive load driving circuit that realizes low power consumption and a high recovery rate in a power recovery circuit that recovers accumulated electric charges.

[0002]

2. Description of the Related Art Conventionally, in a driving circuit for applying a high-voltage pulse to a capacitive load, an inductance L and a load capacitance Cp are applied.
A power recovery circuit utilizing resonance with the Weber et al., Weber et al., SIDD International Symposium Digest Technical Papers, pp. 92-95, 1987 (LF Weber et. Al. SI.
D Int. Symp. Digest. Tech. Papers, pp. 92-9.
5, 1987) and Kogami, et al., "Recovery of Reactive Power from a Townsend-issued Gas Discharge Television", Technical Report of the Institute of Television Engineers of Japan, Vol. 13, No. 58, pp. 7-12, (198).
9).

FIG. 2 shows a circuit configuration diagram of the power recovery circuit described therein. In FIG. 2, the external capacitance Cs (Cs≫C
The charge is stored in p), and the voltage is V / 2.
Here, V is the voltage of the pulse applied to the load. The switch circuits Q ₁ , Q ₂ , Q ₃ , Q ₄ , diodes D ₁ , D ₂ and inductance L are connected to the load capacitance Cp as shown in the figure.

FIG. 3 is a circuit diagram showing each switch circuit Q ₁ , Q ₂ , Q ₃ ,
₅ shows a time chart of the ON (ON) and OFF (OFF) states of Q4 and the output waveform (voltage of load Cp). The operation of this power recovery circuit will be described with reference to FIGS.

At the rise of the output voltage waveform shown in FIG. 3 (period I), the switch circuit Q ₁ shown in FIG. 2 is turned on, and Q ₂ , Q ₃ and Q ₄ are turned off. At this time, the charge stored in the external capacitance Cs (voltage V / 2) is supplied to Cp through Q ₁ , D ₁ , and L. The output voltage rises to V from the resonance between L and Cp. The rise time tr of this output voltage is given by Equation 1.

[0006]

(Equation 1)

Here, C ₃ and C ₄ are switch circuits Q ₃ and Q ₄
2 shows the output capacitance of the FET.

Next, after the output voltage rises to V, Q ₃
Is turned on to hold the output voltage at V (period II). In this case, Q ₁ is may be OFF even ON.

Next, when the output voltage falls (period III
In), and Q ₂ is ON, the OFF to _{Q 1, Q 3, Q 4} . At this time, the charges accumulated in Cp flow into the external capacitance Cs again through L, D ₂ and Q ₂ . The output voltage at that time drops from the resonance characteristic of L-Cp to 0V.

[0010] By turning ON the Q ₄ in the period IV then holds the output voltage to 0V.

As described above, when the voltage of the load Cp rises, the electric charge is supplied from the external capacitor Cs, and when the voltage falls, the electric charge of the load Cp is returned to the external capacitance again. The circuit is realized.

The power consumption of this power recovery circuit is given by E in Equation 2 for one pulse.

[0013]

(Equation 2)

Here, Ec and Er indicate the power consumption due to the output capacitance and on-resistance of the switch circuit and the diode, and C ₁ , C ₂ , C ₃ , and C ₄ indicate the switch circuits Q ₁ , Q ₂ , and Q ₄ , respectively. ₃ and Q ₄ indicate the output capacitances of the FETs, R ₁ and R ₂
It indicates the on resistance of the FET Q ₁ and Q _2. Also, Cd ₁ and Cd ₂ and Rd ₁ and Rd ₂ indicate the output capacitance and on-resistance of the diodes D ₁ and D ₂ , _RL indicates the resistance loss of the inductance L, and tr indicates the rise and fall times of the output waveform. Show.

[0015]

In the power recovery circuit described above, the power consumption of the circuit is reduced, that is, the power recovery rate η
The improvement in represents the performance of the circuit. Here, the power recovery rate η is expressed by Equation 3.

[0016]

(Equation 3)

In the above equation (2), the output capacitance Cd of the diode
₁ and Cd ₂ and the on-resistances Rd ₁ and Rd ₂
The ₁ output capacitance C ₁ of the Q _2, smaller than the C ₂ and the on-resistance R _1, R ₂ are common. Therefore, E = Ec + Er in Equation 2
Can be reduced by reducing C ₁ , C ₂ , R ₁ , and R ₂ , but generally, C = B
/ R (C is the output capacitance, R is the on-resistance, and B is a constant).

FIG. 4 is a diagram showing an n-type F with a breakdown voltage of 450 V manufactured by a certain company H.
Although the output capacity of ET and the value of 1 / R are plotted, it can be seen from this figure that there is a relationship of C = B / R.

Next, the minimum power consumption of the power recovery circuit is obtained by using this relational expression.

From the relational expressions of the output capacitances C ₁ = B ₁ / R ₁ and C ₂ = B ₂ / R ₂ of the FETs of the switch circuits Q ₁ and Q ₂ ,
Can be rewritten into the following equation (4).

[0021]

(Equation 4)

In this equation, when C ₁ and C ₂ are given by Equation 5, the power consumption E of the circuit is the minimum value Emin given by Equation 6, and this value is the minimum value of the theoretical power consumption of the power recovery circuit. give.

[0023]

(Equation 5)

[0024]

(Equation 6)

For example, as a numerical calculation example, Cp = 300
0 pF, tr = 0.5 μs, R _L = 1Ω, V = 200 V,
B ₁ = B ₂ = 2 × 10 to ¹⁰ ΩF, and Cd ₁ , C
If the terms d ₂ , Rd ₁ , and Rd ₂ are ignored, the power recovery rate η is about 96%.

However, further reduction in power consumption is always required for a power recovery circuit. In particular, when this circuit is applied to a matrix display device such as a gas discharge television, the number of electrodes increases and the number of electrodes increases. This is an important issue because of its large capacity.

[0027]

The object of the present invention is to divide the voltage V applied to the capacitive load into n stages (Vgn <V ₁
<V ₂ <... <Vn = V) The step-up and step-down of each voltage is performed by resonance between the n independent inductances L ₁ , L ₂ ,. , That is, the power recovery rate is improved.

That is, in a drive circuit for applying a pulse voltage to a capacitive load, an external power supply (or a constant voltage source based on charges stored in the external capacitance) and an inductance L are connected by a switch circuit, and the other end of the inductance is connected to the other end of the inductance. connect the capacitive load, the capacitive load driving circuit for boosting or reducing the load by utilizing the resonance of L-C, by the resonance of the first inductor L ₁ and the load Cp, the voltage of the load V
gn (load ground voltage) to (V ₁ > Vgn) (or step down from V ₁ to Vgn), and V ₁ to V ₂ (V ₁ <V ₂ ) by at least the second inductance L ₂ and the load Cp. ) to those that provide power recovery circuit is means for stepping down) from the booster (or V ₂ to V _1.

In this case, the number of inductances is L ₁ and L ₂
Not only two, but any number of two or more (n), L
_1, L _2, may be a ... Ln. In this case, if the values of the inductances L ₁ , L ₂ ,.
The voltage intervals of n, V ₁ , V ₂ , and Vn are substantially equal, and the power consumption of the circuit is minimized.

[0030]

According to the present invention, there is provided a driving method in which a voltage applied to a capacitive load is divided and sequentially stepped up or down by respective inductances. In this case, the number of parts of an electronic element including the inductance and its switch circuit is provided. However, there is a disadvantage that the number increases. However, according to the above-mentioned reference in the prior art, Kogami, et al., "Reactive power recovery of a Townsend-issued gas discharge television", a switch circuit is interposed between an electrode of a display element and a power recovery circuit. The number of power recovery circuits can be greatly reduced, and even if the size of one circuit is slightly increased, the cost and capacity are not significantly increased.

[0031]

FIG. 1, FIG. 5, FIG. 6, FIG.
This will be described with reference to FIG. FIG. 1 shows the capacitive load Cp of the present invention.
To the power recovery circuit for applying a pulse voltage V, the inductance L ₁ and the inductance by L _2, shows a circuit diagram when a pulse voltage is applied by dividing the boosted load in two stages, Figure 5 is the switch elements, Q ₁₁ , Q ₁₂ , Q ₂₁ , Q ₂₂ ,
The ON and OFF states of Q ₃ and Q ₄ are shown. Where L
₁ = When L _2, each voltage of the external capacitance Cs ₁ and Cs ₂ is V
/ 4 and 3V / 4 automatically stabilized. Next, the circuit operation of FIG. 1 will be described together with the ON / OFF state of each switch element of FIG.

[0032] First, ON the Q ₁₁ for a period of I in FIG.
At this time, since the voltage of the external capacitor Cs ₁ in FIG. 1 is V / 4, the charge of Cs ₁ flows to Cp through Q ₁₁ , D ₁₁ and L _{1 due} to the resonance of L ₁ and Cp, and the output voltage (The voltage of the load Cp) rises to V / 2. Next, when Q ₂₁ is turned on during the period II, the voltage of Cs ₂ is 3 V / 4, so the resonance of L ₂ and Cp causes the external capacitor Cs to turn on.
Flows into Cp ₂ charges through _{Q 21, D 21, L 2} , the output voltage rises from V / 2 to V. Next, in period III, Q
Turn on ₃ to hold the output voltage at V.

Next, as for the step-down, Q ₃ is turned on during the period IV.
And FF, turning ON the Q _22. At that time, due to the resonance between L ₂ and Cp, the charge accumulated in the load Cp of the voltage V is changed to L ₂ ,
The current flows to Cs ₂ through D ₂₂ and Q _22, and the voltage drops to V / 2. Then, ON the Q ₁₂ for a period of V Then, the electric charge from the resonance of L ₁ and Cp, it was collected in the load Cp voltage V / 2 is L
₁ , D ₁₂ and Q ₁₂ flow to Cs ₁ , and the output voltage drops to zero. Then, ON the Q ₄ in the period VI Then, the output voltage is held to zero.

In this way, the power recovery circuit is operated by dividing the step-up and step-down by the voltage V / 2 via the two inductances L ₁ and L ₂ .

Now, the power consumption of the power recovery circuit shown in FIG. 1 is calculated and compared with Equations 2 and 6 of the conventional circuit to show that the circuit consumes less power than the conventional circuit.

When calculating the power consumption E 'of the power recovery circuit of the present invention shown in FIG. 1, the total power consumption of the power recovery circuit is L
Circuit elements associated with the _{1 (Q 11, D 11,} Q 12, D 12, L 1)
Circuit elements (Q ₂₁ associated with L _{2 and, D 21, Q 22, D} 22, L
₂ ) Sum of power consumption. Therefore, Equation 7 is obtained.

[0037]

(Equation 7)

E ₁ c, E ₁ r, E ₂ c, and E ₂ r are given by Equation ₈ when the voltages of Cs ₁ and Cs ₂ are V / 4 and 3 V / 4.

[0039]

(Equation 8)

However, in order to obtain the same pulse rise time as in the conventional circuit, tr is replaced by tr / 2.

Here, the peak current flowing through the inductance L of the conventional circuit is given by Equation 9, but the peak current I _L ′ flowing through each inductance of the circuit of the present invention is the same as Equation 10. Therefore, the constant of each element can be set to the same value as the conventional circuit (Equation 11).

[0042]

(Equation 9)

[0043]

(Equation 10)

[0044]

[Equation 11]

Here, the values of the inductances L ₁ and L ₂ are _１ ／ of the value L of the conventional inductance because the rise time tr is halved. At this time, assuming that the Q value of the inductance is the same, the values of R _L1 and R _L2 can be replaced by the values of Expression 12.

[0046]

(Equation 12)

By substituting these into Equation 8, the power consumption of the power recovery circuit of the present invention is given by Equation 13.

[0048]

(Equation 13)

Comparing Equations 2 and 13, the power consumption Ec 'based on the output capacitance of the FET and the diode is half of the power consumption Ec of the conventional circuit, and the power consumption based on the resistance loss of the inductance is 1/4. It can be seen that the number has decreased.

Here, when the minimum value of E 'is obtained from the relationship of C ₁ = B ₁ / R ₁ and C ₂ = B ₂ / R ₂ ,

[0051]

[Equation 14]

E ′ becomes the minimum value, and becomes Eq.

[0053]

(Equation 15)

Compared to Equation 6, the power consumption based on the output capacitance and on-resistance of the FET is 1 / √2 times, the power consumption based on the resistance loss of the inductance is 1/4 times, and the power consumption based on the output capacitance of the diode. Is １ ／ times as large.

Next, referring to FIG. 6 and FIG.
Equally divided, each step-up and step-down is divided into n stages, and L ₁ −
Cp, L ₂ -Cp,... Ln-Cp will be described.

FIG. 6 is a circuit diagram of a power recovery circuit using an n-stage resonance circuit, and FIG. 7 is an output waveform and O of each switch element.
N, OFF state. The operation is the same as in FIG.
At the time of boosting, Q ₁₁ , Q ₂₁ ,..., Qn ₁ are sequentially turned on. When the output voltage reaches V, Q ₃ is turned on and held.

[0057] at the time of step-down sequentially O the Qn ₂ ... Q _22, Q ₁₂
Continue to N, when the output voltage is zero, to hold to 0 to ON the Q _4.

Now, assuming that L ₁ = L ₂ =... Ln, the voltages of the external capacitors Cs ₁ , Cs ₂ ,... Csn automatically become V / 2n, 3V / 2n, (2n-1) /
2n. In the circuit diagram 6 of the present invention, in order to make the rise tr of the output voltage equal to the rise time of the conventional circuit,
The value of L ₁ , L ₂ ,... Ln is 1 / n ² of the value of L in the conventional circuit. The resistance loss of the inductance at that time is R _L / n ² when the inductance Q is the same.

As in FIG. 1, the circuit of the present invention, the power consumption E ″ of FIG.

[0060]

(Equation 16)

The power consumption based on the capacitance is 1 / n, and the power consumption based on the resistance loss of the inductance is 1 / n ² . Using the relational expressions of C ₁ = B ₁ / R ₁ and C ₂ = B ₂ / R ₂ , the minimum value of E ″ is obtained when C ₁ and C ₂ are given by the following equation (17).
E ″ min is given by Expression 18.

[0062]

[Equation 17]

[0063]

(Equation 18)

Is given by Comparing Equations (18) and (6), the power consumption based on the output capacity and the on-resistance of the FET is 1 / √n, the power consumption based on the resistance loss of the inductance is 1 / n ² , and the consumption based on the output capacity of the diode. The power becomes 1 / n. The power consumption based on the on-resistance of the diode remains unchanged, but this value is extremely small compared to the on-resistance of the FETs of the switch circuits Q ₁ and Q ₂ .

In the above description of FIGS. 1 and 6 of the present invention, the values of the inductances L ₁ , L ₂ ,... Ln are assumed to be substantially equal. This is because the power consumption of the circuit is minimized only in that case. However, even if the values of the respective inductances are different, it is clear that a power recovery circuit with lower power consumption than the conventional circuit can be realized and is included in the present invention.

[0066]

According to the present invention, a drive circuit for applying a pulse voltage to a capacitive load is a power recovery circuit in which an external power supply and an inductance are connected via a switch circuit, and a load capacitance is connected to the other end. , The capacitive load step-up and step-down
The power recovery circuit can be greatly reduced in power by dividing it into stages and performing step-up and step-down in each stage by resonance between n inductances and a capacitive load. In particular, when the values of the n inductances are substantially equal and the output capacitance and the on-resistance of the FET of the switch element are optimally set, the power consumption based on the output capacitance and the on-resistance of the FET is reduced to 1 / √n. And the power consumption based on the output capacitance of the diode can be reduced to 1 / n ² . Thus, for example, when the power recovery circuit is applied to a matrix display element, the power consumption of the conventional circuit can be reduced from 1 / √2 to a half or a fraction thereof.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram of the present invention when there are two inductances.

FIG. 2 is a conventional circuit configuration diagram.

FIG. 3 shows an output waveform of a conventional circuit and ON and O of each switch.
The figure which shows an FF state.

FIG. 4 is a diagram showing a relationship between an output capacitance and an on-resistance of an FET.

FIG. 5 is a circuit diagram of the present invention.
The figure which shows an N, OFF state.

FIG. 6 is a circuit configuration diagram when the number of inductances is n according to the present invention.

FIG. 7 is a circuit diagram of the present invention.
The figure which shows an N, OFF state.

[Explanation of symbols]

_{Q 1, Q 2, Q 11} , Q 12, ... Qn 2 ... switch circuit, L _1,
L ₂ , Ln inductance, Cp load capacitance, C
s, Cs ₁ ,..., Csn.

──────────────────────────────────────────────────続 き Continuing from the front page (72) Tadashi Naruseki, Inventor 1-280, Higashi Koikekubo, Kokubunji-shi, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd. (72) Inventor Kuni Kitagawa 3681 Hayano, Mobara-shi, Chiba Pref. Hitachi Device Engineering Stock In-company (56) References JP-A-54-11643 (JP, A) JP-A-2-81090 (JP, A) JP-A-4-21890 (JP, A) JP-A-49-28257 (JP, A) JP-A-50-73151 (JP, A) JP-A-63-31816 (JP, A) JP-A-63-144621 (JP, A) JP-A-5-41651 (JP, A) 20785 (JP, A) (58) Field surveyed (Int. Cl. ⁶ , DB name) H03K 17/687

Claims (3)

(57) [Claims] (1)Circuit and capacitive load capacitance and inductance
PartAnd the resonance based on the inductance of the
In a capacitive load driving circuit for applying a voltage to a load,Provided in parallel with the capacitive load, one end
First and second inductors connected to the capacitive load side
And Installed between the first inductance section and the first power supply section.
A first switch unit, Installed between the second inductance section and the second power supply section.
However, the road is turned on later than the first switch.
A second switch unit, With When the first switch section is conductive, the first input
Based on the voltage of the capacitive load,
Boosting the reference voltage to a first voltage,
Use the above second inductance part when is in a conductive state
The voltage of the capacitive load is changed from the first voltage to the second voltage by resonance.
Configured to boost the voltage to Characterized by the capacity
Load drive circuit. 2. The capacitive load drive circuit according to claim 1, wherein said first inductance section and said second inductance section have substantially equal inductance values . (3)Circuit and capacitive load capacitance and inductance
Using the resonance based on the inductance of the
In a capacitive load drive circuit that applies a voltage to a load, Provided in parallel with the above capacitive load and one end is
N inductances connected to the capacitive load side
Department and N power supplies provided for each of the n inductance units
Or with a capacitor, Each of the n inductance units and the n power sources
In response to this, provided between the two, and by conduction, the n
With resonance based on each of the conductance parts and the above capacitance
A switch unit for adding generated voltages to each other, With When the added voltage V is applied to the capacitive load
In this case, the n power supplies or capacitors are m
The second voltage is approximately (2m-1) V / (2n)
Characterized by Capacitive load drive circuit.