JP2912351B1 - Charge pump device - Google Patents

Abstract

An object of the present invention is to provide a charge pump device capable of selecting an optimum operation frequency according to a threshold value of a transistor and preventing an excessive operation current from flowing. SOLUTION: Trimming data T1 to T4 include:
The threshold value of the transistor of the semiconductor integrated circuit in which the charge pump device 100 is incorporated is reflected, and the reference voltage generation circuit 200 compensates for the fluctuation of the predetermined circuit characteristic caused by the threshold value of the transistor based on the trimming data. I do. A crystal oscillation circuit 1, a binary counter 2, and a frequency adjustment circuit 3 as signal generation means generate an oscillation signal F2 having a frequency corresponding to a threshold value of a transistor reflected on the trimming data based on the trimming data T1 to T4. . The charge pump circuit 4 serving as a charge transfer means transfers a charge from a predetermined power supply to a predetermined output node driven by the oscillation signal F2 to obtain a boosted or reduced output V0.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a charge pump device built in a semiconductor integrated circuit.

[0002]

2. Description of the Related Art Conventionally, semiconductor integrated circuits such as timepiece LSIs include an oscillation circuit (OSC), a reference voltage generation circuit, a charge pump circuit, a logic circuit (LOGIC), and an RO circuit.
Various circuit blocks such as M and RAM are built in.

FIG. 5 shows a conventional charge pump device 100A and a reference voltage generation circuit 2 incorporated in a timepiece LSI.
00 is shown. In the figure, a charge pump device 100A includes a crystal oscillation circuit 1 and a binary counter 2
And a charge pump circuit 4. In the charge pump device 100A, the oscillation signal (for example, 32 KHz) of the crystal oscillation circuit 1 is divided by the binary counter 2 and converted into a clock signal of a predetermined frequency. The charge pump circuit 4 operates by being driven by a clock signal from the binary counter 2, and outputs a boosted or reduced output V0.
Get.

[0004] The reference signal generation circuit 200 is configured independently of the charge pump device 100A. The reference voltage generation circuit 200 is configured to generate an output V1 using a voltage determined by a threshold value VT of a transistor (MOSFET) as a reference voltage, and thus this reference voltage has a dependency on the threshold value VT of the transistor. Further, the threshold value VT of this transistor has manufacturing variations, and the output V1 varies according to the threshold value VT of the transistor. For this reason, the reference voltage generation circuit 200 uses the threshold V
A trimming function is provided for compensating a variation in the output V1 caused by T.

That is, the reference voltage generating circuit 200
Is a so-called V that generates a reference voltage corresponding to the sum of thresholds of a Pch transistor and an Nch transistor (not shown).
The T sum type reference voltage circuit 6 and the output V generated by the VT sum type reference voltage circuit 6 based on the trimming data T1 to T4.
1 for trimming. The trimming data T1 to T4 reflect the magnitude of the threshold value VT of the transistor constituting the timepiece LSI, and the trimming data is programmed in advance in, for example, a fuse circuit.

[0006]

By the way, in the field of the above-mentioned digital timepiece, L is used to extend the battery life of the timepiece.
It is essential to reduce current consumption in SI. LSI for clock
Then, the current consumption in the charge pump circuit is the largest,
It occupies about 30% of the current consumption of the entire LSI. Also, LS
The current consumption of I tends to increase as the threshold value VT of the transistor constituting the LSI is lower, and is significantly reflected in the current consumption of the charge pump circuit. Therefore, it is important to reduce the current consumption of the charge pump circuit. Is an important issue.

However, according to the above-mentioned prior art, the charge pump circuit 4 operates at a constant frequency irrespective of the threshold value VT of the transistor, and consumes excessive current when the threshold value VT of the transistor is low. There are inconveniences.

The present invention has been made in view of the above circumstances, and provides a charge pump device that can select an optimum operation frequency in accordance with a threshold value of a transistor and that does not cause an excessive operation current to flow. With the goal.

[0009]

In order to achieve the above object, the present invention has the following arrangement. That is, the present invention is incorporated in a semiconductor integrated circuit having trimming data reflecting a threshold value of a transistor and having a function of compensating for a variation in circuit characteristics due to the threshold value of the transistor based on the trimming data. A charge pump device, based on the trimming data, a signal generating means for generating an oscillation signal having a frequency corresponding to a magnitude of a threshold value of a transistor reflected in the trimming data; Charge transfer means for transferring charges from a power supply to a predetermined output node.

The signal generating means adjusts the frequency of the oscillating signal based on the trimming data to generate an oscillating signal having a predetermined frequency, and adjusts the frequency of the oscillating signal in accordance with the threshold value of the transistor. A frequency adjusting unit for obtaining an oscillation signal of a frequency.

Further, the frequency adjustment section includes a clock generation circuit that generates a plurality of clock signals having different frequencies based on an oscillation signal of a predetermined frequency from the oscillation signal generation section, and a decoder that decodes the trimming data. A frequency selection circuit that selects any one of the plurality of clock signals from the clock generation circuit based on the output signal of the decoder, and outputs the selected signal as an oscillation signal having a frequency corresponding to the threshold value of the transistor. It is characterized by having.

Further, the oscillation signal generation section includes an oscillation circuit for generating a reference oscillation signal of a reference frequency, and a binary counter for dividing the reference oscillation signal to obtain an oscillation signal of the predetermined frequency. It is characterized by the following. Furthermore, the oscillation circuit is characterized by comprising a crystal oscillation circuit.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. In each of the drawings, elements common to the elements shown in FIG. 5 described above are given the same reference numerals, and descriptions thereof will be omitted as appropriate.

FIG. 1 is a block diagram showing a configuration of a charge pump device 100 according to this embodiment incorporated in a timepiece LSI, and a reference voltage generation circuit 200. This LSI has trimming data T1 to T4 on which the threshold value VT of a transistor is reflected.
00 has a function of compensating for a variation in predetermined circuit characteristics caused by the threshold value VT of the transistor based on the trimming data, and has the same configuration as that shown in FIG.

In FIG. 1, a charge pump device 100
Is a reference oscillation signal F of a reference frequency (for example, 32 KHz).
0, and a reference oscillation signal F0
Divided by a predetermined frequency (for example, 32 KHz and 2 KHz)
A binary counter 2 that obtains the oscillation signal F1 of the above, a frequency adjustment circuit 3 that generates an oscillation signal f2 of a frequency corresponding to the magnitude of the threshold value VT of the transistor from the oscillation signal F1 based on the 4-bit trimming data T1 to T4, And a charge pump circuit 4 that is driven by the oscillation signal F2 from the frequency adjustment circuit 3 to obtain the output V0.

Crystal oscillation circuit 1 and binary counter 2
Constitutes an oscillation signal generation unit 101 for generating an oscillation signal F1 of a predetermined frequency, and the oscillation signal generation unit 101 and the frequency adjustment circuit 3 generate an oscillation signal F2 of a frequency corresponding to the threshold value VT of the transistor. A charge transfer circuit (not shown) which is driven by the oscillation signal F2 to transfer a charge from a predetermined power supply (not shown) to a predetermined output node to obtain an output V0. ).

The frequency adjustment circuit 3, as shown in FIG.
Clock signals f1 to f1 having different frequencies from the oscillation signal F1 from the binary counter 2 described above.
And a decoder 33 for decoding the trimming data T1 to T4.
And decode signals D0 to D from decoder 33
15. A frequency selection circuit 3 which selects one of the clock signals f1 to f15 based on No. 15 and outputs it as an oscillation signal F2 having a frequency corresponding to the threshold value of the transistor.
Consists of two.

Here, the description returns to FIG. The reference voltage generation circuit 200 has a threshold V of a transistor (MOSFET).
VT sum type reference voltage circuit 6 for generating an output V1 corresponding to T
And a trimming circuit 5 for adjusting the variation (variation) of the output V1 caused by the threshold value VT of the transistor.

As shown in FIG. 3, the VT sum type reference voltage circuit 6 includes a current source 61, a Pch transistor P63, an Nch
It comprises a reference signal generation section (no symbol) composed of a transistor N63, an operational amplifier 62 of a non-inverting amplifier circuit, and resistors R0 to R15 and R64 for feedback. Here, the drain of the transistor P63 is connected to the drain of the transistor N63, and the source of the transistor N63 is grounded to the ground GND. These transistors P
The gates of 63 and N63 are commonly connected to the drains of transistors P63 and N63.

The current source 61 is connected between the power supply VCC and the source of the transistor P63. The source of the transistor P63 is connected to the minus input node (-) of the operational amplifier 62. The feedback resistors R64 and R0 to R15 are connected in series between the ground GND and the output of the operational amplifier 62, and the plus input node (+) of the operational amplifier 62 is connected to the connection point between the resistors R64 and R0.

According to the VT sum type reference voltage circuit 61,
The operational amplifier 62 detects the threshold value VTP of the transistor P63 and +
The sum of the threshold values VTN of the transistors N63 (hereinafter, “VT”
(Abbreviated as "sum") as a reference voltage, and outputs an output V1. Therefore, this reference voltage input to the minus input node of operational amplifier 62 is applied to transistors P63 and N6.
3 fluctuates depending on each threshold value VT. For example, if the threshold value VT of each of the transistors P63 and N63 is high, the reference voltage is also proportionally high, and the output V1 of the operational amplifier 62 fluctuates.

In order to make the output V1 of the operational amplifier 62 constant, trimming is performed by adjusting the variation of the reference voltage caused by the transistor threshold based on the trimming data T1 to T4 reflecting the transistor threshold VT. A trimming circuit 5 is provided. The trimming circuit 5 includes a decoder 51 for decoding trimming data T1 to T4, and Nch transistors TN0 to TN15 which are turned on based on the decode outputs d0 to d15 of the decoder 51. Transistor T
One of the source and drain of N0 is connected to a connection point between the resistors R0 and R1, and the other is connected to the output of the operational amplifier 62. Similarly, the connection point of each resistor and the operational amplifier 62
The transistors TN2 to TN15 are respectively connected between the output section and the output section.

According to the trimming circuit 5, for example, if the trimming data T1 to T4 are all "L",
The decode output d15 of the decoder 51 is activated, and this turns on the transistor TN0 given to the gate to short-circuit the 15 resistors R1 to R15. As a result, the voltage gain of the operational amplifier 62 becomes the smallest, and the output V1 becomes the smallest. On the other hand, if all the trimming data T1 to T4 are “H”, the decode output d0 of the decoder 51 is activated, and the output V1 becomes the largest.

FIG. 4 shows trimming data T1 to T4.
Shows an example of the relationship between the number of trimming steps represented by and the output V1 of the VT sum type reference voltage circuit 61. In the figure, characteristic lines C1 and C2 correspond to a case where the VT sum is low and a case where the VT sum is high, respectively. The output voltage represented by the characteristic line C1 is lower than the characteristic line C2 because the VT sum is lower. Therefore, in the example shown in FIG. 4, in order to keep the output V1 constant in each characteristic of the characteristic lines C1 and C2, the characteristic line C1
Are adjusted in 14 steps, and the number of trimming steps of the characteristic line 2 is set to 12
You only need to adjust them in steps.

As described above, when the threshold value VT of the transistor is high, the value of the trimming data T1 to T4 is small, and when the threshold value VT of the transistor is low, the value of the trimming data T1 to T4 is large. , VT sum, and reflects the threshold value of the transistor.

The operation of the charge pump device 100 according to this embodiment will be described below with reference to FIGS. The crystal oscillation circuit 1 oscillates and outputs an oscillation signal F0 having a frequency of, for example, 32 KHz. This oscillation signal F0 is frequency-divided by a binary counter-2,
The signal is converted into an oscillation signal F1 having predetermined frequencies of 32 KHz and 2 KHz. The frequency adjustment circuit 3 receives the oscillation signal F1 from the binary counter 2 and the trimming data T1 to T4 from the trimming circuit 5,
An oscillation signal F having a frequency corresponding to the threshold value of the transistor
2 is output. The charge pump circuit 4 operates by being driven by the oscillation signal F2.

Here, the operation of the frequency adjusting circuit 3 for giving the operating frequency of the charge pump circuit 4 will be specifically described with reference to FIG. When the clock generation circuit 31 constituting the frequency selection circuit 3 receives the oscillation signals F1 having the frequencies of 32 KHz and 2 KHz from the binary counter 2, the clock generation circuit 31 calculates f1 <f2 <
.., <F15 <f16, and outputs them to the frequency selection circuit 32.

On the other hand, the decoder 33 outputs the trimming data T1 adjusted by the VT sum reference voltage circuit 6 described above.
To T4, for example, trimming data T1
When T4 is all "L", the decoder output D0 is activated and outputted to the frequency selection circuit 32. If the decoder output D0 is activated, the frequency selection circuit 32
The frequency F16 is selected, and the oscillation signal F2 of this frequency is output.

As described above, the frequency of the oscillation signal F2 is switched according to the trimming data T1 to T4 reflecting the transistor threshold VT, and the transistor threshold V
In a chip with a high T, a high frequency (f16 side) is selected and the operating frequency of the charge pump circuit 4 becomes high. In a chip with a low threshold VT, a low frequency (f1 side) is selected and the operating frequency of the charge pump circuit 4 becomes low. Lower. The fact that the frequency is low means that excessive current consumption of the charge pump circuit can be reduced. When the threshold value VT of the transistor is low, the current consumption of the charge pump circuit is suppressed.

In this embodiment, the trimming data (the number of trimmings) is 4 bits and the number of trimming steps is set to 16 steps. However, the number of trimmings may be increased to 4 bits or more. As a result, the operating frequency of the charge pump circuit 4 can be adjusted with higher accuracy, and the operating current can be reduced with higher accuracy. Further, even when the VT sum reference voltage circuit 6 is not provided, if the output of the charge pump circuit 4 is detected, and the detected value is reflected in the trimming data to adjust the operating frequency, the excess in the charge pump circuit 4 is similarly obtained. Operation current can be reduced.

According to this embodiment, since the trimming value depending on the threshold value VT of the transistor is used for the frequency of the charge pump circuit, an excessive operating current in the charge pump circuit 4 can be reduced. Moreover, conventional circuit blocks such as the binary counter 2 and the trimming circuit 5 can be used, and can be realized only by adding the frequency adjusting circuit 3.

That is, in the field of semiconductor integrated circuits used for digital timepieces and the like, the present invention provides a frequency adjusting circuit 3 capable of adjusting the frequency, and adjusts the trimming value used for the VT reference voltage circuit 6 by the frequency. It is characterized in that excessive operating current in the charge pump circuit 4 is reduced by incorporating it into the adjustment circuit 3,
By adding only a small circuit (frequency adjusting circuit 3) to the conventional digital clock LSI circuit, an optimum operating frequency can be selected in accordance with the threshold value VT of the transistor for each chip. Excessive operating current can be reduced.

[0033]

According to the present invention, the following effects can be obtained. That is, based on the trimming data, an oscillation signal having a frequency corresponding to the magnitude of the threshold value of the transistor reflected on the trimming data is generated, and the electric charge is transferred from a predetermined power supply to a predetermined output node driven by the oscillation signal. As a result, an optimum operating frequency can be selected according to the threshold value of the transistor, and an excessive operating current can be prevented.

In addition, an oscillation signal having a predetermined frequency is generated, and the frequency of the oscillation signal is adjusted based on the trimming data to obtain an oscillation signal having a frequency corresponding to the threshold value of the transistor. An oscillation signal having a frequency corresponding to the magnitude of the threshold value of the transistor reflected in the above can be generated.

Further, a plurality of clock signals having different frequencies are generated based on an oscillation signal having a predetermined frequency, and one of the clock signals is selected based on a decode signal of trimming data reflecting a threshold value of a transistor. Accordingly, an oscillation signal having a frequency corresponding to the magnitude of the threshold value of the transistor can be obtained.

Further, a reference oscillation signal of a reference frequency is generated, and an oscillation signal of a predetermined frequency is obtained by dividing the frequency of the reference oscillation signal, so that an oscillation signal of a predetermined frequency can be obtained.

Further, since the reference oscillation signal is generated by the crystal oscillation circuit, the reference frequency can be kept constant irrespective of the variation in the threshold value of the transistor.

[Brief description of the drawings]

FIG. 1 is a block diagram for explaining a configuration of a charge pump device according to an embodiment of the present invention.

FIG. 2 is a block diagram for explaining a configuration of a frequency adjustment circuit 3 according to the embodiment of the present invention.

FIG. 3 is a block diagram for explaining a configuration of a VT sum type reference voltage circuit and a trimming circuit according to the embodiment of the present invention;

FIG. 4 is a characteristic diagram showing a relationship between an output voltage of the VT sum type reference voltage circuit and the number of trimming steps according to the embodiment of the present invention;

FIG. 5 is a block diagram for explaining a configuration of a charge pump device according to a conventional technique.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 crystal oscillator circuit 2 binary counter 3 frequency adjustment circuit 4 charge pump circuit 5 trimming circuit 6 VT sum reference voltage circuit 31 clock generation circuit 32 frequency selection circuit 33 , 51 ... decoder,
61: current source, 62: operational amplifier, P63: Pch transistor, N63: Nch transistor, R0 to R
15, R64: resistor, 100: charge pump device, 2
00: Reference voltage generation circuit.

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields investigated (Int. Cl. ⁶ , DB name) H02M 3/07 G04C 3/14 G04G 1/00 310 G05F 3/00-3/30

Claims (5)

(57) [Claims] 1. A charge incorporated in a semiconductor integrated circuit having trimming data reflecting a threshold value of a transistor and having a function of compensating a variation in circuit characteristics due to the threshold value of the transistor based on the trimming data. A pump device, based on the trimming data, a signal generating unit that generates an oscillation signal having a frequency corresponding to a magnitude of a threshold value of a transistor reflected in the trimming data, and a predetermined power supply driven by the oscillation signal. And a charge transfer means for transferring the charge to a predetermined output node. 2. An oscillation signal generation unit that generates an oscillation signal of a predetermined frequency, wherein the signal generation unit adjusts a frequency of the oscillation signal based on the trimming data, and adjusts a frequency of the oscillation signal in accordance with a threshold value of the transistor. The charge pump device according to claim 1, further comprising: a frequency adjustment unit that obtains an oscillation signal having a frequency. 3. The frequency adjustment unit includes: a clock generation circuit that generates a plurality of clock signals having different frequencies based on an oscillation signal of a predetermined frequency from the oscillation signal generation unit; and a decoder that decodes the trimming data. A frequency selection circuit that selects one of the plurality of clock signals from the clock generation circuit based on the output signal of the decoder, and outputs the selected signal as an oscillation signal having a frequency corresponding to the threshold value of the transistor. The charge pump device according to claim 2, further comprising: 4. The oscillation signal generation section includes: an oscillation circuit that generates a reference oscillation signal having a reference frequency; and a binary counter that divides the reference oscillation signal to obtain an oscillation signal having the predetermined frequency. The charge pump device according to claim 2, wherein: 5. The charge pump device according to claim 4, wherein said oscillation circuit comprises a crystal oscillation circuit.