JP2907714B2 - Correlation degree detection device - Google Patents
Correlation degree detection deviceInfo
- Publication number
- JP2907714B2 JP2907714B2 JP7711494A JP7711494A JP2907714B2 JP 2907714 B2 JP2907714 B2 JP 2907714B2 JP 7711494 A JP7711494 A JP 7711494A JP 7711494 A JP7711494 A JP 7711494A JP 2907714 B2 JP2907714 B2 JP 2907714B2
- Authority
- JP
- Japan
- Prior art keywords
- output
- states
- subtraction
- correlation degree
- correlation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Compression Or Coding Systems Of Tv Signals (AREA)
- Image Analysis (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は、信号処理装置のうち、
２種類のデータ列の相関度を検出する装置であって、特
に画像データの動きベクトル検出に有効である。BACKGROUND OF THE INVENTION The present invention relates to a signal processing device,
This is a device for detecting the degree of correlation between two types of data strings, and is particularly effective for detecting a motion vector of image data.
【０００２】[0002]
【従来の技術】画像圧縮を実現する方法として、前フレ
ーム画像と現フレーム画像を比較し、似かよった（相関
が高い）部分を前フレーム画像から選出し、それを用い
て時間的冗長性を削減する動きベクトル検出というアル
ゴリズムがある。このアルゴリズムを実現する方法とし
て、ブロックマッチング法があり、コストパフォーマン
スが良く、一般に使われている。このブロックマッチン
グ法では、画像を小さなブロックに分け、着目するブロ
ックが前フレームのどの位置から来たのかを、画素間の
差の絶対値和を調べながらサーチして行く。この場合、
２つの画像間の相関を求めるため１回の試行に時間を要
する上、複数回の試行を行う必要があり、その試行回数
が多いほど、相関度の高い画像を検出する可能性が高く
なる。そのため、１つの装置の中に複数個の相関度検出
装置を備え、それらを並列動作させることにより、高速
化を図っている。例えば従来の相関度検出装置の一例と
して、「Proceeding of ICASSP pp.2453〜2456(1989)」
に減算回路と絶対値回路と累算回路で構成されている例
が記載されている。この相関度検出装置を用いて、並列
処理を行えば、高速な演算が実現できるという利点があ
る一方、複数個の相関度検出装置が必要となるため、面
積が大きくなり、消費電力も増大する。2. Description of the Related Art As a method of realizing image compression, a previous frame image is compared with a current frame image, a similar (highly correlated) portion is selected from the previous frame image, and temporal redundancy is reduced using the same. There is an algorithm called motion vector detection. As a method of realizing this algorithm, there is a block matching method, which has good cost performance and is generally used. In this block matching method, an image is divided into small blocks, and a search is made for the position of the block of interest from the previous frame while checking the absolute value sum of the difference between pixels. in this case,
In order to obtain the correlation between two images, it takes time for one trial, and it is necessary to perform a plurality of trials. As the number of trials increases, the possibility of detecting an image with a high degree of correlation increases. For this reason, a plurality of correlation degree detection devices are provided in one device and operated in parallel to increase the speed. For example, as an example of a conventional correlation detection device, "Proceeding of ICASSP pp. 2453-2456 (1989)"
Describes an example composed of a subtraction circuit, an absolute value circuit, and an accumulation circuit. Performing parallel processing using this correlation detection device has the advantage that high-speed operation can be realized. On the other hand, since a plurality of correlation detection devices are required, the area increases and power consumption increases. .
【０００３】[0003]
【発明が解決しようとする課題】このような従来の相関
度検出装置では、２つのデータの差分をとった後、その
符号ビットを用いて絶対値を求め、その結果を累算する
ため、回路規模が大きく、特に動きベクトル検出装置で
は、処理の高速化のために、上記装置を複数個用いるた
め、面積と消費電力が多くなるという問題があった。In such a conventional correlation degree detection apparatus, a circuit is used to calculate the absolute value by using the sign bit after calculating the difference between two data and accumulate the result. Since the scale is large, and especially the motion vector detecting device uses a plurality of the above devices for speeding up the processing, there is a problem that the area and the power consumption increase.
【０００４】本発明は、上記課題を解決するもので、小
規模な回路により、省面積、低消費電力を図る相関度検
出装置を提供することを目的としている。An object of the present invention is to solve the above-mentioned problems, and an object of the present invention is to provide a correlation degree detecting apparatus which saves area and consumes low power by using a small-scale circuit.
【０００５】[0005]
【課題を解決するための手段】上記目的を達成するため
に、本発明の相関度検出装置は、データ数が等しい２種
類の２の補数で表現されるゼロまたは正の整数のデータ
列の相関度を検出する装置であって、２種類のデータ列
の差分をとる減算手段と、前記減算手段の出力値に対し
て所定の関数に従って２状態を取り、前記２状態の一方
ならば「１」、他方ならば「０」を出力する２値化手段
と、前記２値化手段の出力を累算する累算手段と、前記
累算手段の出力を保持する記憶手段とを備え、前記２値
化手段は、前記減算手段の出力をＤとすると、Ｄ＜−２
n 、またはＤ＞（２ n −１）の場合と、−２ n ≦Ｄ≦（２ n
−１）の場合（但し、ｎはゼロまたは正の整数）により
２状態をＥＸＯＲを用いて出力する構成を採用する。 To achieve the above Symbol purposes SUMMARY OF THE INVENTION, correlation degree detecting apparatus of the present invention, the number of data is equal to two
Zero or positive integer data represented by two's complement of class
A device for detecting the degree of correlation between columns, comprising two types of data columns
Subtraction means for taking the difference of
Takes two states according to a predetermined function, and takes one of the two states
Binarizing means for outputting "1" if it is, and "0" otherwise.
Accumulating means for accumulating an output of the binarizing means;
Storage means for holding the output of the accumulating means;
The converting means, assuming that the output of the subtracting means is D, D <-2
n or D> (2 n −1), and −2 n ≦ D ≦ (2 n
-1) (where n is zero or a positive integer)
A configuration in which two states are output using EXOR is employed.
【０００６】[0006]
【作用】本発明では、上記した構成により、２値化手段
が減算手段の出力をＤとすると、Ｄ＜−２ n 、またはＤ
＞（２ n −１）の場合と、−２ n ≦Ｄ≦（２ n −１）の場
合（但し、ｎはゼロまたは正の整数）により２状態を、
減算手段の出力値に対して、ＥＸＯＲを用いて出力す
る。累算手段は２状態の一方ならば「１」加算し、他方
ならば加算を行なわないようにしたので、絶対値手段が
省略できるとともに累算手段が簡略化できるため、小規
模な回路になり、省面積化、低消費電力化が図れる。According to the present invention, the binarizing means has the above-described structure.
Let D <-2 n , or D
> (2 n -1) and the case of -2 n ≤ D ≤ (2 n -1)
If (where n is zero or a positive integer) two states,
The output value of the subtraction means is output using EXOR.
You. Since the accumulating means adds "1" in one of the two states and does not perform the adding in the other state, the absolute value means can be omitted and the accumulating means can be simplified. In addition, the area and the power consumption can be reduced.
【０００７】[0007]
【実施例】以下、本発明の一実施例について説明する。An embodiment of the present invention will be described below.
【０００８】本発明の一実施例について、図１を参照し
ながら説明する。図１に示すように、１０は減算手段、
３０は累算手段、４０は例えばラッチからなる記憶手段
である。２０は減算手段の出力をＤとすると、ｎ＝２の
場合を例に上げて考えると、Ｄ＜−４またはＤ＞３の場
合と、−４≦Ｄ≦３の場合により２状態を出力する関数
を有する２値化手段である。An embodiment of the present invention will be described with reference to FIG. As shown in FIG. 1, 10 is a subtraction means,
Reference numeral 30 denotes an accumulating unit, and reference numeral 40 denotes a storage unit including, for example, a latch. If the output of the subtracting means is D, and if the case where n = 2 is taken as an example, two states are output depending on the case of D <−4 or D> 3 and the case of −4 ≦ D ≦ 3. a binarization means having a function.
【０００９】上記構成において、３ビットの２の補数で
表現されるデータ数が等しい２種類のデータ列Ａ（２：
０）、Ｂ（２：０）は、減算手段１０により減算され、
その結果は２値化手段２０により、２状態のいずれか一
方を取る。つまり、２値化手段２０は、Ｄ＜−４または
Ｄ＞３の場合は「１」、−４≦Ｄ≦３の場合は「０」の
いずれか一方を取る。累算手段３０は２状態の一方なら
ば「１」加算し、他方ならば「０」加算を行う。本実施
例では累算手段３０は２値化手段の出力を累算し、その
累算結果を記憶手段４０に記憶する。In the above configuration, two types of data strings A (2: 2) having the same number of data represented by 3-bit two's complement numbers
0) and B (2: 0) are subtracted by the subtraction means 10,
The result is the binary means 20 takes one of two states. That is, binarization unit 20, if D of <4 or D> 3 "1", - 4 for ≦ D ≦ 3 take either "0". The accumulating means 30 adds "1" if it is one of the two states, and adds "0" if it is the other. In this embodiment, the accumulation means 30 accumulates the output of the binarization means and stores the accumulation result in the storage means 40.
【００１０】以下の（表１）に「Ａ−Ｂ」の１０進数と
２進数での表記と２値化手段２０の結果を示す。図２に
２値化手段２０の特性図を示す。The following (Table 1) shows the notation of "AB" in decimal and binary numbers and the result of the binarizing means 20. FIG. 2 shows a characteristic diagram of the binarizing means 20.
【００１１】[0011]
【表１】 [Table 1]
【００１２】（表１）から分かるように減算手段出力
「Ａ−Ｂ」の２進数の上位２ビットのＥＸＯＲを行うこ
とにより、２値化でき、その出力を直接累算手段３０で
累算できる。そのため２値化手段２０は１つのＥＸＯＲ
のみで構成できる。As can be seen from Table 1, EXOR of the upper two bits of the binary number of the subtraction means output "AB" can be binarized, and the output can be directly accumulated by the accumulation means 30. . Therefore, the binarizing means 20 has one EXOR
It can be composed only of.
【００１３】このように、本実施例の相関度検出装置に
よれば、２値化手段が簡略化できるため、さらに小規模
な回路になり、ブロックマッチング法を省面積化、低消
費電力化で実現できる。[0013] Thus, according to the correlation degree detecting apparatus of the present embodiment, since the binarization unit can be simplified, made more small-scale circuit, the block matching method area saving, low power consumption realizable.
【００１４】なお、ここでは入力信号のビット数を３ビ
ット（ｎ＝２）としたが、１ビット（ｎ＝０）以上であ
ればなんら問題がない。Here, the number of bits of the input signal is 3 bits (n = 2), but there is no problem if it is 1 bit (n = 0) or more.
【００１５】また、ここでは２状態により「１」加算と
「０」加算を累算手段により実行したが、「０」加算の
代わりに１回前の加算結果をそのまま保持し続けてもな
んら問題がない。In this case, "1" addition and "0" addition are executed by the accumulating means depending on the two states. However, there is no problem if the previous addition result is kept as it is instead of "0" addition. There is no.
【００１６】[0016]
【発明の効果】以上のように本発明は、データ数が等し
い２種類の２の補数で表現されるゼロまたは正の整数の
データ列の相関度を検出する装置であって、２種類のデ
ータ列の差分をとる減算手段と、前記減算手段の出力値
に対して所定の関数に従って２状態を取り、前記２状態
の一方ならば「１」、他方ならば「０」を出力する２値
化手段と、前記２値化手段の出力を累算する累算手段
と、前記累算手段の出力を保持する記憶手段とを備え、
前記２値化手段は、前記減算手段の出力をＤとすると、
Ｄ＜−２ n 、またはＤ＞（２ n −１）の場合と、−２ n ≦
Ｄ≦（２ n −１）の場合（但し、ｎはゼロまたは正の整
数）により２状態をＥＸＯＲを用いて出力する構成を採
用するので、絶対値手段が省略できるとともに累算手段
が簡略化できるため、小規模な回路になり、省面積化、
低消費電力化が図れる。As described above, according to the present invention, the number of data is equal.
Two or two complements of zero or a positive integer
An apparatus for detecting the degree of correlation between data strings.
Subtraction means for taking a difference between data sequences, and an output value of the subtraction means
Takes two states according to a predetermined function,
A binary value that outputs “1” if one of them is output and “0” if the other is
Conversion means and accumulation means for accumulating the output of the binarization means
And storage means for holding the output of the accumulation means,
The binarizing means sets the output of the subtracting means to D,
D <−2 n or D> (2 n −1), and −2 n ≦
D ≦ (2 n −1) (where n is zero or a positive integer)
Number) is used to output two states using EXOR.
Since the absolute value means can be omitted and the accumulating means can be simplified, the circuit becomes small-scale,
Low power consumption can be achieved.
【図１】本発明の一実施例の相関度検出装置のブロック
図FIG. 1 is a block diagram of a correlation detection apparatus according to an embodiment of the present invention;
【図２】同実施例の２値化手段の特性図FIG. 2 is a characteristic diagram of a binarizing unit according to the embodiment;
１０ 減算手段 ２０ ２値化手段 ３０ 累算手段 ４０ 記憶手段10 subtraction means 20 binarization unit 30 accumulating means 40 storage means
Claims (1)
されるゼロまたは正の整数のデータ列の相関度を検出す
る装置であって、 ２種類のデータ列の差分をとる減算手段と、前記減算手段の出力値 に対して所定の関数に従って２状
態を取り、前記２状態の一方ならば「１」、他方ならば
「０」を出力する２値化手段と、 前記２値化手段の出力を累算する累算手段と、 前記累算手段の出力を保持する記憶手段とを備え、 前記２値化手段は、前記減算手段の出力をＤとすると、
Ｄ＜−２n、またはＤ＞（２n−１）の場合と、−２n≦
Ｄ≦（２n−１）の場合（但し、ｎはゼロまたは正の整
数）により２状態をＥＸＯＲを用いて出力することを特
徴とする相関度検出装置。1. Two types of two's complement numbers having the same number of data
A subtraction means for calculating a difference between two types of data strings, and two states in accordance with a predetermined function with respect to an output value of the subtraction means. taken, the if one of the two states "1", if the other and binarization means for outputting "0", and accumulation means for accumulating the output of the binarization means, the output of the accumulator means and a storage means for holding said binarization means, the output of the subtraction means when is D,
D <−2 n or D> (2 n −1), and −2 n ≦
A correlation degree detection apparatus for outputting two states using EXOR when D ≦ (2 n −1) (where n is zero or a positive integer).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7711494A JP2907714B2 (en) | 1994-04-15 | 1994-04-15 | Correlation degree detection device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7711494A JP2907714B2 (en) | 1994-04-15 | 1994-04-15 | Correlation degree detection device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH07288812A JPH07288812A (en) | 1995-10-31 |
| JP2907714B2 true JP2907714B2 (en) | 1999-06-21 |
Family
ID=13624767
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7711494A Expired - Fee Related JP2907714B2 (en) | 1994-04-15 | 1994-04-15 | Correlation degree detection device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2907714B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4525063B2 (en) * | 2003-12-11 | 2010-08-18 | ソニー株式会社 | Motion vector detection apparatus, motion vector detection method, and computer program |
-
1994
- 1994-04-15 JP JP7711494A patent/JP2907714B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH07288812A (en) | 1995-10-31 |
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| LAPS | Cancellation because of no payment of annual fees |