JP2906407B2 - Semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having excellent reliability. [Prior Art] Conventionally, an emitter electrode of a GaAs / AlGaAs pnp type heterojunction bipolar transistor has been used, for example, in Applied Physics Letter 46: 302 (1985) (Appl. Phys. Lett.
46 , 302 (1985)), AuZn-based materials and the like have been used. The main reason for this is that n-channel FETs are mainly used in FETs, and npn-types are mainly used in bipolar transistors. [Problems to be Solved by the Invention] The above prior art does not consider the problem of the p-type electrode peculiar to an electronic device such as a pnp-type bipolar transistor, and metal such as Zn diffuses very deeply into GaAs. Then pn
There was a problem that the bonding deteriorated. In electronic devices, it is desirable that the p-type layer has a thickness of about 200 to 300 mm,
Since it cannot be made as thick as 2-3 μm like a semiconductor laser, Zn
Metal diffuses deeply into the n-type layer until the metal deteriorates the pn junction. For example, in a pnp type two-dimensional electron gas heterojunction bipolar transistor (described in Japanese Patent Application No. 61-4024, hereinafter abbreviated as 2DEG-HBT), an appropriate type of two-dimensional electron gas is indispensable. That is, it is necessary that GaAs has a high mobility and a steep heterojunction is preserved. However, AuZn-based electrodes conventionally used as ohmic electrodes for p-type GaAs are characterized by forming an ohmic contact using an alloy, but Zn tends to diffuse very deeply in GaAs. It has been found that the pn junction deteriorates. This Zn diffusion may reach as much as 1 μm. In particular, deterioration of ohmic characteristics (specific contact resistance ρc) was observed at the time of forming the surface protective film CVDSiO ₂ and at the time of forming the insulating film accompanying the wiring process. This deterioration phenomenon is due to the diffusion of Zn, and from the problems of deterioration of the pn junction characteristics and deterioration of the ohmic characteristics ρc,
When such an electronic device is applied to an integrated circuit, there is a major problem in terms of reliability. Also, with miniaturization of emitter dimensions, it is desirable to reduce emitter resistance. Specific contact resistance ρc is 10 ⁻⁶ Ωcm
^When it exceeds ² , the emitter resistance becomes dominant in the large collector current region, and the deterioration of the current amplification factor and the cutoff frequency comes to the surface. An object of the present invention is to provide a semiconductor device having ohmic contact with excellent reliability. [Means for Solving the Problems] The above object, p ⁺⁺ GaAs layer or ^{_{p ++ In y Ga 1-y}} As layer a metal layer of non-alloy type is disposed in ohmic contact with the top of, and,
a p-type impurity p ⁺⁺ GaAs layer or ^{_{p ++ In y Ga 1-y}} As layer and substantially carbon, carbon concentration of p ⁺⁺ GaAs layer is 5 × 10 ¹⁹ cm
^-3 or more, the specific contact resistance of ohmic contact is 10 ^-6 Ωcm ² or less, and the carbon concentration of the p ⁺⁺ In _y Ga _1-y As layer is 1 × 10 ¹⁹ cm ^-3.
As described above, the specific contact resistance of the ohmic contact is achieved by the semiconductor device having the resistivity of 10 ⁻⁶ Ωcm ² or less. Further, the p ⁺⁺ In _y Ga _1-y As layer is formed of p-type GaAs or p-type Al _x Ga
It is preferable that the value of y is small on the side closer to the _1-x As layer and the composition is graded so that the value of y is large on the opposite side. As a non-alloy type metal, the diffusion into the p ⁺⁺ GaAs layer or p ⁺⁺ In _y Ga _1-y As layer which forms an ohmic contact with this metal should be so shallow that it does not affect other layers. Requested,
Ti / Pt / Au, Mo / Au, W, WSi, Au, WN, WAl and the like can be used. In particular, since WSi, WAl, WN, W, and the like are excellent in workability, the dimensions of the emitter electrode and the emitter can be made the same by using a dry etching method. Therefore, it is preferable to use these metals. This is particularly effective when forming an integrated circuit. This will be described with reference to FIG. Fig. 1 (a)
FIG. 2B is a cross-sectional view of a principal part of the semiconductor device, schematically illustrating the present invention. In FIG. 1A, 71 is a p-type GaAs layer (or p-type Al _x Ga _{1 -x} As) usually connected to the emitter region, and 70 is 5
A p ⁺⁺ GaAs layer containing a p-type impurity of about × 10 ¹⁹ Ωcm ^-3 (or a p ⁺⁺ I containing a p-type impurity of about 1 × 10 ¹⁹ Ωcm ^-3)
n _y Ga _1-y As layer, in which case the lower layer is p-type GaAs
The composition is connected to the layer 71, and the composition is preferably inclined by changing the value of y.) 60 is a non-alloy type metal, such as Ti / Pt / Au or Mo / Au. . Such a structure can be formed by a normal lift-off method. On the other hand, FIG. 1 (b) shows a non-alloy type metal as WS
In this example, a metal excellent in workability such as i, W Al, W, etc. is used. In this case, the p ⁺⁺ GaAs layer 70 and the P-type GaAs
Layer 71 may be etched away by dry etching to form the shape as shown. [Operation] In the present invention, unlike the alloy type ohmic contact, there is no diffusion of atoms forming a level in the GaAs layer, so that a highly reliable ohmic contact can be obtained. For the same reason, the deterioration of the specific contact resistance ρc is small, and
A value of about ^-6 Ωcm is obtained. Embodiment An embodiment of the present invention will be described below with reference to the drawings. Embodiment 1 FIG. 2 shows an example in which the present invention is applied to a pnp type 2DEG-HBT.
In the figure, 50 is Ti (300Å) / Pt (300Å) / Au (1500
Å) The emitter electrode 17 is a p-type electrode containing C at 1 × 10 ²⁰ cm ^−3.
++ GaAs (1000Å), 16 is p-type containing 5 × 10 ¹⁷ cm ^-3 of C
GaAs (1500Å), 15 is p-type Al containing the same concentration of C as 16
GaAs (1000Å), 14 is n-type AlGa containing 4 × 10 ¹⁸ cm ^-3 of Si
As (250 °), 13 is undoped AlGaAs (50 °), 12 is undoped (p ⁻ ) GaAs (1500 °), and 11 is C at 5 × 10 ¹⁹ cm ^−3.
Including p ⁺ GaAs (5000 °), 10 is a semi-insulating GaAs substrate.
The base electrode 51 and the collector electrode 52 are formed according to ordinary specifications. Such a multilayer film is formed by gas source MBE (MO-MBE)
However, it may be formed by the MOCVD method. Element isolation was performed by mesa isolation. The emitter electrode is WSi (3500
After the deposition of Å), it may be formed by dry etching. When an organic metal (for example, trimethylgallium) is used as a gas source by MO-MBE, C (carbon) can be doped as a p-type impurity. In this case, roughly
Doping can be performed up to 10 ²⁰ cm ^-3, and C does not diffuse even after a heating step of 800 ° C. or more. In this semiconductor device, deterioration of the pn junction was prevented, and the specific contact resistance ρc was reduced to 10 ⁻⁶ Ωcm ² or less. In the present embodiment, p ⁺⁺ GaAs is used as 17 but p ⁺⁺
An In _y Ga _1-y As layer can also be used. Embodiment 2 FIG. 3 shows an embodiment in which the present invention is applied to a normal pnp type HBT. 50 is an emitter electrode of Mo (1500Å) / Au (1500Å), 21
Is a p ⁺⁺ In _y Ga _1-y As layer containing C at 5 × 10 ¹⁹ cm ⁻³ (0.5 ≦ y ≦ 0
, The value of y is small below the layer, and the value of y is large above the layer. 1500Å), 20 is C 6 × 10 ¹⁷ cm
^-3 containing p-type GaAs (1000Å), 19 is a p-type Al _x Ga _1-x As containing x 6 × 10 ¹⁷ cm ^-3 (x = 0.45, 1000Å), 18 is a base layer
N-type GaAs (1000 °) containing 4 × 10 ¹⁸ cm ^-3 of Si;
Is 2 × 10 ¹⁶ cm ^−3, a collector p-type GaAs (3000 mm), 11 is a collector layer, p ⁺ GaAs containing 5 × 10 ¹⁸ cm ⁻³ C (3000 mm),
10 is a semi-insulating GaAs substrate. The base electrode 51 and the collector electrode 52 are formed by a usual method. These multilayer films are also formed by the MO-MBE method as in the first embodiment. The effect of the second embodiment was similar to that of the first embodiment. In these embodiments, the example in which the emitter region is formed on the surface side of the emitter top structure has been described. It is effective to apply the present invention to the formation. That is, n
The presence of the base layer, which is a layer, causes a problem of deterioration of the pn junction between the collector base and a problem of the connector resistance. In this case, the problem can be solved by applying the present invention. [Effects of the Invention] According to the present invention, a metal having low diffusivity and a high concentration of p ⁺⁺ G
Since the formation of the ohmic electrode portion to the emitter region with the junction of aAs or ^{_{p ++ In y Ga 1-y}} As, prevents deterioration of the pn junction,
The specific contact resistance ρc can be reduced to 10 ⁻⁶ Ωcm or less.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a sectional view of a main part of one embodiment for explaining the present invention, and FIGS. 2 and 3 are sectional views of a semiconductor device of one embodiment of the present invention, respectively. It is. 10 ...... semi-insulating GaAs substrate ^{11 ...... p + GaAs, 12 ......} (p -) GaAs 12 '...... p -type GaAs, 13 ...... Al GaAs 14 ...... n-type Al GaAs, 15 ...... p-type Al GaAs 16: p-type GaAs, 17: p ⁺⁺ GaAs 18: n-type GaAs, 19: p-type Al _x Ga _1-x As 20: p-type GaAs, 21: p ⁺⁺ In _y Ga _1-y As 50: Emitter electrode, 51: Base electrode 52: Collector electrode, 60: Non-alloy type metal 70: p ⁺⁺ GaAs, 71: p-type GaAs

   ────────────────────────────────────────────────── ─── Continuation of front page    (72) Inventor Tomoyoshi Mishima               1-280 Higashi Koikebo, Kokubunji-shi, Tokyo                 Central Research Laboratory, Hitachi, Ltd.                (56) References JP-A-60-160664 (JP, A)                 JP-A-60-244065 (JP, A)                 JP-A-62-232122 (JP, A)                 Applied Physics L               letters vol. 50 no. 20               pp. 1435-37 (1987)

Claims (1)

(57) [Claims] A non-alloy type metal layer is arranged on the p ⁺⁺ GaAs layer or the p ⁺⁺ In _y Ga _1-y As layer and brought into ohmic contact, and the p ⁺⁺ G
substantially carbon a p-type impurity aAs layer or _{^{p ++ In y Ga 1-y}} As layer, the carbon concentration of the p ⁺⁺ GaAs layer is 5 × 10 ¹⁹ cm
^-3 or more, the specific contact resistance of the above ohmic contact is 10 ^-6 Ωcm ²
The carbon concentration of the p ⁺⁺ In _y Ga _1-y As layer is 1 × 1
0 ¹⁹ cm ^-3 or more, specific contact resistance of the above ohmic contact is 10 ^-6
A semiconductor device having a resistivity of Ωcm ² or less. 2. The metal layer and the p ⁺⁺ GaAs layer or the p ⁺⁺ In _y Ga _1-y As layer are all arranged in substantially the same pattern and substantially at the same position in a plane. 2. The semiconductor device according to claim 1, wherein: 3. The p ⁺⁺ GaAs layer or _{^{p ++ In y Ga 1-y}} As layer and the metal layer is in the range first claims, characterized in that the emitter electrode of the pnp bipolar transistor of the emitter top structure 3. The semiconductor device according to item 2 or 2. 4. The p ⁺⁺ GaAs layer or _{^{p ++ In y Ga 1-y}} As layer and the metal layer is in the range first of the claims characterized in that it constitutes a collector electrode of the pnp type bipolar transistor collector top structure 3. The semiconductor device according to item 2 or 2.