JP2903946B2 - Multi-chip semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
The present invention relates to a multi-chip semiconductor device mounted on one substrate, and more particularly to an improvement in a test function of each semiconductor chip.

[0002]

2. Description of the Related Art First, a single-chip (MOS) semiconductor device will be described with reference to FIG. That is, one semiconductor chip 1 is mounted on one substrate (package) 2. Input pad P ₁ is P-channel transistor in the semiconductor chip 1 Q _P1 and an N-channel transistor Q
is connected to an input buffer consisting of _n1, in this case, between the input Pas <br/> head P ₁ and input buffer (Q _P1, Q _n1), overvoltage (overvoltage, under-voltage) protection diodes Q against
_P2 and _Qn2 are connected. The protection diode Q _P2 is a P-channel transistor having a source and a gate connected to each other, so that the voltage of the input / output pad P ₁ is VCC + | V _thp
| (V _thp is the threshold voltage of the P-channel transistor)
When the voltage becomes larger, the protection diode Q _P2 is turned on and the voltage of the input pad P ₁ (that is, the input buffer (Q
The input voltage of _P1 and _Qn1 ) is prevented from becoming high.
On the other hand, the protection diode Q _n2 source - an N-channel transistor having the gate is connected, therefore, the input pad <br/> de voltage GND-V _thn (V _thn of P ₁ is the threshold of the N-channel transistor input pads P ₁ of the voltage protection diode Q _n2 when it becomes smaller than the voltage) becomes oN (i.e., the input buffer (Q _P1, Q _n1) input voltage) is prevented from becoming low voltage. Entry of the substrate 2 by the input <br/> pad P ₁ of the semiconductor chip 1 is a bonding wire W ₁
The force pad P ₁ ′ is connected to the input pin T ₁ by the internal wiring C ₁ .

In the semiconductor chip 1, a P-channel transistor Q _P3 and an N-channel transistor Q _n3
Become more output buffers are connected to the output pad P _2. The output pad P ₂ ′ of the semiconductor chip 1 is connected to the output pad P ₂ of the substrate ₂ by a bonding wire W ₂ , and the output pad P ₂ ′ is connected to the output pin T ₂ by an internal wiring C ₂ . . The output buffers (Q _P3 , Q _n3 ) also have protection diodes equivalently. That is, as shown in FIG. 6, in the case of the CMOS structure, P ^- is the power supply voltage GND to the semiconductor substrate is applied, P ^- the N ⁺ impurity layer in a semiconductor substrate output buffer (Q _P3, Q
Since the output OUT, i.e. the output pads P ₂ of _n3) is connected to the PN junction diode D1 is formed therebetween acts as a protection diode for low-voltage, in the case of the other,
N ^- power supply voltage VCC is applied to the well N ^- P in the well
⁺ Output OU of output buffer (Q _P3 , Q _n3 ) in impurity layer
PN junction diode D2 to be formed therebetween so T clogging output pad P ₂ is connected to act as a high-voltage protection diode.

Thus, in FIG. 5, the pads, for example, P ₁ of the semiconductor chip ₁ and the pins, for example, T _{1 of the} substrate 2 have a one-to-one correspondence.

[0005] Next, the input of the single-chip open-short test for example, a semiconductor chip 1 of the semiconductor device shown in FIG. 5
A case where the connection between the force pin P ₁ and the input pin T ₁ of the substrate 2 is tested will be described. First, the power supply V of the semiconductor chip 1
CC and GND are set to 0 V via a pin (not shown).
Next, connect the input pin T ₁ to the terminal C of the diode bridge circuit shown in FIG. 7 (A), the output pin T ₂ to 0V. In this state, 2 is connected to the terminal A of the diode bridge circuit.
A voltage of about V is applied, and a constant current of about 300 μA flows between the terminals B and C (see FIG. 7B).

[0006] If abnormality of open short circuit in FIG. 5, N channelization transistor Q _n2 of a protective diode is turned on, the result, the voltage of the terminal C of the voltage, i.e. the diode bridge circuit on the input pin T ₁ is N Channel transistor threshold voltage -V _thn, for example -0.6
V.

If the input pin T ₁ and the output pin T ₂ shown in FIG. 5 are short-circuited, the voltage of the output pin T ₂ is 0 V. Therefore, the voltage of the input pin T ₁ , that is, the terminal C of the diode bridge circuit. Becomes 0V. Further, if the open between the input pin T ₁ and the input pad P ₁ in FIG. 5, the voltage of the terminal C of the voltage, i.e. the diode bridge circuit on the input pin <br/> down T ₁ is the voltage at terminal A, that - 2V.

As described above, the connection test between the input pin T ₁ and the input pad P ₁ is performed by judging that the voltage of the terminal C of the diode bridge circuit is any one of −0.6 V, 0 V, and −2 V. I can do it. It performed in the same manner by using a protection diode D1 inherent Setsuzoku also tested as shown in Figure 6 the output pin T ₂ and the output pad P _2.

Next, a multi-chip semiconductor device will be described with reference to FIG. That is, a plurality of substrates, for example, 3
Semiconductor chips 1-1, 1-2, and 1-3 are mounted. Each semiconductor chip 1-1, 1-2, and 1-3 of the pad (not shown) pad P of the substrate 2 'is connected to the bonding wire (not shown), the substrate 2 pads P'
Is connected to the pin T by the internal wiring C. In such a multi-chip semiconductor device, as shown in FIG.
Pads of a plurality of semiconductor chips may be connected to one pin T of the substrate 2 in some cases.

FIG. 9 is a partially detailed view of FIG. 8, showing a case where pads of two semiconductor chips 1-1 and 1-2 are connected to one pin . That is, the semiconductor chip 1-
An output buffer of the first input buffer (Q _P1, Q _n1) connected input pad to <br/> de P ₁ and the semiconductor chip 1-2 (Q _P3, Q
connected output pads P ₂ to _n3) is connected to the input pad P ₁ ', the output pad P _2' and one of the input and output pins T ₁ via the internal wiring C ₁ of the substrate 2.

[0011]

An invention has had, however, input and output pins T ₁ to the input pad P ₁ shown in FIG. 9, the output pad P
When performed by a diode bridge circuit showing a connection test between ₂ to 7, open between the input and output pins T ₁ is open between the input pad P ₁ and input and output pins T ₁ and the output pad P ₂ is Can be determined to be open only when, but if only one of them is open, there is a problem that it cannot be determined to be open because it is normally connected and the protection diode of the semiconductor chip is turned on.

There is a so-called ECIPT test structure for inactivating a specific semiconductor chip (see Japanese Patent Application Laid-Open No. 64-10184). Such a test structure is provided in a semiconductor chip. However, open / short tests of individual semiconductor chips are not possible. Therefore, the object of the present invention is to open individual semiconductor chips.
An object of the present invention is to provide a multichip semiconductor device capable of performing a short test.

[0013]

Means for Solving the Problems To solve the above problems,
The means for this is shown in FIG. That is, each semiconductor chip
1-1 and 1-2 are connected to an internal circuit.pad
P₁, P_Two,thispadP₁, P_TwoBetween the power line GND
Connected switching transistor Q_n4, Q_n6Control
Additional topadP_Three, P_FourIs provided. On the other hand,
The substrate 2 has the semiconductor chips 1-1 and 1-2.padP
₁, P_TwoConnected topadP₁', P_Two', Each semiconductor chip
1-1, 1-2 additionalpadP_Three, P_FourAttached to
AdditivepadP_Three', P_Four',thesepadP₁', P_TwoConnect to '
Was donepinT₁And additionalpadP_Three', P_Four'Connected to
Test pin T_Three, T_FourIs provided.

[0014]

According to the above-mentioned means, each semiconductor chip 1-1,
1-2, the switching transistors Q _n4 , Q
By controlling on and off of _n6 , each input / output unit of the semiconductor chip is activated and deactivated.

[0015]

FIG. 2 shows a first embodiment of a multichip semiconductor device according to the present invention. In FIG. 2, the components of FIG. 9 include an N-channel transistor Q _n4 as a switch,
P-channel transistor Q _p5 and N-channel transistor Q _n5 as protection diodes, input pad P ₃ ,
P ₃ ′, test pin T ₃ , N-channel transistor Q _n6 as a switch, P-channel transistor Q _p7 and N-channel transistor Q _n7 as protection diodes, input
Pads P ₄ and P ₄ ′ and a test pin T ₄ are added. That is, turning on the transistor Q _n4 by the voltage of the input pad P ₃ of the semiconductor chip 1-1 is intended to off control, the input pad P ₃ are connected by a bonding wire W ₃ to the input pad P ₃ of the substrate 2 ' It is further connected to the test pin T ₃ by internal wiring C _3. Similarly, on the transistor Q _n6 by the voltage of the input pad P ₄ of the semiconductor chip 1-2 is intended to off control, connect the input pad P ₄ to the input pad P ₄ 'of the substrate 2 by a bonding wire W ₄ is are connected to the test pin T ₄ further by internal wiring C _4. In this case, the input
Protection diodes Q _p5, Q _n5 is provided to prevent the overvoltage of the power pad P _3, the protection diode Q _p7, Q _n7 is provided to prevent over-voltage of the input pad P _4.

[0016] Therefore, when performing open test the input and output pins T ₁ of the input <br/> pads P ₁ and the substrate 2 of the semiconductor chip 11 of FIG. 2, the test pin T ₃ to a high level, the test pins T _4, the power supply VCC, the GND and 0V, appropriate voltage for example 2~3V to the input and output pins T ₁ (transistor Q _n4
(When the on-resistance of the substrate is about 3 KΩ). As a result, the transistor Q _n4 is turned on, and the transistor Q _n4 is turned on.
Turn off _n6 . As a result, if there is no abnormality between the input and output pins T ₁ of the input-output pads P ₁ and the substrate 2 of the semiconductor chip 1-1, the transistor Q _n4 drain - the current example, about 1mA flows between the source, input and output It can be observed along the route of pin T ₁ → input pin P ₁ ′ → bonding wire W ₁ → input pad P ₁ → transistor Q _n4 → GND. That is, since the transistor _Qn6 is off, an open test of only the semiconductor chip 1-1 can be performed.

[0017] Similarly, when performing open test the input and output pins T ₁ of the output <br/> pad P ₂ and the substrate 2 of the semiconductor chip 1-2 of FIG. 2, the test pin T ₄ to a high level, the test The pin T ₃ , the power supplies VCC and GND are set to 0 V, and an appropriate voltage, for example, 2 to ₃ V is applied to the input / output pin T ₁ . As a result, the transistor Q _n6 is turned on and the transistor Q _n4 is turned off. As a result, the semiconductor chip 1-2 is ejected.
If there is no abnormality between the input and output pins T ₁ of the power pad P ₂ and the substrate 2, the drain of the transistor Q _n6 - the current example, about 1mA flows between the source, input pins T ₁ → output path <br/> head P ₂ '→ bonding wire W ₂ → output pad P ₂ →
It can be observed on the path of the transistor Q _n6 → GND. That is, since the transistor _Qn4 is off, an open test of only the semiconductor chip 1-2 can be performed. In general, a semiconductor manufacturer performs a semiconductor device test using an LSI tester. LSI
The tester has, as its basic functions, simultaneous application of voltage application to each terminal and measurement of the current flowing through the terminal. Therefore, this test can be performed without adding a special test device.

[0018] Considering the case of performing open test in the test circuit shown in FIG. 7 the multi-chip semiconductor device in FIG. 2, the test pin T ₃ to a high level, the test pin T ₄ and 0V, also the power supply VCC and GND at 0V
And Connect one state to the diode bridge circuit terminal C and output pins T ₁ of the shown in FIG. 7 (A), by applying a degree -2V to the terminal A, supplying a constant current of about 300μA terminal B, and between C (Reference: FIG. 7B). As a result, FIG.
Input pads P of the input and output pins T ₁ and the semiconductor chip 1-1
If there is no abnormality between the _1, the transistor Q _n4 is on, the voltage at the terminal of the voltage, i.e. the diode bridge circuit of the input and output pins T ₁ becomes 0V. On the other hand, if the open between the input and output pins T ₁ to the input pad P ₁ in FIG. 2, the voltage of the terminal C of the voltage, i.e. the diode bridge circuit of the input and output pins T ₁ is a voltage clogging -2V terminal A .
Thus, input pads P of the input and output pins T ₁ and the semiconductor chip 1-1 by the voltage of the terminal C of the diode bridge circuit is determined that there 0V, in any of -2V
Test connection with ₁ .

Similarly, the test pin T _{4 is set} to a high level, the test pin T _{3 is set} to 0 V, and the power supply VCC and GND are
Is 0 V, the input / output pin T ₁ and the output pad P _{2 of the} semiconductor chip 1-2 are determined by determining whether the voltage of the terminal C of the diode bridge circuit is at 0 V or −2 V. Connection test with

FIG. 3 shows a second embodiment of the multichip semiconductor device according to the present invention. 3, an N-channel transistor Q _n2 as a protection diode in FIG.
Allowed connection to the gate to the output pad P _3, in which was allowed also used the N-channel transistor Q _n4 in FIG. Thereby, the number of elements of the semiconductor chip 1-1 can be reduced.
In the case of a protection diode included in the output buffer (Q _P3 , Q _n3 ) (see FIG. 6), such a protection diode cannot be used as a switching transistor. The open test operation of the multi-chip semiconductor device of FIG. 3 is exactly the same as the open test operation of the multi-chip semiconductor device of FIG.

FIG. 4 is a diagram showing a test flow of the multi-chip semiconductor device. First, in step 401,
A short test is performed as in the case of the single-chip semiconductor device. In this case, all test pins such as T ₃ , T ₄
Is set to 0V. As a result, if a short circuit is detected, the process proceeds to a repair step, and if a short circuit is not detected, the process proceeds to step 402.

In step 402, an open test is performed as in the case of the single-chip semiconductor device. Also in this case, all test pins, for example, T ₃ and T ₄ are set to 0V. As a result, when all the connections between the input / output pins of the board and the pads of the plurality of semiconductor chips connected to the input / output pins are open, the connection is detected as a failure, and the input / output pins of the board and the input / output pins are not detected. If the connection with the pad of one semiconductor chip connected to the output pin is open, it is detected as defective. As a result, if an open is detected, the process proceeds to a repair step. If no open is detected, the process proceeds to step 403.

In step 403, an open test is performed using test pins provided by the present invention, for example, T ₃ and T ₄ . That is, by setting a specific test pin to a high level and setting the other test pins to 0 V, a specific connection is established between the input / output pins of the substrate and the pads of a plurality of semiconductor chips connected to the input / output pins. Perform an open test in. As a result, if an open is detected, the procedure proceeds to a repair step. If no open is detected, the procedure proceeds to a function test.

[0024]

As described above, according to the present invention, an open test can be performed on each of a plurality of semiconductor chips mounted on a multi-chip semiconductor device.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a basic configuration of the present invention.

FIG. 2 is a circuit diagram showing a first embodiment of the multichip semiconductor device according to the present invention.

FIG. 3 is a circuit diagram showing a second embodiment of the multichip semiconductor device according to the present invention.

FIG. 4 is a test flow of the multichip semiconductor device according to the present invention.

FIG. 5 is a circuit diagram showing a conventional single-chip semiconductor device.

FIG. 6 is a sectional view showing the output buffer of FIG. 5;

FIG. 7 is a circuit diagram showing an open / short test circuit.

FIG. 8 is a diagram showing a conventional multi-chip semiconductor device.

FIG. 9 is a detailed partial circuit diagram of FIG. 8;

[Explanation of symbols]

1, 1-1, 1-2 ... semiconductor chip 2 ... substrate Q _P1 , Q _n1 ... input buffer Q _P2 , Q _n2 ... protection diode Q _P3 , Q _n3 ... output buffer Q _n4 ... switching transistor Q _P5 , Q _n5 ... protection diodes Q _n6 ... switching transistor Q _P7, Q _n7 ... protection diode P _1, P ₁ '... input pad _{W 1, W 2, W 3} , W 4 ... bonding wire P _2, P _2' ... output pad C _1, C ₂ , C ₃ , C ₄ ... internal wiring T ₁ ... input pin (input / output pin) T ₂ ... output pin T ₃ , T ₄ ... test pin

Claims (8)

(57) [Claims] A plurality of semiconductor chips (1-1, 1-2)
In a multi-chip semiconductor device having the semiconductor chip mounted on a single substrate (2), wherein each of the semiconductor chips is connected to a first chip connected to an internal circuit.
Head and (P _1, P _2), said first pad and a power supply line (GN
D) and a switching transistor (Q
_n4, and Q _n6), and a first additional input pad for controlling the switching transistor (P _3, P _4), the substrate is connected the to the first pad of each semiconductor chip A second pad (P ₁ ′, P ₂ ′) and a second additional input pad (P ₃ ′, P ₄ ′) connected to the first additional input pad of each semiconductor chip; The second pad (P
₁ ', P _2' and output pins connected to) (T _1), wherein the
Test pins connected to the two additional input pads (T ₃ ,
T ₄ ). 2. The multi-chip semiconductor device according to claim 1, wherein said switching transistor also serves as an overvoltage protection diode. 3. A plurality of semiconductor chips (1-1, 1-2).
In multi-chip devices mounted on a single substrate (2), each semiconductor chip, the first path <br/> head connected to the internal circuit (P _1, P _2), said first 1 pad and power supply line (GN
D) and a switching transistor (Q
_n4, and Q _n6), a first additional input pad (P _3, P ₄ connected to the gate of the switching transistor); and a, the substrate is bonded to the first pad of each semiconductor chip The second path connected by wires (W ₁ , W ₂ )
Head _{(P 1 ', P 2'} ) , a second additional input said connected by a first bonding wire with <br/> additive input pads of the semiconductor chips (W _3, W ₄₎ Pad (P ₃ ', P ₄ ')
And an input / output pin (T ₁ ) connected to the second pad.
And test pins (T ₃ , C ₃ ) connected to the second additional input pad by a wiring pattern (C ₃ , C ₄ ).
T ₄ ). 4. The multi-chip semiconductor device according to claim 3, wherein said switching transistor also serves as an overvoltage protection diode. 5. A plurality of semiconductor chips (1-1, 1-2)
In multi-chip devices mounted on a single substrate (2), each semiconductor chip includes a buffer (Q _p1, Q _n1), and overvoltage protection diode (Q _p2, Q _n2), the buffer and the overvoltage The first pad (P
_1, P ₂₎ and the switching transistor (Q _n4 connected between said first pad and the power supply line (GND),
Q _n6 ), and a first additional input pad (P ₃ , P ₄ ) connected to the gate of the switching transistor, wherein the substrate is connected to a first pad of each of the semiconductor chips. A second pad (P ₁ ′, P ₂ ′), a second additional input pad (P ₃ ′, P ₄ ′) connected to a first additional input pad of each semiconductor chip; input and output pins connected to the second pad (T _1), and characterized by comprising the said connected test pin to a second additional input <br/> pads (T _3, T ₄₎ Multi-chip semiconductor device. 6. A plurality of semiconductor chips (1-1, 1-2).
Is mounted on one substrate (2), wherein each of the semiconductor chips comprises a buffer (Q _p1 , Q _n1 )
A first pad (P ₁ , P ₂ ) connected to a buffer ;
A switching transistor (Q _n4 , Q _n6 ) connected between the first pad and a power supply line (GND) and acting as an overvoltage protection diode when in an off state; and a first transistor for controlling the switching transistor . comprising and additional input <br/> pads (P _3, P _4), the substrate, a second pad connected to the first pad of each semiconductor chip _{(P 1 ', P 2'} ) If, the input-output pins connected to the second pad <br/> (T _1), wherein each semiconductor chip
Second additional input pad connected to the first additional input pad of the
Multichip characterized input pad _{(P 3 ', P 4'} ) and, by including the test pins connected to the additional input pad <br/> de of said 2 (T _3, T ₄₎ Semiconductor device. 7. A plurality of semiconductor chips (1-1, 1-2)
In multi-chip devices mounted on a single substrate (2), each semiconductor chip, and Batsufa (Q _p1, Q _n1), and overvoltage protection diode (Q _p2, G _n2), the Batsufa and the overvoltage a first pad connected to a protection diode (P _1, P _2), connected to the switching transistor (Q _n4, Q between the first pad and the power supply line (GND)
_n6 ) for controlling the switching transistor
And a first additional input pad (P _3, P _4), said substrate, said second pad connected by the semiconductor chip first bonding wires to pads (W _1, W ₂₎ < br /> de (P ₁ ', P _2') and said respective semiconductor chip first second additional input pad connected by bonding wires to an additional input pad (W _3, W ₄₎ of (P ₃ ', P _4' and),
An input / output pin (T ₁ ) connected to the second pad ;
The second additional input pad has a wiring pattern '(C ₃ ,
A multi-chip semiconductor device comprising: test pins (T ₃ , T ₄ ) connected by C ₄ ). 8. A plurality of semiconductor chips (1-1, 1-2).
Is mounted on one substrate (2), wherein each of the semiconductor chips comprises a buffer (Q _p1 , Q _n1 )
A first pad (P ₁ , P ₂ ) connected to a buffer ;
A switching transistor (Q _n4 , Q _n6 ) connected between the first pad and a power supply line (GND) and acting as an overvoltage protection diode when in an off state; and a first transistor for controlling the switching transistor . comprising and additional input <br/> pads (P _3, P _4), the substrate, Bonn to the first pad of each semiconductor chip
Welding wire (W _1, W ₂₎ second Pas <br/> head connected by _{(P 1 ', P 2'} ) and, connected to the second pad
A second pin (T ₁ ) connected to the second pad
Second additional input pad _{(P 3 ', P 4'} ) and, by including the connected test pin biasing <br/> additive input pad of said 2 (T _3, T ₄₎ A multi-chip semiconductor device characterized by the following.